ARM: pantheon: enable dcache by default
PATCH 1/1 ARM: pantheon: enable dcache by default
Marvell 88SV331xV5 has its specific arm cp15 opcode, which could flush out whole dcache by only one line of asm code.
--- arch/arm/cpu/arm926ejs/pantheon/cpu.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-)
arch/arm/cpu/arm926ejs/pantheon/cpu.c +14 -0
@@ -105,3 +105,17 @@ void i2c_clk_enable(void) { }#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in start.S */ +dcache_enable (); +} + +void flush_cache (unsigned long start,unsigned long size) +{ +/* clean & invalidate all D cache */ + asm("mcr p15, 0, %0, c7, c14, 0" : :"r" (0 )); +} +#endif
Signature · 1 line
1.7.0.4
PATCH 1/1 ARM: pantheon: enable dcache by default
Quoted 9 lines
-----Original Message-----
From: Lei Wen [mailto:leiwen at marvell.com]
Sent: Wednesday, October 05, 2011 8:43 PM
To: Prafulla Wadaskar; u-boot at lists.denx.de
Subject: [PATCH] ARM: pantheon: enable dcache by defaultMarvell 88SV331xV5 has its specific arm cp15 opcode, which could
I think this will be applicable to all SoC those fall under this core. So we should modify arch/arm/include/asm/cache.h for this.
Quoted 20 lines
flush out whole dcache by only one line of asm code.
Signed-off-by Lei Wen <[email protected]>--- arch/arm/cpu/arm926ejs/pantheon/cpu.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-)arch/arm/cpu/arm926ejs/pantheon/cpu.c +4
-0@@ -105,3 +105,17 @@ void i2c_clk_enable(void) { }#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{
arch/arm/cpu/arm926ejs/pantheon/cpu.c void i2c_clk_enable(void) · line 121
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arch/arm/cpu/arm926ejs/pantheon/cpu.c +10
-0+/* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} + +void flush_cache (unsigned long start,unsigned long size) +{ +/* clean & invalidate all D cache */ + asm("mcr p15, 0, %0, c7, c14, 0" : :"r" (0 )); +} +#endif
Otherwise ack for this change
Regards..
Prafulla ..
Quoted 2 lines
--
1.7.0.4
PATCH 1/1 ARM: pantheon: enable dcache by default
Hi Prafulla,
Quoted 8 lines · Prafulla Wadaskar
Quoted 8 lines
-----Original Message-----
From: Lei Wen [mailto:leiwen at marvell.com]
Sent: Wednesday, October 05, 2011 8:43 PM
To: Prafulla Wadaskar; u-boot at lists.denx.de
Subject: [PATCH] ARM: pantheon: enable dcache by default
Quoted 4 lines
Quoted 1 line
Marvell 88SV331xV5 has its specific arm cp15 opcode, which could
I think this will be applicable to all SoC those fall under this core. So we should modify
arch/arm/include/asm/cache.hfor this.
I modify my original one patch into three small patch series. And put the op code place as you suggested, please help re-check it.
Quoted 25 lines
Quoted 25 lines
flush out whole dcache by only one line of asm code.
Signed-off-by Lei Wen <[email protected]>---
?arch/arm/cpu/arm926ejs/pantheon/cpu.c | ? 14 ++++++++++++++ ?1 files changed, 14 insertions(+), 0 deletions(-)arch/arm/cpu/arm926ejs/pantheon/cpu.c +0
-0@@ -105,3 +105,17 @@ void i2c_clk_enable(void) ?{ ?}?#endif
arch/arm/cpu/arm926ejs/pantheon/cpu.c +8
-0+ +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ + ? ? /* Enable D-cache. I-cache is already enabled in start.S */ + ? ? dcache_enable(); +} +
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arch/arm/cpu/arm926ejs/pantheon/cpu.c void i2c_clk_enable(void) · line 121
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arch/arm/cpu/arm926ejs/pantheon/cpu.c +6
-0+void ?flush_cache(unsigned long start, unsigned long size) +{ + ? ? /* clean & invalidate all D cache */ + ? ? asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0)); +} +#endif Otherwise ack for this change
Thanks,
Lei
cover enable dcache for pantheon and armada100
In reply to Lei WenThis patch seris use Marvell its own special op code to flush the dcache
Lei Wen (3):
ARM: add special dcache flush op code for 88SV331xV5
ARM: pantheon: enable dcache by default
ARM: armada100: enable dcache by default
arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ arch/arm/lib/cache.c | 5 +++++ 3 files changed, 21 insertions(+), 0 deletions(-)
cover enable dcache for pantheon and armada100
Hi Prafulla,
Quoted 7 lines · Lei Wen
This patch seris use Marvell its own special op code to flush the dcache
Lei Wen (3):
?ARM: add special dcache flush op code for 88SV331xV5 ?ARM: pantheon: enable dcache by default ?ARM: armada100: enable dcache by default
Quoted 5 lines
?arch/arm/cpu/arm926ejs/armada100/cpu.c | ? ?8 ++++++++ ?arch/arm/cpu/arm926ejs/pantheon/cpu.c ?| ? ?8 ++++++++ ?arch/arm/lib/cache.c ? ? ? ? ? ? ? ? ? | ? ?5 +++++?3 files changed, 21 insertions(+), 0 deletions(-)
Do you have any comment over this patch series?
Thanks,
Lei
cover enable dcache for pantheon and armada100
Le 18/10/2011 17:02, Lei Wen a ?crit :
Quoted 10 lines
Hi Prafulla,
Quoted 7 lines · Lei Wen
This patch seris use Marvell its own special op code to flush the dcache
Lei Wen (3):
ARM: add special dcache flush op code for 88SV331xV5
ARM: pantheon: enable dcache by default
ARM: armada100: enable dcache by default
Quoted 7 lines
Quoted 5 lines
arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ arch/arm/lib/cache.c | 5 +++++ 3 files changed, 21 insertions(+), 0 deletions(-)Do you have any comment over this patch series?
Prafulla, will you take this series in?
Amicalement,
Signature · 1 line
Albert.
cover enable dcache for pantheon and armada100
Quoted 29 lines
-----Original Message-----
From: Albert ARIBAUD [mailto:albert.u.boot at aribaud.net]
Sent: Wednesday, November 09, 2011 1:37 AM
To: Prafulla Wadaskar
Cc: u-boot at lists.denx.de; Lei Wen
Subject: Re: [U-Boot] [PATCH 0/3] enable dcache for pantheon and armada100Le 18/10/2011 17:02, Lei Wen a ?crit :
Quoted 3 lines
Hi Prafulla,
On Sat, Oct 8, 2011 at 9:59 PM, Lei Wen<[email protected]>
Quoted 1 line · wrote:
Quoted 1 line
This patch seris use Marvell its own special op code to
flush the dcache
Quoted 12 lines
Quoted 11 lines
Lei Wen (3):
ARM: add special dcache flush op code for 88SV331xV5
ARM: pantheon: enable dcache by default
ARM: armada100: enable dcache by defaultarch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ arch/arm/lib/cache.c | 5 +++++ 3 files changed, 21 insertions(+), 0 deletions(-)
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Do you have any comment over this patch series?
Prafulla, will you take this series in?
Yes, I will do it
Regards..
Prafulla . . .
Quoted 4 lines
Amicalement,
--
Albert.
PATCH 1/3 ARM: add special dcache flush op code for 88SV331xV5
In reply to Lei WenMarvell 88SV331xV5 has its specific arm cp15 opcode, which could flush out whole dcache by only one line of asm code.
--- arch/arm/lib/cache.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
arch/arm/lib/cache.c +5 -0
@@ -33,11 +33,16 @@ void __flush_cache(unsigned long start, unsigned long size)arm1136_cache_flush ();#endif #ifdef CONFIG_ARM926EJS +#ifdef CONFIG_SHEEVA_88SV331xV5 +/* clean & invalidate all D cache */ + asm("mcr p15, 0, %0, c7, c14, 0" : :"r" (0 )); +#else /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : :"memory" );/* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : :"r" (0 ));#endif +#endif return ; }void flush_cache (unsigned long start,unsigned long size)
Signature · 1 line
1.7.0.4
PATCH 2/3 ARM: pantheon: enable dcache by default
In reply to Lei Wen--- arch/arm/cpu/arm926ejs/pantheon/cpu.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
arch/arm/cpu/arm926ejs/pantheon/cpu.c +8 -0
@@ -88,3 +88,11 @@ void i2c_clk_enable(void) { }#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in arch_cpu_init */ +dcache_enable (); +} +#endif
Signature · 1 line
1.7.0.4
PATCH 3/3 ARM: armada100: enable dcache by default
In reply to Lei Wen--- arch/arm/cpu/arm926ejs/armada100/cpu.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
arch/arm/cpu/arm926ejs/armada100/cpu.c +8 -0
@@ -106,3 +106,11 @@ void i2c_clk_enable(void) { }#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches (void ) +{ +/* Enable D-cache. I-cache is already enabled in arch_cpu_init */ +dcache_enable (); +} +#endif
Signature · 1 line
1.7.0.4