spi/pl022: only enable RX interrupts when TX is complete
Subsystems (2)
PATCH 1/6 spi/pl022: only enable RX interrupts when TX is complete
From: Chris Blair <[email protected]>
For interrupt mode transfers, start with only TX interrupts enabled to reduce the overall number of interrupts received. Once TX is complete, enable RX interrupts to complete the transfer.
Signed-off-by Chris Blair <[email protected]>
Signed-off-by Linus Walleij <[email protected]>
--- drivers/spi/spi-pl022.c | 14 +++++++++----- 1 files changed, 9 insertions(+), 5 deletions(-)
drivers/spi/spi-pl022.c +9 -5
@@ -1244,9 +1244,9 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)if ((pl022->tx == pl022->tx_end) && (flag ==0 )) { flag =1 ; -/* Disable Transmit interrupt */ -writew (readw (SSP_IMSC (pl022->virtbase)) & - (~SSP_IMSC_MASK_TXIM ), +/* Disable Transmit interrupt, enable receive interrupt */ +writew ((readw (SSP_IMSC (pl022->virtbase)) & + ~SSP_IMSC_MASK_TXIM ) |SSP_IMSC_MASK_RXIM ,SSP_IMSC (pl022->virtbase)); }
@@ -1379,12 +1379,16 @@ static void pump_transfers(unsigned long data) } err_config_dma: -writew (ENABLE_ALL_INTERRUPTS ,SSP_IMSC (pl022->virtbase)); +/* enable all interrupts except RX */ +writew (ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM ,SSP_IMSC (pl022->virtbase)); }static void do_interrupt_dma_transfer (struct pl022 *pl022) { -u32 irqflags =ENABLE_ALL_INTERRUPTS ; +/* default is to enable all interrupts except RX - +* this will be enabled once TX is complete +*/ +u32 irqflags =ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM ;/* Enable target chip */ pl022->cur_chip->cs_control (SSP_CHIP_SELECT );
Signature · 1 line
1.7.3.2
PATCH 1/6 spi/pl022: only enable RX interrupts when TX is complete
drivers/spi/spi-pl022.c static void pump_transfers(unsigned long data) · line 1390
Quoted 3 lines · Linus WALLEIJ
drivers/spi/spi-pl022.c +3
-0+/* default is to enable all interrupts except RX - +* this will be enabled once TX is complete +*/
Other than fixing this multiline comment, everything other looks fine.
Reviewed-by Viresh Kumar <[email protected]>
Signature · 1 line
viresh