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ARM: davinci: psc: fix incorrect mask

PATCH New Sekhar Nori 2 participants 5 messages Nov 14, 2011 – Nov 15, 2011

Subsystems (3)
Arm (32-bit) Arm sub-architectures TI DaVinci machine support
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Sekhar Nori

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#0 lore raw

PATCH v4 1/4 ARM: davinci: psc: fix incorrect mask

From: Murali Karicheri <[email protected]>

There are 5 LSB bits defined in PDSTAT and the code currently uses a mask of 1 bit to check the status.

Use a proper mask per the hardware specification. While at it, use a #define for the mask to improve readability.

Reviewed-by Sergei Shtylyov <[email protected]>
Signed-off-by Murali Karicheri <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
---
 arch/arm/mach-davinci/include/mach/psc.h |    1 +
 arch/arm/mach-davinci/psc.c              |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)
arch/arm/mach-davinci/include/mach/psc.h +1 -0
index fa59c09..8bf279a 100644
@@ -244,6 +244,7 @@
 #define PSC_STATE_ENABLE	3
 
 #define MDSTAT_STATE_MASK	0x3f
+#define PDSTAT_STATE_MASK	0x1f
 #define MDCTL_FORCE		BIT(31)
 
 #ifndef __ASSEMBLER__
arch/arm/mach-davinci/psc.c +1 -1
index 1fb6bdf..a0e1770 100644
@@ -80,7 +80,7 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 	__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
 
 	pdstat = __raw_readl(psc_base + PDSTAT);
-	if ((pdstat & 0x00000001) == 0) {
+	if ((pdstat & PDSTAT_STATE_MASK) == 0) {
 		pdctl1 = __raw_readl(psc_base + PDCTL1);
 		pdctl1 |= 0x1;
 		__raw_writel(pdctl1, psc_base + PDCTL1);
Signature · 1 line
1.6.2.4
author
#1 lore raw

PATCH v4 2/4 ARM: davinci: psc: fix incorrect offsets

From: Murali Karicheri <[email protected]>

Seperate PDSTAT and PDCTL registers are defined for domain 0 and domain 1 where as the code always reads the domain 0 PDSTAT register and domain 1 PDCTL register.

Fix this issue. While at it, introduce usage of macros for register masks to improve readability.

Reviewed-by Sergei Shtylyov <[email protected]>
Signed-off-by Murali Karicheri <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>
---
 arch/arm/mach-davinci/include/mach/psc.h |    4 +++-
 arch/arm/mach-davinci/psc.c              |   16 ++++++++--------
 2 files changed, 11 insertions(+), 9 deletions(-)
arch/arm/mach-davinci/include/mach/psc.h +3 -1
index 8bf279a..8bc3fc2 100644
@@ -233,7 +233,7 @@
 #define PTCMD		0x120
 #define PTSTAT		0x128
 #define PDSTAT		0x200
-#define PDCTL1		0x304
+#define PDCTL		0x300
 #define MDSTAT		0x800
 #define MDCTL		0xA00
 

@@ -246,6 +246,8 @@
 #define MDSTAT_STATE_MASK	0x3f
 #define PDSTAT_STATE_MASK	0x1f
 #define MDCTL_FORCE		BIT(31)
+#define PDCTL_NEXT		BIT(1)
+#define PDCTL_EPCGOOD		BIT(8)
 
 #ifndef __ASSEMBLER__
arch/arm/mach-davinci/psc.c +8 -8
index a0e1770..d7e210f 100644
@@ -52,7 +52,7 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 		unsigned int id, bool enable, u32 flags)
 {
-	u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
+	u32 epcpr, ptcmd, ptstat, pdstat, pdctl, mdstat, mdctl;
 	void __iomem *psc_base;
 	struct davinci_soc_info *soc_info = &davinci_soc_info;
 	u32 next_state = PSC_STATE_ENABLE;

@@ -79,11 +79,11 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 		mdctl |= MDCTL_FORCE;
 	__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
 
-	pdstat = __raw_readl(psc_base + PDSTAT);
+	pdstat = __raw_readl(psc_base + PDSTAT + 4 * domain);
 	if ((pdstat & PDSTAT_STATE_MASK) == 0) {
-		pdctl1 = __raw_readl(psc_base + PDCTL1);
-		pdctl1 |= 0x1;
-		__raw_writel(pdctl1, psc_base + PDCTL1);
+		pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
+		pdctl |= PDCTL_NEXT;
+		__raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
 
 		ptcmd = 1 << domain;
 		__raw_writel(ptcmd, psc_base + PTCMD);

@@ -92,9 +92,9 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
 			epcpr = __raw_readl(psc_base + EPCPR);
 		} while ((((epcpr >> domain) & 1) == 0));
 
-		pdctl1 = __raw_readl(psc_base + PDCTL1);
-		pdctl1 |= 0x100;
-		__raw_writel(pdctl1, psc_base + PDCTL1);
+		pdctl = __raw_readl(psc_base + PDCTL + 4 * domain);
+		pdctl |= PDCTL_EPCGOOD;
+		__raw_writel(pdctl, psc_base + PDCTL + 4 * domain);
 	} else {
 		ptcmd = 1 << domain;
 		__raw_writel(ptcmd, psc_base + PTCMD);
Signature · 1 line
1.6.2.4
author
#2 lore raw

PATCH 3/4 ARM: davinci: dm646x does not have a DSP domain

Fix the incorrect classification of DSP clock into a seperate DSP domain on DM646x.

Per the reference guide (http://www.ti.com/lit/ug/spruep9e/spruep9e.pdf)
there is only one "AlwaysON" power domain on DM6467.

Signed-off-by Sekhar Nori <[email protected]>

---
This patch has not been tested on DM6467 yet.

 arch/arm/mach-davinci/dm646x.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)
arch/arm/mach-davinci/dm646x.c +0 -1
index b0c350a..d73f9f9 100644
@@ -161,7 +161,6 @@ static struct clk dsp_clk = {
 	.name = "dsp",
 	.parent = &pll1_sysclk1,
 	.lpsc = DM646X_LPSC_C64X_CPU,
-	.flags = PSC_DSP,
 	.usecount = 1,			/* REVISIT how to disable? */
 };
Signature · 1 line
1.6.2.4
author
#3 lore raw

PATCH v4 4/4 ARM: davinci: add support for multiple power domains

From: Murali Karicheri <[email protected]>

On a new SoC based on DaVinci, there are multiple power domains similar to that in C6670 (c6x). Currently the clock module assumes that there are only two power domains (0 and 1).

This patch removes this restriction to allow porting on to the new SoC.

Reviewed-by Sergei Shtylyov <[email protected]>
Signed-off-by Murali Karicheri <[email protected]>
Signed-off-by Sekhar Nori <[email protected]>

---
This patch has not been tested on DM644x yet.

 arch/arm/mach-davinci/clock.c  |   13 +++----------
 arch/arm/mach-davinci/clock.h  |   10 +++++-----
 arch/arm/mach-davinci/dm644x.c |    4 ++--
 3 files changed, 10 insertions(+), 17 deletions(-)
arch/arm/mach-davinci/clock.c +3 -10
index 0086113..008772e 100644
@@ -31,19 +31,12 @@ static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
 static DEFINE_SPINLOCK(clockfw_lock);
 
-static unsigned psc_domain(struct clk *clk)
-{
-	return (clk->flags & PSC_DSP)
-		? DAVINCI_GPSC_DSPDOMAIN
-		: DAVINCI_GPSC_ARMDOMAIN;
-}
-
 static void __clk_enable(struct clk *clk)
 {
 	if (clk->parent)
 		__clk_enable(clk->parent);
 	if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
-		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+		davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
 				true, clk->flags);
 }
 

@@ -53,7 +46,7 @@ static void __clk_disable(struct clk *clk)
 		return;
 	if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
 	    (clk->flags & CLK_PSC))
-		davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
+		davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc,
 				false, clk->flags);
 	if (clk->parent)
 		__clk_disable(clk->parent);

@@ -237,7 +230,7 @@ static int __init clk_disable_unused(void)
 
 		pr_debug("Clocks: disable unused %s\n", ck->name);
 
-		davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
+		davinci_psc_config(ck->domain, ck->gpsc, ck->lpsc,
 				false, ck->flags);
 	}
 	spin_unlock_irq(&clockfw_lock);
arch/arm/mach-davinci/clock.h +5 -5
index a705f36..46f0f1b 100644
@@ -93,6 +93,7 @@ struct clk {
 	u8			usecount;
 	u8			lpsc;
 	u8			gpsc;
+	u8			domain;
 	u32			flags;
 	struct clk              *parent;
 	struct list_head	children; 	/* list of children */

@@ -107,11 +108,10 @@ struct clk {
 /* Clock flags: SoC-specific flags start at BIT(16) */
 #define ALWAYS_ENABLED		BIT(1)
 #define CLK_PSC			BIT(2)
-#define PSC_DSP			BIT(3) /* PSC uses DSP domain, not ARM */
-#define CLK_PLL			BIT(4) /* PLL-derived clock */
-#define PRE_PLL			BIT(5) /* source is before PLL mult/div */
-#define PSC_SWRSTDISABLE	BIT(6) /* Disable state is SwRstDisable */
-#define PSC_FORCE		BIT(7) /* Force module state transtition */
+#define CLK_PLL			BIT(3) /* PLL-derived clock */
+#define PRE_PLL			BIT(4) /* source is before PLL mult/div */
+#define PSC_SWRSTDISABLE	BIT(5) /* Disable state is SwRstDisable */
+#define PSC_FORCE		BIT(6) /* Force module state transtition */
 
 #define CLK(dev, con, ck) 	\
 	{			\
arch/arm/mach-davinci/dm644x.c +2 -2
index 555ff5b..f38c4bb 100644
@@ -130,7 +130,7 @@ static struct clk dsp_clk = {
 	.name = "dsp",
 	.parent = &pll1_sysclk1,
 	.lpsc = DAVINCI_LPSC_GEM,
-	.flags = PSC_DSP,
+	.domain = DAVINCI_GPSC_DSPDOMAIN,
 	.usecount = 1,			/* REVISIT how to disable? */
 };
 

@@ -145,7 +145,7 @@ static struct clk vicp_clk = {
 	.name = "vicp",
 	.parent = &pll1_sysclk2,
 	.lpsc = DAVINCI_LPSC_IMCOP,
-	.flags = PSC_DSP,
+	.domain = DAVINCI_GPSC_DSPDOMAIN,
 	.usecount = 1,			/* REVISIT how to disable? */
 };
Signature · 1 line
1.6.2.4
#4 lore raw

PATCH v4 2/4 ARM: davinci: psc: fix incorrect offsets

In reply to Sekhar Nori

Hello.

Quoted 21 lines · Sekhar Nori

From: Murali Karicheri<[email protected]>

Seperate PDSTAT and PDCTL registers are defined for domain 0 and domain 1 where as the code always reads the domain 0 PDSTAT register and domain 1 PDCTL register.

Fix this issue. While at it, introduce usage of macros for register masks to improve readability.

Reviewed-by Sergei Shtylyov<[email protected]>
Signed-off-by Murali Karicheri<[email protected]>
Signed-off-by Sekhar Nori<[email protected]>
---
  arch/arm/mach-davinci/include/mach/psc.h |    4 +++-
  arch/arm/mach-davinci/psc.c              |   16 ++++++++--------
  2 files changed, 11 insertions(+), 9 deletions(-)
arch/arm/mach-davinci/include/mach/psc.h +0 -0
index 8bf279a..8bc3fc2 100644

[...]

arch/arm/mach-davinci/include/mach/psc.h line 249

Quoted 5 lines
arch/arm/mach-davinci/include/mach/psc.h +1 -0
@@ -246,6 +246,8 @@
  #define MDSTAT_STATE_MASK	0x3f
  #define PDSTAT_STATE_MASK	0x1f
  #define MDCTL_FORCE		BIT(31)
+#define PDCTL_NEXT		BIT(1)

BIT(0) actually.

WBR, Sergei