Add more framework to OMAP3 SPL, port more boards

PATCH New Tom Rini 3 participants 28 messages Nov 18, 2011 – Nov 29, 2011 Arm (32-bit)

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Tom Rini

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2011-11-18 22:47 UTC #0 lore raw

v4 cover Add more framework to OMAP3 SPL, port more boards

Hey all,

This is related to, but a bit different from the RFT thread I made with beagleboard SPL patches. I've incorporated the feedback about splitting the changes up a lot more and after talking with Scott Wood on IRC after the ML thread, I've created an omap3 specific file with the NAND related stuff these boards need (since it would have gotten very big for what's really needed here at this stage). The series is checkpatch.pl clean.

What we have in patches 1-8 is bugfixing and cleanup of the memory code. It's worth noting that without these changes we do some very 'funny' (read: wrong) things on some platforms like omap3_evm where we find 384MB memory when there's really only 256MB (and maybe 256 on the 128MB boards, not sure).

Patch 9 adds another hook for SDRC boards to be able to say what timings they have because on say beagle or omap3_evm, we have a few choices. We also convert devkit8000 here.

Patch 10 adds a new CONFIG (CONFIG_SPL_OMAP3_ID_NAND) and file so that OMAP3 boards which have a PoP chip for NAND/DDR can find out what they are and decide on timings based on that.

Patches 11 and 12 convert Beagleboard and OMAP3 EVM to SPL.

Patches 13 and 14 convert the am3517 evm and am3517 crane boards (which don't use SDRC but EMIF4) to SPL as well (given Ilya Yanok fixed a bug in <asm/arch-omap3/cpu.h> for emif4 this is just a mechanical change).

Changes in v4:
- Update this to match the feedback I'd incorporated before
- Update enable_gpmc_cs_config to not use so many magic values and explain the bitshifts.
- Add MCFG macro to calculate this value for the various DDR chips that are in use.
- Enhance the comments in <asm/arch-omap3/mem.h> to say to read the TRM to understand what all possible values are and bitshifts and update the comments about rfr_ctrl to explain why they aren't broken into values + shifts.
- The above three should cover all of Heiko Schocher's feedback.

Changes in v3:
- Rename CONFIG_SPL_OMAP3_POP_PROBE to CONFIG_SPL_OMAP3_ID_NAND at Igor's request (and function to identify_nand_chip).
- Drop an unused CONFIG_OMAP3_MICRON_DDR from all of the board config files

Changes in v2:
- Incorporate Igor Grinberg's feedback (except non-CodingStyle whitespacing).
- Move to ToT (so omap3_evm patch is reworked a good deal, others that touch <asm/arch-omap3/mem.h> reworked and use new macros when applicable)
- Fixed a few more typos and hardcoded values to defines while addressing Igor's feedback.

Signature · 1 line

Tom

Tom Rini

author

2011-11-18 22:47 UTC #1 lore raw

PATCH v4 1/14 omap3: mem: Comment enable_gpmc_cs_config more

Expand the "enable the config" comment to explain what the bit shifts are and define out two of the magic numbers.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/cpu/armv7/omap3/mem.c        |   12 +++++++++---
 arch/arm/include/asm/arch-omap3/mem.h |    4 ++++
 2 files changed, 13 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/omap3/mem.c +9 -3

index a01c303..2f1efea 100644
@@ -105,9 +105,15 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
 	writel(gpmc_config[3], &cs->config4);
 	writel(gpmc_config[4], &cs->config5);
 	writel(gpmc_config[5], &cs->config6);
-	/* Enable the config */
-	writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
-		(1 << 6)), &cs->config7);
+
+	/*
+	 * Enable the config.  size is the CS size and goes in
+	 * bits 11:8.  We set bit 6 to enable this CS and the base
+	 * address goes into bits 5:0.
+	 */
+	 writel((size << 8) | (GPMC_CS_ENABLE << 6) |
+				 ((base >> 24) & GPMC_BASEADDR_MASK),
+				 &cs->config7);
 	sdelay(2000);
 }

arch/arm/include/asm/arch-omap3/mem.h +4 -0

index db6a696..abf4e82 100644
@@ -259,6 +259,10 @@ enum {
 #define GPMC_SIZE_32M	0xE
 #define GPMC_SIZE_16M	0xF
 
+#define GPMC_BASEADDR_MASK	0x3F
+
+#define GPMC_CS_ENABLE		0x1
+
 #define SMNAND_GPMC_CONFIG1	0x00000800
 #define SMNAND_GPMC_CONFIG2	0x00141400
 #define SMNAND_GPMC_CONFIG3	0x00141400

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:47 UTC #2 lore raw

PATCH v4 2/14 OMAP3: Update SDRC dram_init to always call make_cs1_contiguous()

In reply to Tom Rini

We update the comment in make_cs1_contiguous() to be a little bit more clear (it's been copy/pasted from other silicons) and then explain in dram_init() why we need to always try this.

Note that in the previous behavior we were always calling this on boards that never had cs1 populated anyhow so making sure we do this always is fine and will correct things like omap3evm detecting an invalid amount of memory (384MB).

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/cpu/armv7/omap3/sdrc.c |   23 +++++++++++------------
 1 files changed, 11 insertions(+), 12 deletions(-)

arch/arm/cpu/armv7/omap3/sdrc.c +11 ~~-12~~

index 0dd1955..66ce33f 100644
@@ -58,10 +58,9 @@ u32 is_mem_sdr(void)
 
 /*
  * make_cs1_contiguous -
- *  - For es2 and above remap cs1 behind cs0 to allow command line
- *    mem=xyz use all memory with out discontinuous support compiled in.
- *    Could do it at the ATAG, but there really is two banks...
- *  - Called as part of 2nd phase DDR init.
+ * - When we have CS1 populated we want to have it mapped after cs0 to allow
+ *   command line mem=xyz use all memory with out discontinuous support
+ *   compiled in.  We could do it in the ATAG, but there really is two banks...
  */
 void make_cs1_contiguous(void)
 {

@@ -207,16 +206,16 @@ int dram_init(void)
 
 	size0 = get_sdr_cs_size(CS0);
 	/*
-	 * If a second bank of DDR is attached to CS1 this is
-	 * where it can be started.  Early init code will init
-	 * memory on CS0.
+	 * We always need to have cs_cfg point at where the second
+	 * bank would be, if present.  Failure to do so can lead to
+	 * strange situations where memory isn't detected and
+	 * configured correctly.  CS0 will already have been setup
+	 * at this point.
 	 */
-	if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
-		do_sdrc_init(CS1, NOT_EARLY);
-		make_cs1_contiguous();
+	make_cs1_contiguous();
+	do_sdrc_init(CS1, NOT_EARLY);
+	size1 = get_sdr_cs_size(CS1);
 
-		size1 = get_sdr_cs_size(CS1);
-	}
 	gd->ram_size = size0 + size1;
 
 	return 0;

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #3 lore raw

PATCH v4 3/14 OMAP3: Add a helper function to set timings in SDRC

In reply to Tom Rini

Since we go through the sequence to setup the SDRC timings more than once, break this logic out into its own function and have that function call mem_ok() to make sure the memory is usable.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/cpu/armv7/omap3/sdrc.c |  116 ++++++++++++++++++++------------------
 1 files changed, 61 insertions(+), 55 deletions(-)

arch/arm/cpu/armv7/omap3/sdrc.c +61 ~~-55~~

index 66ce33f..2756024 100644
@@ -108,14 +108,45 @@ u32 get_sdr_cs_offset(u32 cs)
 }
 
 /*
+ * write_sdrc_timings -
+ *  - Takes CS and associated timings and initalize SDRAM
+ *  - Test CS to make sure it's OK for use
+ */
+static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
+		u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
+{
+	/* Setup timings we got from the board. */
+	writel(mcfg, &sdrc_base->cs[cs].mcfg);
+	writel(ctrla, &sdrc_actim_base->ctrla);
+	writel(ctrlb, &sdrc_actim_base->ctrlb);
+	writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
+	writel(CMD_NOP, &sdrc_base->cs[cs].manual);
+	writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+	writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+	writel(mr, &sdrc_base->cs[cs].mr);
+
+	/*
+	 * Test ram in this bank
+	 * Disable if bad or not present
+	 */
+	if (!mem_ok(cs))
+		writel(0, &sdrc_base->cs[cs].mcfg);
+}
+
+/*
  * do_sdrc_init -
- *  - Initialize the SDRAM for use.
- *  - code called once in C-Stack only context for CS0 and a possible 2nd
- *    time depending on memory configuration from stack+global context
+ *  - Code called once in C-Stack only context for CS0 and with early being
+ *    true and a possible 2nd time depending on memory configuration from
+ *    stack+global context.
  */
 void do_sdrc_init(u32 cs, u32 early)
 {
 	struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
+	u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
+
+	sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
+	sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 
 	if (early) {
 		/* reset sdrc controller */

@@ -127,73 +158,48 @@ void do_sdrc_init(u32 cs, u32 early)
 		/* setup sdrc to ball mux */
 		writel(SDRC_SHARING, &sdrc_base->sharing);
 
-		/* Disable Power Down of CKE cuz of 1 CKE on combo part */
+		/* Disable Power Down of CKE because of 1 CKE on combo part */
 		writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
 				&sdrc_base->power);
 
 		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 		sdelay(0x20000);
-	}
-
 /* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
  * to prevent this to be build in non-SPL build */
 #ifdef CONFIG_SPL_BUILD
-	/* If we use a SPL there is no x-loader nor config header so we have
-	 * to do the job ourselfs
-	 */
-	if (cs == CS0) {
-		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-
-		/* General SDRC config */
-		writel(V_MCFG, &sdrc_base->cs[cs].mcfg);
-		writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl);
-
-		/* AC timings */
-		writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla);
-		writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb);
-
-		/* Initialize */
-		writel(CMD_NOP, &sdrc_base->cs[cs].manual);
-		writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
+		/*
+		 * If we use a SPL there is no x-loader nor config header so
+		 * we have to do the job ourselfs
+		 */
+
+		mcfg = V_MCFG;
+		ctrla = V_ACTIMA_165;
+		ctrlb = V_ACTIMB_165;
+		rfr_ctrl = V_RFR_CTRL;
+		mr = V_MR;
+
+		write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
+				rfr_ctrl, mr);
+#endif
 
-		writel(V_MR, &sdrc_base->cs[cs].mr);
 	}
-#endif
 
 	/*
-	 * SDRC timings are set up by x-load or config header
-	 * We don't need to redo them here.
-	 * Older x-loads configure only CS0
-	 * configure CS1 to handle this ommission
+	 * If we aren't using SPL we have been loaded by some
+	 * other means which may not have correctly initialized
+	 * both CS0 and CS1 (such as some older versions of x-loader)
+	 * so we may be asked now to setup CS1.
 	 */
 	if (cs == CS1) {
-		sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
-		sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
-		writel(readl(&sdrc_base->cs[CS0].mcfg),
-			&sdrc_base->cs[CS1].mcfg);
-		writel(readl(&sdrc_base->cs[CS0].rfr_ctrl),
-			&sdrc_base->cs[CS1].rfr_ctrl);
-		writel(readl(&sdrc_actim_base0->ctrla),
-			&sdrc_actim_base1->ctrla);
-		writel(readl(&sdrc_actim_base0->ctrlb),
-			&sdrc_actim_base1->ctrlb);
-
-		writel(CMD_NOP, &sdrc_base->cs[cs].manual);
-		writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-		writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
-		writel(readl(&sdrc_base->cs[CS0].mr),
-			&sdrc_base->cs[CS1].mr);
-	}
+		mcfg = readl(&sdrc_base->cs[CS0].mcfg),
+		rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
+		ctrla = readl(&sdrc_actim_base0->ctrla),
+		ctrlb = readl(&sdrc_actim_base0->ctrlb);
+		mr = readl(&sdrc_base->cs[CS0].mr);
+		write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
+				rfr_ctrl, mr);
 
-	/*
-	 * Test ram in this bank
-	 * Disable if bad or not present
-	 */
-	if (!mem_ok(cs))
-		writel(0, &sdrc_base->cs[cs].mcfg);
+	}
 }
 
 /*

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #4 lore raw

PATCH v4 4/14 OMAP3: Change mem_ok to clear again after reading back

In reply to Tom Rini

It's possible to need to call this function on the same banks multiple times so we want to be sure that 'pos A' is cleared out again at the end.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/cpu/armv7/omap3/mem.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/omap3/mem.c +1 -0

index 2f1efea..2fe5ac7 100644
@@ -86,6 +86,7 @@ u32 mem_ok(u32 cs)
 	writel(0x0, addr + 4);		/* remove pattern off the bus */
 	val1 = readl(addr + 0x400);	/* get pos A value */
 	val2 = readl(addr);		/* get val2 */
+	writel(0x0, addr + 0x400);	/* clear pos A */
 
 	if ((val1 != 0) || (val2 != pattern))	/* see if pos A val changed */
 		return 0;

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #5 lore raw

PATCH v4 5/14 OMAP3: Remove get_mem_type prototype

In reply to Tom Rini

This function doesn't exist for omap3

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

arch/arm/include/asm/arch-omap3/sys_proto.h +0 -1

index 995e7cb..9e64410 100644
@@ -49,7 +49,6 @@ void set_muxconf_regs(void);
 u32 get_cpu_family(void);
 u32 get_cpu_rev(void);
 u32 get_sku_id(void);
-u32 get_mem_type(void);
 u32 get_sysboot_value(void);
 u32 is_gpmc_muxed(void);
 u32 get_gpmc0_type(void);

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #6 lore raw

PATCH v4 6/14 omap3: mem: Add MCFG helper macro

In reply to Tom Rini

This adds an MCFG macro to calculate the correct value, similar to the ACTIMA/ACTIMB macros and adds a comment that all of the potential values here are documented in the TRM. Then we convert the Micron value to use this macro.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap3/mem.h |   46 +++++++++++++++++++++-----------
 1 files changed, 30 insertions(+), 16 deletions(-)

arch/arm/include/asm/arch-omap3/mem.h +30 ~~-16~~

index abf4e82..12ff3b0 100644
@@ -39,6 +39,12 @@ enum {
 
 #define EARLY_INIT	1
 
+/*
+ * For a full explanation of these registers and values please see
+ * the Technical Reference Manual (TRM) for any of the processors in
+ * this family.
+ */
+
 /* Slower full frequency range default timings for x32 operation*/
 #define SDRC_SHARING	0x00000100
 #define SDRC_MR_0_SDR	0x00000031

@@ -86,6 +92,27 @@ enum {
 		ACTIM_CTRLB_TXP(b)	|	\
 		ACTIM_CTRLB_TXSR(d)
 
+/*
+ * Values used in the MCFG register.  Only values we use today
+ * are defined and the rest can be found in the TRM.  Unless otherwise
+ * noted all fields are one bit.
+ */
+#define V_MCFG_RAMTYPE_DDR		(0x1)
+#define V_MCFG_DEEPPD_EN		(0x1 << 3)
+#define V_MCFG_B32NOT16_32		(0x1 << 4)
+#define V_MCFG_BANKALLOCATION_RBC	(0x2 << 6)	/* 6:7 */
+#define V_MCFG_RAMSIZE(a)		((((a)/(1024*1024))/2) << 8) /* 8:17 */
+#define V_MCFG_ADDRMUXLEGACY_FLEX	(0x1 << 19)
+#define V_MCFG_CASWIDTH_10B		(0x5 << 20)	/* 20:22 */
+#define V_MCFG_RASWIDTH(a)		((a) << 24)	/* 24:26 */
+
+/* Macro to construct MCFG */
+#define MCFG(a, b)						\
+		V_MCFG_RASWIDTH(b) | V_MCFG_CASWIDTH_10B |	\
+		V_MCFG_ADDRMUXLEGACY_FLEX | V_MCFG_RAMSIZE(a) |	\
+		V_MCFG_BANKALLOCATION_RBC |			\
+		V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
+
 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
 #define INFINEON_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
 					/* 15/6 + 18/6 = 5.5 -> 6	*/

@@ -138,21 +165,8 @@ enum {
 		ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,	\
 				MICRON_TXP_165,	MICRON_XSR_165)
 
-#define MICRON_RAMTYPE			0x1
-#define MICRON_DDRTYPE			0x0
-#define MICRON_DEEPPD			0x1
-#define MICRON_B32NOT16			0x1
-#define MICRON_BANKALLOCATION	0x2
-#define MICRON_RAMSIZE			((PHYS_SDRAM_1_SIZE/(1024*1024))/2)
-#define MICRON_ADDRMUXLEGACY	0x1
-#define MICRON_CASWIDTH			0x5
-#define MICRON_RASWIDTH			0x2
-#define MICRON_LOCKSTATUS		0x0
-#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
-	(MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
-	(MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
-	(MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
-	(MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
+#define MICRON_RASWIDTH		0x2
+#define MICRON_V_MCFG(size)	MCFG((size), MICRON_RASWIDTH)
 
 #define MICRON_ARCV				2030
 #define MICRON_ARE				0x1

@@ -199,7 +213,7 @@ enum {
 #ifdef CONFIG_OMAP3_MICRON_DDR
 #define V_ACTIMA_165		MICRON_V_ACTIMA_165
 #define V_ACTIMB_165		MICRON_V_ACTIMB_165
-#define V_MCFG			MICRON_V_MCFG
+#define V_MCFG			MICRON_V_MCFG(PHYS_SDRAM_1_SIZE)
 #define V_RFR_CTRL		MICRON_V_RFR_CTRL
 #define V_MR			MICRON_V_MR
 #endif

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #7 lore raw

PATCH v4 7/14 OMAP3: Add optimal SDRC autorefresh control values

In reply to Tom Rini

This adds the optimal SDRC autorefresh control register values for 100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this to provide the default 165MHz value.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap3/mem.h |   16 +++++++++++-----
 1 files changed, 11 insertions(+), 5 deletions(-)

arch/arm/include/asm/arch-omap3/mem.h +11 -5

index 12ff3b0..912c737 100644
@@ -49,6 +49,16 @@ enum {
 #define SDRC_SHARING	0x00000100
 #define SDRC_MR_0_SDR	0x00000031
 
+/*
+ * SDRC autorefresh control values.  This register consists of autorefresh
+ * enable at bits 0:1 and an autorefresh counter value in bits 8:23.  The
+ * counter is a result of ( tREFI / tCK ) - 50.
+ */
+#define SDP_3430_SDRC_RFR_CTRL_100MHz	0x0002da01
+#define SDP_3430_SDRC_RFR_CTRL_133MHz	0x0003de01 /* 7.8us/7.5ns - 50=0x3de */
+#define SDP_3430_SDRC_RFR_CTRL_165MHz	0x0004e201 /* 7.8us/6ns - 50=0x4e2 */
+#define SDP_3430_SDRC_RFR_CTRL_200MHz	0x0005e601 /* 7.8us/5ns - 50=0x5e6 */
+
 #define DLL_OFFSET		0
 #define DLL_WRITEDDRCLKX2DIS	1
 #define DLL_ENADLL		1

@@ -168,10 +178,6 @@ enum {
 #define MICRON_RASWIDTH		0x2
 #define MICRON_V_MCFG(size)	MCFG((size), MICRON_RASWIDTH)
 
-#define MICRON_ARCV				2030
-#define MICRON_ARE				0x1
-#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
-
 #define MICRON_BL				0x2
 #define MICRON_SIL				0x0
 #define MICRON_CASL				0x3

@@ -214,7 +220,7 @@ enum {
 #define V_ACTIMA_165		MICRON_V_ACTIMA_165
 #define V_ACTIMB_165		MICRON_V_ACTIMB_165
 #define V_MCFG			MICRON_V_MCFG(PHYS_SDRAM_1_SIZE)
-#define V_RFR_CTRL		MICRON_V_RFR_CTRL
+#define V_RFR_CTRL		SDP_3430_SDRC_RFR_CTRL_165MHz
 #define V_MR			MICRON_V_MR
 #endif

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #8 lore raw

PATCH v4 8/14 OMAP3: Suffix all Micron memory timing parts with their speed

In reply to Tom Rini

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap3/mem.h |   21 +++++++++++----------
 1 files changed, 11 insertions(+), 10 deletions(-)

arch/arm/include/asm/arch-omap3/mem.h +11 ~~-10~~

index 912c737..4f996d9 100644
@@ -175,15 +175,16 @@ enum {
 		ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165,	\
 				MICRON_TXP_165,	MICRON_XSR_165)
 
-#define MICRON_RASWIDTH		0x2
-#define MICRON_V_MCFG(size)	MCFG((size), MICRON_RASWIDTH)
+#define MICRON_RASWIDTH_165	0x2
+#define MICRON_V_MCFG_165(size)	MCFG((size), MICRON_RASWIDTH_165)
 
-#define MICRON_BL				0x2
-#define MICRON_SIL				0x0
-#define MICRON_CASL				0x3
-#define MICRON_WBST				0x0
-#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
-	(MICRON_SIL << 3) | (MICRON_BL))
+#define MICRON_BL_165			0x2
+#define MICRON_SIL_165			0x0
+#define MICRON_CASL_165			0x3
+#define MICRON_WBST_165			0x0
+#define MICRON_V_MR_165			((MICRON_WBST_165 << 9) | \
+		(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
+		(MICRON_BL_165))
 
 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
 #define NUMONYX_TDAL_165	6	/* Twr/Tck + Trp/tck		*/

@@ -219,9 +220,9 @@ enum {
 #ifdef CONFIG_OMAP3_MICRON_DDR
 #define V_ACTIMA_165		MICRON_V_ACTIMA_165
 #define V_ACTIMB_165		MICRON_V_ACTIMB_165
-#define V_MCFG			MICRON_V_MCFG(PHYS_SDRAM_1_SIZE)
+#define V_MCFG			MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE)
 #define V_RFR_CTRL		SDP_3430_SDRC_RFR_CTRL_165MHz
-#define V_MR			MICRON_V_MR
+#define V_MR			MICRON_V_MR_165
 #endif
 
 #ifdef CONFIG_OMAP3_NUMONYX_DDR

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #9 lore raw

PATCH v4 9/14 OMAP3 SPL: Rework memory initalization and devkit8000 support

In reply to Tom Rini

This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1.

Cc Frederik Kriewitz <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/cpu/armv7/omap3/sdrc.c             |   28 ++++++++++++++------------
 arch/arm/include/asm/arch-omap3/mem.h       |   26 -------------------------
 arch/arm/include/asm/arch-omap3/sys_proto.h |    2 +
 board/timll/devkit8000/devkit8000.c         |   21 ++++++++++++++++++++
 include/configs/devkit8000.h                |    5 ----
 5 files changed, 38 insertions(+), 44 deletions(-)

arch/arm/cpu/armv7/omap3/sdrc.c +15 ~~-13~~

index 2756024..a27b4b1 100644
@@ -148,6 +148,18 @@ void do_sdrc_init(u32 cs, u32 early)
 	sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
 	sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
 
+	/*
+	 * When called in the early context this may be SPL and we will
+	 * need to set all of the timings.  This ends up being board
+	 * specific so we call a helper function to take care of this
+	 * for us.  Otherwise, to be safe, we need to copy the settings
+	 * from the first bank to the second.  We will setup CS0,
+	 * then set cs_cfg to the appropriate value then try and
+	 * setup CS1.
+	 */
+#ifdef CONFIG_SPL_BUILD
+	get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+#endif
 	if (early) {
 		/* reset sdrc controller */
 		writel(SOFTRESET, &sdrc_base->sysconfig);

@@ -164,22 +176,12 @@ void do_sdrc_init(u32 cs, u32 early)
 
 		writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
 		sdelay(0x20000);
-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
- * to prevent this to be build in non-SPL build */
 #ifdef CONFIG_SPL_BUILD
-		/*
-		 * If we use a SPL there is no x-loader nor config header so
-		 * we have to do the job ourselfs
-		 */
-
-		mcfg = V_MCFG;
-		ctrla = V_ACTIMA_165;
-		ctrlb = V_ACTIMB_165;
-		rfr_ctrl = V_RFR_CTRL;
-		mr = V_MR;
-
 		write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
 				rfr_ctrl, mr);
+		make_cs1_contiguous();
+		write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
+				rfr_ctrl, mr);
 #endif
 
 	}

arch/arm/include/asm/arch-omap3/mem.h +0 ~~-26~~

index 4f996d9..09f5872 100644
@@ -212,32 +212,6 @@ enum {
 		ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165,	\
 				NUMONYX_TXP_165, NUMONYX_XSR_165)
 
-#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165		INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165		INFINEON_V_ACTIMB_165
-#endif
-
-#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165		MICRON_V_ACTIMA_165
-#define V_ACTIMB_165		MICRON_V_ACTIMB_165
-#define V_MCFG			MICRON_V_MCFG_165(PHYS_SDRAM_1_SIZE)
-#define V_RFR_CTRL		SDP_3430_SDRC_RFR_CTRL_165MHz
-#define V_MR			MICRON_V_MR_165
-#endif
-
-#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165		NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165		NUMONYX_V_ACTIMB_165
-#endif
-
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
-#error "Please choose the right DDR type in config header"
-#endif
-
-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
-#error "Please choose the right DDR type in config header"
-#endif
-
 /*
  * GPMC settings -
  * Definitions is as per the following format

arch/arm/include/asm/arch-omap3/sys_proto.h +2 -0

index 9e64410..80e167b 100644
@@ -38,6 +38,8 @@ void per_clocks_enable(void);
 void memif_init(void);
 void sdrc_init(void);
 void do_sdrc_init(u32, u32);
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+		u32 *mr);
 void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,

board/timll/devkit8000/devkit8000.c +21 -0

index fee0dff..b06aab6 100644
@@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis)
 	return dm9000_initialize(bis);
 }
 #endif
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on the first bank.  This
+ * provides the timing values back to the function that configures
+ * the memory.  We have either one or two banks of 128MB DDR.
+ */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
+		u32 *mr)
+{
+	/* General SDRC config */
+	*mcfg = MICRON_V_MCFG_165(128 << 20);
+	*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+
+	/* AC timings */
+	*ctrla = MICRON_V_ACTIMA_165;
+	*ctrlb = MICRON_V_ACTIMB_165;
+
+	*mr = MICRON_V_MR_165;
+}

include/configs/devkit8000.h +0 -5

index e1743dc..b3e60cd 100644
@@ -68,10 +68,6 @@
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 
 /* Hardware drivers */
-
-/* DDR - I use Micron DDR */
-#define CONFIG_OMAP3_MICRON_DDR		1
-
 /* DM9000 */
 #define CONFIG_NET_RETRY_COUNT		20
 #define	CONFIG_DRIVER_DM9000		1

@@ -284,7 +280,6 @@
 /*  Physical Memory Map  */
 #define CONFIG_NR_DRAM_BANKS		2 /* CS1 may or may not be populated */
 #define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE		(128 << 20)	/*@least 128 MiB */
 #define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #10 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

In reply to Tom Rini

A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c

arch/arm/cpu/armv7/omap3/Makefile +3 -0

index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)	+= spl_id_nand.o
+endif
 
 COBJS-$(CONFIG_EMIF4)	+= emif4.o
 COBJS-$(CONFIG_SDRC)	+= sdrc.o

arch/arm/cpu/armv7/omap3/spl_id_nand.c new file +87 -0

87 lines not on this page · raw message

arch/arm/include/asm/arch-omap3/sys_proto.h +1 -0

index 80e167b..e5031d5 100644
@@ -40,6 +40,7 @@ void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 		u32 *mr);
+void identify_nand_chip(int *mfr, int *id);
 void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,

Signature · 1 line

1.7.0.4

Igor Grinberg

2011-11-20 07:36 UTC #11 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Hi Tom,

Quoted 19 lines · Tom Rini

A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
arch/arm/cpu/armv7/omap3/Makefile +0 -0
index 8e85891..4b38e45 100644

arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36

Quoted 6 lines

arch/arm/cpu/armv7/omap3/Makefile +3 -0

@@ -31,6 +31,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)	+= spl_id_nand.o
+endif

You haven't responded to my question on the above stuff. Otherwise all the series look good to me.

Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html

Here is the relevant part:

Quoted 16 lines

Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 10 lines
index 8e85891..772f3d4 100644
arch/arm/cpu/armv7/omap3/Makefile +3 -0
@@ -31,6 +31,9 @@ COBJS	+= board.o
 COBJS	+= clock.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE)	+= spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?

Quoted 1 line

Quoted 1 line
But then it would build for both SPL and non-SPL cases.

No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o

Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD

# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif

This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.

Quoted 108 lines

COBJS-$(CONFIG_EMIF4) += emif4.o
COBJS-$(CONFIG_SDRC) += sdrc.o

arch/arm/cpu/armv7/omap3/spl_id_nand.c new file +87 -0

new file mode 100644
index 0000000..0871fc9
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2011
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ *     Tom Rini <[email protected]>
+ *
+ * Initial Code from:
+ *     Richard Woodruff <[email protected]>
+ *     Jian Zhang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/nand.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mem.h>
+
+static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
+
+/* nand_command: Send a flash command to the flash chip */
+static void nand_command(u8 command)
+{
+	writeb(command, &gpmc_config->cs[0].nand_cmd);
+
+	if (command == NAND_CMD_RESET) {
+		unsigned char ret_val;
+		writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
+		do {
+			/* Wait until ready */
+			ret_val = readl(&gpmc_config->cs[0].nand_dat);
+		} while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY);
+	}
+}
+
+/*
+ * Many boards will want to know the results of the NAND_CMD_READID command
+ * in order to decide what to do about DDR initialization.  This function
+ * allows us to do that very early and to pass those results back to the
+ * board so it can make whatever decisions need to be made.
+ */
+void identify_nand_chip(int *mfr, int *id)
+{
+	/* Make sure that we have setup GPMC for NAND correctly. */
+	writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
+	writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
+	writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
+	writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
+	writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
+	writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
+
+	/*
+	 * Enable the config.  The CS size goes in bits 11:8.  We set
+	 * bit 6 to enable the CS and the base address goes into bits 5:0.
+	 */
+	writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) |
+				((NAND_BASE >> 24) & GPMC_BASEADDR_MASK),
+			&gpmc_config->cs[0].config7);
+
+	sdelay(2000);
+
+	/* Issue a RESET and then READID */
+	nand_command(NAND_CMD_RESET);
+	nand_command(NAND_CMD_READID);
+
+	/* Set the address to read to 0x0 */
+	writeb(0x0, &gpmc_config->cs[0].nand_adr);
+
+	/* Read off the manufacturer and device id. */
+	*mfr = readb(&gpmc_config->cs[0].nand_dat);
+	*id = readb(&gpmc_config->cs[0].nand_dat);
+}

arch/arm/include/asm/arch-omap3/sys_proto.h +1 -0

index 80e167b..e5031d5 100644
@@ -40,6 +40,7 @@ void sdrc_init(void);
 void do_sdrc_init(u32, u32);
 void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
 		u32 *mr);
+void identify_nand_chip(int *mfr, int *id);
 void emif4_init(void);
 void gpmc_init(void);
 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,

Signature · 2 lines

Regards,
Igor.

Tom Rini

2011-11-20 14:26 UTC #12 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 17 lines · Igor Grinberg

Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. ?Other boards may simply use this as an easy way to identify board revs. ?So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. ?All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
?arch/arm/cpu/armv7/omap3/Makefile ? ? ? ? ? | ? ?3 +
?arch/arm/cpu/armv7/omap3/spl_id_nand.c ? ? ?| ? 87 +++++++++++++++++++++++++++
?arch/arm/include/asm/arch-omap3/sys_proto.h | ? ?1 +
?3 files changed, 91 insertions(+), 0 deletions(-) ?create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c

Quoted 14 lines

arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS ? ? ? += board.o
?COBJS ? ? ? ?+= clock.o
?COBJS ? ? ? ?+= mem.o
?COBJS ? ? ? ?+= sys_info.o
arch/arm/cpu/armv7/omap3/Makefile +3 -0
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) ? ?+= spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.

Missed that, sorry!

Quoted 29 lines

Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 10 lines
index 8e85891..772f3d4 100644
arch/arm/cpu/armv7/omap3/Makefile +0 -0
@@ -31,6 +31,9 @@ COBJS += board.o
?COBJS ?+= clock.o
?COBJS ?+= mem.o
?COBJS ?+= sys_info.o
arch/arm/cpu/armv7/omap3/Makefile +3 -0
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) ? ?+= spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) ? ? += spl_pop_probe.o

Quoted 7 lines

Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.

Well, if we always link this, but then #error, U-Boot won't build :) I guess the reason to not #ifndef CONFIG_SPL_BUILD the whole file is that the normal style for SPL is to only include the file when building for SPL.

Signature · 1 line

Tom

Igor Grinberg

2011-11-21 07:04 UTC #13 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 69 lines · Tom Rini

Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 34 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 10 lines
index 8e85891..772f3d4 100644
arch/arm/cpu/armv7/omap3/Makefile +3 -0
@@ -31,6 +31,9 @@ COBJS += board.o
 COBJS  += clock.o
 COBJS  += mem.o
 COBJS  += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE)    += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif

Quoted 4 lines

Quoted 2 lines
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Well, if we always link this, but then #error, U-Boot won't build :)

No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.

Quoted 3 lines

I guess the reason to not #ifndef CONFIG_SPL_BUILD the whole file is that the normal style for SPL is to only include the file when building for SPL.

I don't understand the sentence above and
the way it is related to my question.

Signature · 2 lines

Regards,
Igor.

Tom Rini

2011-11-21 14:12 UTC #14 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 73 lines · Igor Grinberg

Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. ?Other boards may simply use this as an easy way to identify board revs. ?So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. ?All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
?arch/arm/cpu/armv7/omap3/Makefile ? ? ? ? ? | ? ?3 +
?arch/arm/cpu/armv7/omap3/spl_id_nand.c ? ? ?| ? 87 +++++++++++++++++++++++++++
?arch/arm/include/asm/arch-omap3/sys_proto.h | ? ?1 +
?3 files changed, 91 insertions(+), 0 deletions(-) ?create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS ? ? ? += board.o
?COBJS ? ? ? ?+= clock.o
?COBJS ? ? ? ?+= mem.o
?COBJS ? ? ? ?+= sys_info.o
arch/arm/cpu/armv7/omap3/Makefile +3 -0
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND) ? ?+= spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 10 lines
index 8e85891..772f3d4 100644
arch/arm/cpu/armv7/omap3/Makefile +0 -0
@@ -31,6 +31,9 @@ COBJS += board.o
?COBJS ?+= clock.o
?COBJS ?+= mem.o
?COBJS ?+= sys_info.o
arch/arm/cpu/armv7/omap3/Makefile +3 -0
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) ? ?+= spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) ? ? += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.

Quoted 6 lines

Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.

So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.

Signature · 1 line

Tom

Igor Grinberg

2011-11-21 14:41 UTC #15 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 81 lines · Tom Rini

Quoted 73 lines · Igor Grinberg
Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 10 lines
index 8e85891..772f3d4 100644
arch/arm/cpu/armv7/omap3/Makefile +3 -0
@@ -31,6 +31,9 @@ COBJS += board.o
 COBJS  += clock.o
 COBJS  += mem.o
 COBJS  += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE)    += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Quoted 6 lines
Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.

Quoted 5 lines

So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.

Well, yes I think it makes sense for all SPL related config options to do something like:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#define CONFIG_SPL_...
#define CONFIG_SPL_...
#endif

And the error message, I have proposed above, will prevent people from doing stupid things, like defining CONFIG_SPL_OMAP3_POP_PROBE without the CONFIG_SPL_BUILD. At least for now, until we have Kbuild with dependencies and stuff...

Signature · 2 lines

Regards,
Igor.

Tom Rini

author

2011-11-21 15:33 UTC #16 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 96 lines · Igor Grinberg

Quoted 81 lines · Tom Rini
Quoted 73 lines · Igor Grinberg
Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 10 lines
index 8e85891..772f3d4 100644
arch/arm/cpu/armv7/omap3/Makefile +3 -0
@@ -31,6 +31,9 @@ COBJS += board.o
 COBJS  += clock.o
 COBJS  += mem.o
 COBJS  += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE)    += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Quoted 6 lines
Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.
Quoted 5 lines
So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.
Well, yes I think it makes sense for all SPL related config options to do something like:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#define CONFIG_SPL_...
#define CONFIG_SPL_...
#endif

Quoted 4 lines

And the error message, I have proposed above, will prevent people from doing stupid things, like defining CONFIG_SPL_OMAP3_POP_PROBE without the CONFIG_SPL_BUILD. At least for now, until we have Kbuild with dependencies and stuff...

Well, I guess the point I'd try and make is that it's not how SPL is done today. Really following the existing format would be (in the Makefile):
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
COBJS-y += spl_id_nand.o
endif
endif

I can see the point you're making but I'm asking if we need to change everyone around to your suggested way of building before we can merge these changes in? Thanks!

Signature · 1 line

Tom

Igor Grinberg

2011-11-22 14:33 UTC #17 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 102 lines · Tom Rini

Quoted 96 lines · Igor Grinberg
Quoted 81 lines · Tom Rini
Quoted 73 lines · Igor Grinberg
Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 10 lines
index 8e85891..772f3d4 100644
arch/arm/cpu/armv7/omap3/Makefile +3 -0
@@ -31,6 +31,9 @@ COBJS += board.o
 COBJS  += clock.o
 COBJS  += mem.o
 COBJS  += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE)    += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Quoted 6 lines
Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.
Quoted 5 lines
So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.
Well, yes I think it makes sense for all SPL related config options to do something like:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#define CONFIG_SPL_...
#define CONFIG_SPL_...
#endif
Quoted 4 lines
And the error message, I have proposed above, will prevent people from doing stupid things, like defining CONFIG_SPL_OMAP3_POP_PROBE without the CONFIG_SPL_BUILD. At least for now, until we have Kbuild with dependencies and stuff...

Quoted 8 lines

Well, I guess the point I'd try and make is that it's not how SPL is done today. Really following the existing format would be (in the Makefile):
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
COBJS-y += spl_id_nand.o
endif
endif

This is bad!
We don't want the code to look like the above crap, do we? Because next thing will be even worth:
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
ifdef CONFIG_SPL_OMAP3_ID_NAND_SHIT...
COBJS-y += spl_id_nand_shit...o
endif
endif
endif

Quoted 4 lines

I can see the point you're making but I'm asking if we need to change everyone around to your suggested way of building before we can merge these changes in? Thanks!

Ok. I understand your point. No, I don't think we should. The real question is, do we want it look like the above crap? If not, then please, do it right in this patch and all the rest can be changed later.
Also would be nice to make all future patches do the right thing.

Signature · 2 lines

Regards,
Igor.

Tom Rini

author

2011-11-22 14:51 UTC #18 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 128 lines · Igor Grinberg

Quoted 102 lines · Tom Rini
Quoted 96 lines · Igor Grinberg
Quoted 81 lines · Tom Rini
Quoted 73 lines · Igor Grinberg
Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
Quoted 10 lines
index 8e85891..772f3d4 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -31,6 +31,9 @@ COBJS += board.o
COBJS += clock.o
COBJS += mem.o
COBJS += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Quoted 6 lines
Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.
Quoted 5 lines
So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.
Well, yes I think it makes sense for all SPL related config options to do something like:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#define CONFIG_SPL_...
#define CONFIG_SPL_...
#endif
Quoted 4 lines
And the error message, I have proposed above, will prevent people from doing stupid things, like defining CONFIG_SPL_OMAP3_POP_PROBE without the CONFIG_SPL_BUILD. At least for now, until we have Kbuild with dependencies and stuff...
Quoted 8 lines
Well, I guess the point I'd try and make is that it's not how SPL is done today. Really following the existing format would be (in the Makefile):
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
COBJS-y += spl_id_nand.o
endif
endif
This is bad!
We don't want the code to look like the above crap, do we? Because next thing will be even worth:
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
ifdef CONFIG_SPL_OMAP3_ID_NAND_SHIT...
COBJS-y += spl_id_nand_shit...o
endif
endif
endif
Quoted 4 lines
I can see the point you're making but I'm asking if we need to change everyone around to your suggested way of building before we can merge these changes in? Thanks!

Quoted 5 lines

Ok. I understand your point. No, I don't think we should. The real question is, do we want it look like the above crap? If not, then please, do it right in this patch and all the rest can be changed later.
Also would be nice to make all future patches do the right thing.

OK, will do. Thanks!

Signature · 1 line

Tom

Tom Rini

author

2011-11-22 15:39 UTC #19 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 129 lines · Tom Rini

Quoted 128 lines · Igor Grinberg
Quoted 102 lines · Tom Rini
Quoted 96 lines · Igor Grinberg
Quoted 81 lines · Tom Rini
Quoted 73 lines · Igor Grinberg
Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
Quoted 10 lines
index 8e85891..772f3d4 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -31,6 +31,9 @@ COBJS += board.o
COBJS += clock.o
COBJS += mem.o
COBJS += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Quoted 6 lines
Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.
Quoted 5 lines
So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.
Well, yes I think it makes sense for all SPL related config options to do something like:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#define CONFIG_SPL_...
#define CONFIG_SPL_...
#endif
Quoted 4 lines
And the error message, I have proposed above, will prevent people from doing stupid things, like defining CONFIG_SPL_OMAP3_POP_PROBE without the CONFIG_SPL_BUILD. At least for now, until we have Kbuild with dependencies and stuff...
Quoted 8 lines
Well, I guess the point I'd try and make is that it's not how SPL is done today. Really following the existing format would be (in the Makefile):
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
COBJS-y += spl_id_nand.o
endif
endif
This is bad!
We don't want the code to look like the above crap, do we? Because next thing will be even worth:
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
ifdef CONFIG_SPL_OMAP3_ID_NAND_SHIT...
COBJS-y += spl_id_nand_shit...o
endif
endif
endif
Quoted 4 lines
I can see the point you're making but I'm asking if we need to change everyone around to your suggested way of building before we can merge these changes in? Thanks!

Quoted 7 lines

Quoted 5 lines
Ok. I understand your point. No, I don't think we should. The real question is, do we want it look like the above crap? If not, then please, do it right in this patch and all the rest can be changed later.
Also would be nice to make all future patches do the right thing.
OK, will do. Thanks!

Well, there's a problem. spl/Makefile both sets CONFIG_SPL_BUILD and then says "here's a bunch of core stuff" we need. So... we can't hide most CONFIG choices under a CONFIG_SPL_BUILD check. We can in the Makefiles however do more:
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_...) += spl_foo.o
endif
than we do today.

Signature · 1 line

Tom

Igor Grinberg

2011-11-23 07:39 UTC #20 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 136 lines · Tom Rini

Quoted 135 lines · Tom Rini
Quoted 133 lines · Igor Grinberg
Quoted 102 lines · Tom Rini
Quoted 96 lines · Igor Grinberg
Quoted 81 lines · Tom Rini
Quoted 73 lines · Igor Grinberg
Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
arch/arm/cpu/armv7/omap3/Makefile +0 -0
Quoted 14 lines
index 8e85891..772f3d4 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -31,6 +31,9 @@ COBJS += board.o
COBJS += clock.o
COBJS += mem.o
COBJS += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no"
and depend on CONFIG_SPL_BUILD, so you don't need to enclose
it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Quoted 6 lines
Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.
Quoted 5 lines
So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.
Well, yes I think it makes sense for all SPL related config options to do something like:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#define CONFIG_SPL_...
#define CONFIG_SPL_...
#endif
Quoted 4 lines
And the error message, I have proposed above, will prevent people from doing stupid things, like defining CONFIG_SPL_OMAP3_POP_PROBE without the CONFIG_SPL_BUILD. At least for now, until we have Kbuild with dependencies and stuff...
Quoted 8 lines
Well, I guess the point I'd try and make is that it's not how SPL is done today. Really following the existing format would be (in the Makefile):
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
COBJS-y += spl_id_nand.o
endif
endif
This is bad!
We don't want the code to look like the above crap, do we? Because next thing will be even worth:
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
ifdef CONFIG_SPL_OMAP3_ID_NAND_SHIT...
COBJS-y += spl_id_nand_shit...o
endif
endif
endif
Quoted 4 lines
I can see the point you're making but I'm asking if we need to change everyone around to your suggested way of building before we can merge these changes in? Thanks!
Ok. I understand your point. No, I don't think we should. The real question is, do we want it look like the above crap? If not, then please, do it right in this patch and all the rest can be changed later.
Also would be nice to make all future patches do the right thing.

Quoted 5 lines

Quoted 1 line
OK, will do. Thanks!
Well, there's a problem. spl/Makefile both sets CONFIG_SPL_BUILD and then says "here's a bunch of core stuff" we need. So... we can't hide most CONFIG choices under a CONFIG_SPL_BUILD check.

Why? What's the problem?
Is a board config file gets included before the CONFIG_SPL_BUILD gets exported? And then the "sub" symbol does not get defined? Is that what's going on? or am I missing something?

Quoted 6 lines

We can in the
Makefiles however do more:
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_...) += spl_foo.o
endif
than we do today.

And it will turn into a crap... and spread over all the U-Boot code... This is a problem!

What I propose here is to use the same model as Linux uses - one independent config option per feature, which can be selected by a board config file. Is it impossible right now?

Signature · 2 lines

Regards,
Igor.

Tom Rini

author

2011-11-23 14:48 UTC #21 lore raw

PATCH v4 10/14 OMAP3 SPL: Add identify_nand_chip function

Quoted 139 lines · Igor Grinberg

Quoted 138 lines · Tom Rini
Quoted 136 lines · Tom Rini
Quoted 128 lines · Igor Grinberg
Quoted 102 lines · Tom Rini
Quoted 96 lines · Igor Grinberg
Quoted 81 lines · Tom Rini
Quoted 73 lines · Igor Grinberg
Quoted 72 lines · Tom Rini
Quoted 17 lines · Igor Grinberg
Hi Tom,
Quoted 14 lines · Tom Rini
A number of boards are populated with a PoP chip for both DDR and NAND memory. Other boards may simply use this as an easy way to identify board revs. So we provide a function that can be called early to reset the NAND chip and return the result of NAND_CMD_READID. All of this code is put into spl_id_nand.c and controlled via CONFIG_SPL_OMAP3_ID_NAND.
Signed-off-by Tom Rini <[email protected]>
---
 arch/arm/cpu/armv7/omap3/Makefile           |    3 +
 arch/arm/cpu/armv7/omap3/spl_id_nand.c      |   87 +++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/sys_proto.h |    1 +
 3 files changed, 91 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/omap3/spl_id_nand.c
Quoted 14 lines
arch/arm/cpu/armv7/omap3/Makefile COBJS += board.o · line 36
Quoted 11 lines
arch/arm/cpu/armv7/omap3/Makefile +3 -0
index 8e85891..4b38e45 100644
@@ -31,6 +31,9 @@ COBJS       += board.o
 COBJS        += clock.o
 COBJS        += mem.o
 COBJS        += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_ID_NAND)    += spl_id_nand.o
+endif
You haven't responded to my question on the above stuff. Otherwise all the series look good to me.
Missed that, sorry!
Quoted 36 lines
Original version available at:
http://www.mail-archive.com/u-boot at lists.denx.de/msg68828.html
Here is the relevant part:
Quoted 16 lines
Quoted 16 lines
Quoted 15 lines
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile
index 8e85891..772f3d4 100644
--- a/arch/arm/cpu/armv7/omap3/Makefile
+++ b/arch/arm/cpu/armv7/omap3/Makefile
@@ -31,6 +31,9 @@ COBJS += board.o
COBJS += clock.o
COBJS += mem.o
COBJS += sys_info.o
+ifdef CONFIG_SPL_BUILD
+COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
+endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no"
and depend on CONFIG_SPL_BUILD, so you don't need to enclose
it in #ifdef?
Quoted 1 line
Quoted 1 line
But then it would build for both SPL and non-SPL cases.
No, it should not.
What do you think of the following:
In the Makefile have only:
COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check:
#ifndef CONFIG_SPL_BUILD
# error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD
#endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
Quoted 6 lines
Quoted 1 line
Well, if we always link this, but then #error, U-Boot won't build :)
No you do not always link this... please, read more carefully... Only when CONFIG_SPL_OMAP3_POP_PROBE symbol is defined, the file will be compiled, but if CONFIG_SPL_OMAP3_POP_PROBE defined without CONFIG_SPL_BUILD being defined, then it will emit an error.
Quoted 5 lines
So make the config file do:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#endif
? That's now how the rest of the SPL code works.
Well, yes I think it makes sense for all SPL related config options to do something like:
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_OMAP3_POP_PROBE
#define CONFIG_SPL_...
#define CONFIG_SPL_...
#endif
Quoted 4 lines
And the error message, I have proposed above, will prevent people from doing stupid things, like defining CONFIG_SPL_OMAP3_POP_PROBE without the CONFIG_SPL_BUILD. At least for now, until we have Kbuild with dependencies and stuff...
Quoted 8 lines
Well, I guess the point I'd try and make is that it's not how SPL is done today. Really following the existing format would be (in the Makefile):
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
COBJS-y += spl_id_nand.o
endif
endif
This is bad!
We don't want the code to look like the above crap, do we? Because next thing will be even worth:
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_SPL_OMAP3_ID_NAND
ifdef CONFIG_SPL_OMAP3_ID_NAND_SHIT...
COBJS-y += spl_id_nand_shit...o
endif
endif
endif
Quoted 4 lines
I can see the point you're making but I'm asking if we need to change everyone around to your suggested way of building before we can merge these changes in? Thanks!
Quoted 5 lines
Ok. I understand your point. No, I don't think we should. The real question is, do we want it look like the above crap? If not, then please, do it right in this patch and all the rest can be changed later.
Also would be nice to make all future patches do the right thing.
OK, will do. Thanks!

Quoted 7 lines

Quoted 3 lines
Well, there's a problem. spl/Makefile both sets CONFIG_SPL_BUILD and then says "here's a bunch of core stuff" we need. So... we can't hide most CONFIG choices under a CONFIG_SPL_BUILD check.
Why? What's the problem?
Is a board config file gets included before the CONFIG_SPL_BUILD gets exported? And then the "sub" symbol does not get defined?

Correct. Give the change you're proposing a try on devkit8000, you'll see what I mean.

Quoted 9 lines

Is that what's going on? or am I missing something?
Quoted 6 lines
We can in the
Makefiles however do more:
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_...) += spl_foo.o
endif
than we do today.

Quoted 7 lines

And it will turn into a crap... and spread over all the U-Boot code... This is a problem!
What I propose here is to use the same model as Linux uses - one independent config option per feature, which can be selected by a board config file. Is it impossible right now?

Yes, needs a good bit of thinking.

Signature · 1 line

Tom

Tom Rini

author

2011-11-18 22:48 UTC #22 lore raw

PATCH v4 11/14 OMAP3: Add SPL support to Beagleboard

In reply to Tom Rini

This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h> and Numonyx MCFG calculation. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC. We also change CONFIG_SYS_TEXT_BASE to 0x80100000.

Cc: Dirk Behme <[email protected]>
Beagleboard rev C5, xM rev A:

Tested-by Tom Rini <[email protected]>

Beagleboard xM rev C:

Tested-by Matt Ranostay <[email protected]>

Beagleboard rev B7, C2, xM rev B:

Tested-by Matt Porter <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap3/mem.h |   29 +++++++++++++
 board/ti/beagle/beagle.c              |   71 ++++++++++++++++++++++++++++++++-
 board/ti/beagle/config.mk             |   33 ---------------
 include/configs/omap3_beagle.h        |   59 +++++++++++++++++++++++++--
 4 files changed, 153 insertions(+), 39 deletions(-)
 delete mode 100644 board/ti/beagle/config.mk

arch/arm/include/asm/arch-omap3/mem.h +29 -0

index 09f5872..4ea5f74 100644
@@ -186,6 +186,32 @@ enum {
 		(MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \
 		(MICRON_BL_165))
 
+/* Micron part (200MHz optimized) 5 ns */
+#define MICRON_TDAL_200		6
+#define MICRON_TDPL_200		3
+#define MICRON_TRRD_200		2
+#define MICRON_TRCD_200		3
+#define MICRON_TRP_200		3
+#define MICRON_TRAS_200		8
+#define MICRON_TRC_200		11
+#define MICRON_TRFC_200		15
+#define MICRON_V_ACTIMA_200	\
+		ACTIM_CTRLA(MICRON_TRFC_200, MICRON_TRC_200,		\
+				MICRON_TRAS_200, MICRON_TRP_200,	\
+				MICRON_TRCD_200, MICRON_TRRD_200,	\
+				MICRON_TDPL_200, MICRON_TDAL_200)
+
+#define MICRON_TWTR_200		2
+#define MICRON_TCKE_200		4
+#define MICRON_TXP_200		2
+#define MICRON_XSR_200		23
+#define MICRON_V_ACTIMB_200	\
+		ACTIM_CTRLB(MICRON_TWTR_200, MICRON_TCKE_200,	\
+				MICRON_TXP_200,	MICRON_XSR_200)
+
+#define MICRON_RASWIDTH_200	0x3
+#define MICRON_V_MCFG_200(size)	MCFG((size), MICRON_RASWIDTH_200)
+
 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
 #define NUMONYX_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
 					/* 15/6 + 18/6 = 5.5 -> 6	*/

@@ -212,6 +238,9 @@ enum {
 		ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165,	\
 				NUMONYX_TXP_165, NUMONYX_XSR_165)
 
+#define NUMONYX_RASWIDTH_165		0x4
+#define NUMONYX_V_MCFG_165(size)	MCFG((size), NUMONYX_RASWIDTH_165)
+
 /*
  * GPMC settings -
  * Definitions is as per the following format

board/ti/beagle/beagle.c +69 -2

105 lines not on this page · raw message

board/ti/beagle/config.mk deleted +0 ~~-33~~

deleted file mode 100644
index cf055db..0000000
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2006
-# Texas Instruments, <www.ti.com>
-#
-# Beagle Board uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000

include/configs/omap3_beagle.h +55 -4

75 lines not on this page · raw message

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #23 lore raw

PATCH v4 12/14 OMAP3: Add SPL support to omap3_evm

In reply to Tom Rini

Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.

Signed-off-by Tom Rini <[email protected]>

---
 arch/arm/include/asm/arch-omap3/mem.h  |   26 ++++++++++++++++++++
 board/ti/evm/config.mk                 |   33 -------------------------
 board/ti/evm/evm.c                     |   41 ++++++++++++++++++++++++++++++-
 include/configs/omap3_evm.h            |   27 +++++++++++++++++++++
 include/configs/omap3_evm_common.h     |   30 +++++++++++++++++++++-
 include/configs/omap3_evm_quick_mmc.h  |   10 +++++++
 include/configs/omap3_evm_quick_nand.h |   22 +++++++++++++++++
 7 files changed, 152 insertions(+), 37 deletions(-)
 delete mode 100644 board/ti/evm/config.mk

arch/arm/include/asm/arch-omap3/mem.h +26 -0

index 4ea5f74..5fd02d4 100644
@@ -123,6 +123,32 @@ enum {
 		V_MCFG_BANKALLOCATION_RBC |			\
 		V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR
 
+/* Hynix part of AM/DM37xEVM (200MHz optimized) */
+#define HYNIX_TDAL_200		6
+#define HYNIX_TDPL_200		3
+#define HYNIX_TRRD_200		2
+#define HYNIX_TRCD_200		4
+#define HYNIX_TRP_200		3
+#define HYNIX_TRAS_200		8
+#define HYNIX_TRC_200		11
+#define HYNIX_TRFC_200		18
+#define HYNIX_V_ACTIMA_200	\
+		ACTIM_CTRLA(HYNIX_TRFC_200, HYNIX_TRC_200,	\
+				HYNIX_TRAS_200, HYNIX_TRP_200,	\
+				HYNIX_TRCD_200, HYNIX_TRRD_200,	\
+				HYNIX_TDPL_200, HYNIX_TDAL_200)
+
+#define HYNIX_TWTR_200		2
+#define HYNIX_TCKE_200		1
+#define HYNIX_TXP_200		1
+#define HYNIX_XSR_200		28
+#define HYNIX_V_ACTIMB_200	\
+		ACTIM_CTRLB(HYNIX_TWTR_200, HYNIX_TCKE_200,	\
+				HYNIX_TXP_200, HYNIX_XSR_200)
+
+#define HYNIX_RASWIDTH_200	0x3
+#define HYNIX_V_MCFG_200(size)	MCFG((size), HYNIX_RASWIDTH_200)
+
 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
 #define INFINEON_TDAL_165	6	/* Twr/Tck + Trp/tck		*/
 					/* 15/6 + 18/6 = 5.5 -> 6	*/

board/ti/evm/config.mk deleted +0 ~~-33~~

deleted file mode 100644
index d173eef..0000000
@@ -1,33 +0,0 @@
-#
-# (C) Copyright 2006 - 2008
-# Texas Instruments, <www.ti.com>
-#
-# EVM uses OMAP3 (ARM-CortexA8) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000

board/ti/evm/evm.c +39 -2

63 lines not on this page · raw message

include/configs/omap3_evm.h +27 -0

index 47ec39f..dc611ca 100644
@@ -84,6 +84,13 @@
 #define CONFIG_GENERIC_MMC
 #define CONFIG_OMAP_HSMMC
 #define CONFIG_DOS_PARTITION
+/* SPL */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
 
 /* USB
  *

@@ -94,6 +101,26 @@
 #define CONFIG_MUSB_HCD
 /* #define CONFIG_MUSB_UDC */
 
+/* NAND SPL */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
 /* -----------------------------------------------------------------------------
  * Include common board configuration
  * -----------------------------------------------------------------------------

include/configs/omap3_evm_common.h +28 -2

index 54aa7a7..a2aeb76 100644
@@ -27,7 +27,6 @@
 #define CONFIG_SDRC			/* The chip has SDRC controller */
 
 #define CONFIG_OMAP3_EVM		/* This is a OMAP3 EVM */
-#define CONFIG_OMAP3_MICRON_DDR		/* with MICRON DDR part */
 #define CONFIG_TWL4030_POWER		/* with TWL4030 PMIC */
 
 #undef CONFIG_USE_IRQ			/* no support for IRQs */

@@ -71,7 +70,6 @@
  */
 #define CONFIG_NR_DRAM_BANKS		2
 #define PHYS_SDRAM_1			OMAP34XX_SDRC_CS0
-#define PHYS_SDRAM_1_SIZE		(32 << 20)
 #define PHYS_SDRAM_2			OMAP34XX_SDRC_CS1
 
 /* SDRAM Bank Allocation method */

@@ -289,4 +287,32 @@
 /* Uncomment to define the board revision statically */
 /* #define CONFIG_STATIC_BOARD_REV	OMAP3EVM_BOARD_GEN_2 */
 
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x40200800
+#define CONFIG_SPL_MAX_SIZE		(45 * 1024)	/* 45 KB */
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_OMAP3_ID_NAND
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss@the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80100000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
 #endif /* __OMAP3_EVM_COMMON_H */

include/configs/omap3_evm_quick_mmc.h +10 -0

index 691e4c2..912da7d 100644
@@ -88,4 +88,14 @@
 	"root=/dev/mmcblk0p2 rw "	\
 	"rootfstype=ext3 rootwait"
 
+/*
+ * SPL
+ */
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
 #endif /* __OMAP3_EVM_QUICK_MMC_H */

include/configs/omap3_evm_quick_nand.h +22 -0

index 2d18314..2f879c0 100644
@@ -76,4 +76,26 @@
 	"root=/dev/mtdblock4 rw "	\
 	"rootfstype=jffs2 "
 
+/*
+ * SPL
+ */
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
+						10, 11, 12, 13}
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
 #endif /* __OMAP3_EVM_QUICK_NAND_H */

Signature · 1 line

1.7.0.4

Tom Rini

2011-11-29 22:20 UTC #24 lore raw

PATCH v4 12/14 OMAP3: Add SPL support to omap3_evm

Quoted 4 lines · Tom Rini

Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. This also changes CONFIG_SYS_TEXT_BASE to 0x80100000.
Signed-off-by Tom Rini <[email protected]>

In ToT we now have EFI partition table support in the 'full' build. I'm disabling EFI support for SPL since that's something that the ROM code won't grok anyhow (or rather, it would only grok the compat table and look there for what it needs). This is only noticed since EFI needs crc32 support which we don't expose to SPL today.

Signature · 1 line

Tom

Tom Rini

author

2011-11-18 22:48 UTC #25 lore raw

PATCH v4 13/14 AM3517: Add SPL support

In reply to Tom Rini

The only change of note is that we move from 0x80008000 to 0x80100000 for CONFIG_SYS_TEXT_BASE

Cc Vaibhav Hiremath <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 board/logicpd/am3517evm/am3517evm.c |    2 +-
 board/logicpd/am3517evm/config.mk   |   30 ------------------
 include/configs/am3517_evm.h        |   57 +++++++++++++++++++++++++++++++++-
 3 files changed, 56 insertions(+), 33 deletions(-)
 delete mode 100644 board/logicpd/am3517evm/config.mk

board/logicpd/am3517evm/am3517evm.c +1 -1

index c0a006a..0a105bf 100644
@@ -76,7 +76,7 @@ void set_muxconf_regs(void)
 	MUX_AM3517EVM();
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
        omap_mmc_init(0);

board/logicpd/am3517evm/config.mk deleted +0 ~~-30~~

deleted file mode 100644
index 71ec5d0..0000000
@@ -1,30 +0,0 @@
-#
-# Author: Vaibhav Hiremath <[email protected]>
-#
-# Based on ti/evm/config.mk
-#
-# Copyright (C) 2010
-# Texas Instruments Incorporated - http://www.ti.com/
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000

include/configs/am3517_evm.h +55 -2

73 lines not on this page · raw message

Signature · 1 line

1.7.0.4

Tom Rini

author

2011-11-18 22:48 UTC #26 lore raw

PATCH v4 14/14 AM3517 CraneBoard: Add SPL support

In reply to Tom Rini

The only change of note is that we move from 0x80008000 to 0x80100000 for CONFIG_SYS_TEXT_BASE

Cc Nagendra T S <[email protected]>

Tested-by Koen Kooi <[email protected]>

Signed-off-by Tom Rini <[email protected]>

---
 board/ti/am3517crane/am3517crane.c |    2 +-
 board/ti/am3517crane/config.mk     |   29 ------------------
 include/configs/am3517_crane.h     |   57 ++++++++++++++++++++++++++++++++++-
 3 files changed, 56 insertions(+), 32 deletions(-)
 delete mode 100644 board/ti/am3517crane/config.mk

board/ti/am3517crane/am3517crane.c +1 -1

index cd5683d..436645a 100644
@@ -75,7 +75,7 @@ void set_muxconf_regs(void)
 	MUX_AM3517CRANE();
 }
 
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
 int board_mmc_init(bd_t *bis)
 {
 	omap_mmc_init(0);

board/ti/am3517crane/config.mk deleted +0 ~~-29~~

deleted file mode 100644
index c6a18b5..0000000
@@ -1,29 +0,0 @@
-#
-# Author: Srinath R <[email protected]>
-#
-# Based on logicpd/am3517evm/config.mk
-#
-# Copyright (C) 2011 Mistral Solutions Pvt Ltd
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 2 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-#
-# Physical Address:
-# 8000'0000 (bank0)
-# A000/0000 (bank1)
-# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
-# (mem base + reserved)
-
-# For use with external or internal boots.
-CONFIG_SYS_TEXT_BASE = 0x80008000

include/configs/am3517_crane.h +55 -2

73 lines not on this page · raw message

Signature · 1 line

1.7.0.4

Tom Rini

2011-11-29 21:55 UTC #27 lore raw

v4 cover Add more framework to OMAP3 SPL, port more boards

In reply to Tom Rini

Quoted 46 lines · Tom Rini

Hey all,
This is related to, but a bit different from the RFT thread I made with beagleboard SPL patches. ?I've incorporated the feedback about splitting the changes up a lot more and after talking with Scott Wood on IRC after the ML thread, I've created an omap3 specific file with the NAND related stuff these boards need (since it would have gotten very big for what's really needed here at this stage). ?The series is checkpatch.pl clean.
What we have in patches 1-8 is bugfixing and cleanup of the memory code. It's worth noting that without these changes we do some very 'funny' (read: wrong) things on some platforms like omap3_evm where we find 384MB memory when there's really only 256MB (and maybe 256 on the 128MB boards, not sure).
Patch 9 adds another hook for SDRC boards to be able to say what timings they have because on say beagle or omap3_evm, we have a few choices. ?We also convert devkit8000 here.
Patch 10 adds a new CONFIG (CONFIG_SPL_OMAP3_ID_NAND) and file so that OMAP3 boards which have a PoP chip for NAND/DDR can find out what they are and decide on timings based on that.
Patches 11 and 12 convert Beagleboard and OMAP3 EVM to SPL.
Patches 13 and 14 convert the am3517 evm and am3517 crane boards (which don't use SDRC but EMIF4) to SPL as well (given Ilya Yanok fixed a bug in <asm/arch-omap3/cpu.h> for emif4 this is just a mechanical change).
Changes in v4:
- Update this to match the feedback I'd incorporated before
- Update enable_gpmc_cs_config to not use so many magic values ?and explain the bitshifts.
- Add MCFG macro to calculate this value for the various DDR chips ?that are in use.
- Enhance the comments in <asm/arch-omap3/mem.h> to say to read the ?TRM to understand what all possible values are and bitshifts and ?update the comments about rfr_ctrl to explain why they aren't broken ?into values + shifts.
- The above three should cover all of Heiko Schocher's feedback.
Changes in v3:
- Rename CONFIG_SPL_OMAP3_POP_PROBE to CONFIG_SPL_OMAP3_ID_NAND at Igor's ?request (and function to identify_nand_chip).
- Drop an unused CONFIG_OMAP3_MICRON_DDR from all of the board config files

Quoted 6 lines

Changes in v2:
- Incorporate Igor Grinberg's feedback (except non-CodingStyle whitespacing).
- Move to ToT (so omap3_evm patch is reworked a good deal, others that ?touch <asm/arch-omap3/mem.h> reworked and use new macros when applicable)
- Fixed a few more typos and hardcoded values to defines while addressing ?Igor's feedback.

After talking with Wolfgang, this will be merged to u-boot-ti.

Signature · 1 line

Tom