i.mx: add the initial i.mx6q core/board support

In order to support the coming MX6 platform and to reducde the duplicated code, we had better move some common files or functions to the imx-common folder for sharing.

This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature added but just fix the checkpatch errors in the old file and remove the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6

Signed-off-by Jason Liu <[email protected]>

Cc Stefano Babic <[email protected]>

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

Cc Stefano Babic <[email protected]>

---
v2:put aips init to c code as Marek suggest
remove the parenthesis such as (2)
remork get_usdhcx_clk() to get_usdhc_clk(port) remove the iomux base init and assign it staticly correct the chip rev print-message(rev1.0)
---

arch/arm/cpu/armv7/mx6/clock.c new file +5 -0

+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/ccm_regs.h>

arch/arm/cpu/armv7/mx6/clock.c new file +4 -0

+
+	printf("\n");
+	printf("IPG             %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+	printf("UART            %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);

arch/arm/cpu/armv7/mx6/soc.c new file +32 -0

new file mode 100644
index 0000000..dbf8b93
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+

arch/arm/include/asm/arch-mx6/gpio.h new file +25 -0

new file mode 100644
index 0000000..20c4e57
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_MX6_GPIO_H

+++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h

arch/arm/include/asm/arch-mx6/gpio.h new file +46 -0

@@ -0,0 +1,1683 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6X_PINS_H__
+#define __ASM_ARCH_MX6_MX6X_PINS_H__
+
+#include <asm/arch/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS		(1 << 16)
+#define PAD_CTL_PUS_100K_DOWN	(0 << 14)
+#define PAD_CTL_PUS_47K_UP	(1 << 14)
+#define PAD_CTL_PUS_100K_UP	(2 << 14)
+#define PAD_CTL_PUS_22K_UP	(3 << 14)
+
+#define PAD_CTL_PUE		(1 << 13)
+#define PAD_CTL_PKE		(1 << 12)
+#define PAD_CTL_ODE		(1 << 11)
+#define PAD_CTL_SPEED_LOW	(1 << 6)
+#define PAD_CTL_SPEED_MED	(2 << 6)
+#define PAD_CTL_SPEED_HIGH	(3 << 6)
+#define PAD_CTL_DSE_DISABLE	(0 << 3)
+#define PAD_CTL_DSE_240ohm	(1 << 3)
+#define PAD_CTL_DSE_120ohm	(2 << 3)
+#define PAD_CTL_DSE_80ohm	(3 << 3)
+#define PAD_CTL_DSE_60ohm	(4 << 3)
+#define PAD_CTL_DSE_48ohm	(5 << 3)
+#define PAD_CTL_DSE_40ohm	(6 << 3)

Quoted 5 lines · Jason Liu

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

Signed-off-by Jason Liu <[email protected]>

Cc Stefano Babic <[email protected]>

Quoted 7 lines

---
v2:put aips init to c code as Marek suggest ? ?remove the parenthesis such as (2)
? ?remork get_usdhcx_clk() to get_usdhc_clk(port) ? ?remove the iomux base init and assign it staticly ? ?correct the chip rev print-message(rev1.0)
---

Hi Jason,

please understand I cannot go deep into the review due to not yet published user manual - my comments are more related to how your code can be integrated in current IMX code.

Quoted 11 lines

arch/arm/cpu/armv7/mx6/clock.c new file +10 -0

+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/clock.h>
+
+enum pll_clocks {
+ ? ? PLL_SYS, ? ? ? ?/* System PLL */
+ ? ? PLL_BUS, ? ? ? ?/* System Bus PLL*/

arch/arm/cpu/armv7/mx6/clock.c line 37

Quoted 5 lines

+ ? ? PLL_USBOTG, ? ? /* OTG USB PLL */
+ ? ? PLL_ENET, ? ? ? /* ENET PLL */

arch/arm/cpu/armv7/mx6/clock.c new file +3 -0

+};
+
+struct imx_ccm_reg *imx_ccm = (struct imx_ccm_reg *)CCM_BASE_ADDR;

Is it ok to initialize it here ? How does it work before and after relocation ?

arch/arm/cpu/armv7/mx6/clock.c line 73

Quoted 6 lines

arch/arm/cpu/armv7/mx6/clock.c new file +5 -0

+
+ ? ? return PLL3_80M / (uart_podf + 1);
+}
+
+

One newline too much

Quoted 6 lines

+ ? ? if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
+ ? ? ? ? ? ? if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
+ ? ? ? ? ? ? ? ? ? ? root_freq = PLL2_PFD2_FREQ;
+ ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? root_freq = PLL3_PFD1_FREQ;;

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^---one is enough Drop the redundant semicolon.

arch/arm/cpu/armv7/mx6/clock.c line 239

Quoted 9 lines

arch/arm/cpu/armv7/mx6/clock.c new file +8 -0

+static u32 get_mmdc_ch0_clk(void)
+{
+ ? ? u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
+ ? ? u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+
+ ? ? return get_periph_clk() / (mmdc_ch0_podf + 1);
+}

add a newline here

arch/arm/cpu/armv7/mx6/clock.c line 286

Quoted 5 lines

arch/arm/cpu/armv7/mx6/clock.c new file +4 -0

+u32 imx_get_uartclk(void)
+{
+ ? ? return get_uart_clk();
+}

This is ok - but I think we should switch to mxc_get_clock(MXC_UART_CLK) in serial_mxc.c. However, this should be done in another patch.

Quoted 15 lines

+
+ ? ? printf("\n");
+ ? ? printf("IPG ? ? ? ? ? ? %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
+ ? ? printf("UART ? ? ? ? ? ?%8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
+ ? ? printf("CSPI ? ? ? ? ? ?%8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+ ? ? printf("AHB ? ? ? ? ? ? %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
+ ? ? printf("AXI ? ? ? ? ? ? %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
+ ? ? printf("DDR ? ? ? ? ? ? %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
+ ? ? printf("USDHC1 ? ? ? ? ?%8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
+ ? ? printf("USDHC2 ? ? ? ? ?%8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
+ ? ? printf("USDHC3 ? ? ? ? ?%8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
+ ? ? printf("USDHC4 ? ? ? ? ?%8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
+ ? ? printf("EMI SLOW ? ? ? ?%8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
+ ? ? printf("IPG PERCLK ? ? ?%8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);

Not yet checked, but it seems to me that some lines are too long, are'nt they ?

Quoted 46 lines

arch/arm/cpu/armv7/mx6/soc.c new file +39 -0

new file mode 100644
index 0000000..dbf8b93
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+
+u32 get_cpu_rev(void)
+{
+ ? ? int system_rev = 0x61000 | CHIP_REV_1_0;
+
+ ? ? return system_rev;
+}
+#ifdef CONFIG_ARCH_CPU_INIT

arch/arm/cpu/armv7/mx6/soc.c

Quoted 3 lines

arch/arm/cpu/armv7/mx6/soc.c new file +3 -0

+void init_aips(void)
+{
+ ? ? u32 reg = AIPS1_ON_BASE_ADDR;

I know that in manual (MX51, at least) this range is called AIPS1_ON_PLATFORM, but we used the name AIPS1_BASE_ADDR for MX51 and MX53. Could we stick with the same name ? It is easier for everybody starting with IMX if the registers with the same meaning.

Quoted 4 lines

arch/arm/cpu/armv7/mx6/soc.c new file +3 -0

+
+ ? ? /*
+ ? ? ?* Set all MPROTx to be non-bufferable, trusted for R/W,

arch/arm/cpu/armv7/mx6/soc.c line 55

Quoted 10 lines

arch/arm/cpu/armv7/mx6/soc.c new file +10 -0

+ ? ? ?* not forced to user-mode.
+ ? ? ?*/
+ ? ? writel(0x77777777, reg + 0x00);
+ ? ? writel(0x77777777, reg + 0x04);
+
+ ? ? writel(0x00000000, reg + 0x40);
+ ? ? writel(0x00000000, reg + 0x44);
+ ? ? writel(0x00000000, reg + 0x48);
+ ? ? writel(0x00000000, reg + 0x4c);
+ ? ? writel(0x00000000, reg + 0x50);

I would prefer to have a structure (as described in AIPSTZ Register Memory Map) for this instead of a raw translating of the assembly routine.

arch/arm/include/asm/arch-mx6/ccm_regs.h line 2

Quoted 9 lines

arch/arm/include/asm/arch-mx6/ccm_regs.h new file +2 -0

new file mode 100644
index 0000000..b55cb49
@@ -0,0 +1,894 @@
+/*
+ * Freescale ANADIG Register Definitions

? ? ? ? ? ? ? ? ?^---

ANADIG: this is new. What is ?

Quoted 37 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +29 -0

new file mode 100644
index 0000000..20c4e57
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_MX6_GPIO_H
+#define __ASM_ARCH_MX6_GPIO_H
+
+/* GPIO registers */
+struct gpio_regs {

arch/arm/include/asm/arch-mx6/gpio.h line 35

Quoted 6 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +6 -0

+ ? ? u32 ? ? gpio_dr;
+ ? ? u32 ? ? gpio_dir;
+ ? ? u32 ? ? gpio_psr;
+};
+
+#endif ? ? ? /* __ASM_ARCH_MX6_GPIO_H */

What about the proposal to have a common include path ?

Quoted 57 lines

+++ b/arch/arm/include/asm/arch-mx6/mx6x_pins.h

arch/arm/include/asm/arch-mx6/gpio.h new file +54 -0

@@ -0,0 +1,1683 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Auto Generate file, please don't edit it
+ *
+ */
+
+#ifndef __ASM_ARCH_MX6_MX6X_PINS_H__
+#define __ASM_ARCH_MX6_MX6X_PINS_H__
+
+#include <asm/arch/iomux-v3.h>
+
+/* Use to set PAD control */
+#define PAD_CTL_HYS ? ? ? ? ?(1 << 16)
+#define PAD_CTL_PUS_100K_DOWN ? ? ? ?(0 << 14)
+#define PAD_CTL_PUS_47K_UP ? (1 << 14)
+#define PAD_CTL_PUS_100K_UP ?(2 << 14)
+#define PAD_CTL_PUS_22K_UP ? (3 << 14)
+
+#define PAD_CTL_PUE ? ? ? ? ?(1 << 13)
+#define PAD_CTL_PKE ? ? ? ? ?(1 << 12)
+#define PAD_CTL_ODE ? ? ? ? ?(1 << 11)
+#define PAD_CTL_SPEED_LOW ? ?(1 << 6)
+#define PAD_CTL_SPEED_MED ? ?(2 << 6)
+#define PAD_CTL_SPEED_HIGH ? (3 << 6)
+#define PAD_CTL_DSE_DISABLE ?(0 << 3)
+#define PAD_CTL_DSE_240ohm ? (1 << 3)
+#define PAD_CTL_DSE_120ohm ? (2 << 3)
+#define PAD_CTL_DSE_80ohm ? ?(3 << 3)
+#define PAD_CTL_DSE_60ohm ? ?(4 << 3)
+#define PAD_CTL_DSE_48ohm ? ?(5 << 3)
+#define PAD_CTL_DSE_40ohm ? ?(6 << 3)
+#define PAD_CTL_DSE_34ohm ? ?(7 << 3)
+#define PAD_CTL_SRE_FAST ? ? (1 << 0)
+#define PAD_CTL_SRE_SLOW ? ? (0 << 0)
+
+#define NO_MUX_I ? ? ? ? ? ? 0x3FF
+#define NO_PAD_I ? ? ? ? ? ? 0x7FF
+
+enum {

arch/arm/include/asm/arch-mx6/gpio.h line 56

Quoted 2 lines

arch/arm/include/asm/arch-mx6/gpio.h new file +2 -0

+ ? ? MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 ? ? ? ? ?= IOMUX_PAD(0x0360, 0x004C, 0, 0x0000, 0, 0),
+ ? ? MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 ? ? ? ? ? = IOMUX_PAD(0x0360, 0x004C, 1, 0x0834, 0, 0),

Only to remark. These lines will be marked with WARNING by checkpatch, but it is surely more readable as it is in the patch as if each line will be split. I have already merged the MX28 iomux, and even in that case the single lines were longer as 80 bytes. If nobody complains, I will merge the pin definition as it is.

Best regards,
Stefano Babic

--
=====================================================================
DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
=====================================================================

Hi Jason,

? ? ? ?What about using

#ifdef GPIO4_BASE_ADDR
? ? ? ?[3] = GPIO4_BASE_ADDR,
#endif

? ? ? ?Then we can avoid adding SOC compile options in future.

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2011/11/18 Lv Terry-R65388 <[email protected]>:

Quoted 7 lines

Hi Jason,

What about using

#ifdef GPIO4_BASE_ADDR
       [3] = GPIO4_BASE_ADDR,

#endif

[...]

Quoted 1 line

Then we can avoid adding SOC compile options in future.

Terry, please don't top-post. As for your comments, I don't think so, first, we should not simply use GPIOx_BASE_ADDR, and second, it will introduce a lot of other platforms changes.

Jason Liu

Quoted 13 lines

2011/11/18 Lv Terry-R65388 <[email protected]>:

Quoted 7 lines

Hi Jason,

? ? ? ?What about using

#ifdef GPIO4_BASE_ADDR
? ? ? ?[3] = GPIO4_BASE_ADDR,
#endif

[...]

Quoted 1 line

? ? ? ?Then we can avoid adding SOC compile options in future.

Quoted 5 lines

Terry, please don't top-post. As for your comments, I don't think so, first, we should not simply use GPIOx_BASE_ADDR, and second, it will introduce a lot of other platforms changes.

Jason Liu

So it's Jason Liu or Jason Hui ?! What the heck is your name ?

M

Quoted 17 lines · Marek Vasut

Quoted 17 lines

2011/11/18 Lv Terry-R65388 <[email protected]>:

Quoted 7 lines

Hi Jason,

What about using

#ifdef GPIO4_BASE_ADDR
       [3] = GPIO4_BASE_ADDR,

#endif

[...]

Quoted 1 line

Then we can avoid adding SOC compile options in future.

Terry, please don't top-post. As for your comments, I don't think so, first, we should not simply use GPIOx_BASE_ADDR, and second, it will introduce a lot of other platforms changes.

Quoted 3 lines

Quoted 1 line

Jason Liu

So it's Jason Liu or Jason Hui ?! What the heck is your name ?

There is some mistake when linaro assign me the email address. in fact, it should be jason.liu at linaro.org. But anyway, I don't care about it. Sorry to make you confuse. ;)

Quoted 24 lines · Marek Vasut

Quoted 22 lines

Quoted 13 lines

2011/11/18 Lv Terry-R65388 <[email protected]>:

Quoted 9 lines

Hi Jason,

What about using

#ifdef GPIO4_BASE_ADDR

       [3] = GPIO4_BASE_ADDR,

#endif

[...]

Quoted 7 lines

Quoted 1 line

Then we can avoid adding SOC compile options in future.

Terry, please don't top-post. As for your comments, I don't think so, first, we should not simply use GPIOx_BASE_ADDR, and second, it will introduce a lot of other platforms changes.

Jason Liu

So it's Jason Liu or Jason Hui ?! What the heck is your name ?

Quoted 3 lines

There is some mistake when linaro assign me the email address. in fact, it should be jason.liu at linaro.org. But anyway, I don't care about it. Sorry to make you confuse. ;)

but the "Jason Hui" part is controlled purely on your side :). only the "jason.hui at linaro.org" is controlled by Linaro.
-mike

Quoted 25 lines · On Friday 18 November 2011 07:26:59 Jason Hui wrote:

Quoted 24 lines · Marek Vasut

Quoted 22 lines

Quoted 13 lines

2011/11/18 Lv Terry-R65388 <[email protected]>:

Quoted 9 lines

Hi Jason,

What about using

#ifdef GPIO4_BASE_ADDR

       [3] = GPIO4_BASE_ADDR,

#endif

[...]

Quoted 7 lines

Quoted 1 line

Then we can avoid adding SOC compile options in future.

Terry, please don't top-post. As for your comments, I don't think so, first, we should not simply use GPIOx_BASE_ADDR, and second, it will introduce a lot of other platforms changes.

Jason Liu

So it's Jason Liu or Jason Hui ?! What the heck is your name ?

Quoted 6 lines

Quoted 3 lines

There is some mistake when linaro assign me the email address. in fact, it should be jason.liu at linaro.org. But anyway, I don't care about it. Sorry to make you confuse. ;)

but the "Jason Hui" part is controlled purely on your side :). only the "jason.hui at linaro.org" is controlled by Linaro.

Not really ... you can fake both ;-D

Signed-off-by Jason Liu <[email protected]>

Cc Stefano Babic <[email protected]>

---
v2: Cc Stefano

---
 drivers/serial/serial_mxc.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

drivers/serial/serial_mxc.c +2 -2

index dcb4bd1..7d0f288 100644
@@ -47,14 +47,18 @@
 #elif defined(CONFIG_SYS_MX27_UART6)
 #define UART_PHYS 0x1001c000
 #elif defined(CONFIG_SYS_MX35_UART1) || defined(CONFIG_SYS_MX51_UART1) || \
-	defined(CONFIG_SYS_MX53_UART1)
+	defined(CONFIG_SYS_MX53_UART1) || defined(CONFIG_MX6Q_UART1)
 #define UART_PHYS UART1_BASE_ADDR
 #elif defined(CONFIG_SYS_MX35_UART2) || defined(CONFIG_SYS_MX51_UART2) || \
-	defined(CONFIG_SYS_MX53_UART2)
+	defined(CONFIG_SYS_MX53_UART2) || defined(CONFIG_MX6Q_UART2)
 #define UART_PHYS UART2_BASE_ADDR
 #elif defined(CONFIG_SYS_MX35_UART3) || defined(CONFIG_SYS_MX51_UART3) || \

Quoted 31 lines · Jason Liu

Signed-off-by Jason Liu <[email protected]>

Cc Stefano Babic <[email protected]>

---
v2: Cc Stefano
---
?drivers/serial/serial_mxc.c | ? 10 +++++++---
?1 files changed, 7 insertions(+), 3 deletions(-)

drivers/serial/serial_mxc.c +0 -0

index dcb4bd1..7d0f288 100644
@@ -47,14 +47,18 @@
 ?#elif defined(CONFIG_SYS_MX27_UART6)

?#define UART_PHYS 0x1001c000
?#elif defined(CONFIG_SYS_MX35_UART1) || defined(CONFIG_SYS_MX51_UART1) || \
- ? ? defined(CONFIG_SYS_MX53_UART1)
+ ? ? defined(CONFIG_SYS_MX53_UART1) || defined(CONFIG_MX6Q_UART1) ?#define UART_PHYS UART1_BASE_ADDR
?#elif defined(CONFIG_SYS_MX35_UART2) || defined(CONFIG_SYS_MX51_UART2) || \
- ? ? defined(CONFIG_SYS_MX53_UART2)
+ ? ? defined(CONFIG_SYS_MX53_UART2) || defined(CONFIG_MX6Q_UART2) ?#define UART_PHYS UART2_BASE_ADDR
?#elif defined(CONFIG_SYS_MX35_UART3) || defined(CONFIG_SYS_MX51_UART3) || \
- ? ? defined(CONFIG_SYS_MX53_UART3)
+ ? ? defined(CONFIG_SYS_MX53_UART3) || defined(CONFIG_MX6Q_UART3) ?#define UART_PHYS UART3_BASE_ADDR

drivers/serial/serial_mxc.c +4 -0

+#elif defined(CONFIG_MX6Q_UART4)
+#define UART_PHYS UART4_BASE_ADDR
+#elif defined(CONFIG_MX6Q_UART5)
+#define UART_PHYS UART5_BASE_ADDR

Quoted 3 lines

?#else
?#error "define CONFIG_SYS_MXxx_UARTx to use the MXC UART driver" ?#endif

This is not a comment of your patch, but I cannot avoid to note how much crap in this file. And we have not yet added all possible values for each SOC, only the values necessary to build the actual boards.

The worst thing is that we do not need all this stuff. We set a lot of #ifdef only to set the UART base address, and we really ignore (because unneeded) the CONFIG_SYS_*_UART_*. It should be really better to define the base address in the board configuration file, as we already do for other drivers (USB with ehci base address, SD,..). Maybe with a MXC_UART_BASE_ADDRESS, and we can get rid of all this bad stuff.

I will prepare a patch...

Best regards,
Stefano Babic

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Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
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The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except it adds one mix register to support debug/SD3.0 and move the low bit 0-6 of XFERTYP register to the mix control reg low bit 0-6. Thus on i.mx6q, we have the following compared with the previous soc: (can refer to RM of chapter 56.3.3)

i.mx6q:
mix control:
bit 31 - bit 7: Added for debug/SD3.0 support
bit 6 - bit 0: move in the XFERTYP register bit 6-0 on previous soc XFERTYP register:
bit 31 - bit 7: the same as before,
bit 6 - bit 0: no-use

previous soc
mix control: no
XFERTYP register:
bit 31 - bit 0: xfertype information

Signed-off-by Jason Liu <[email protected]>

CC Stefano Babic <[email protected]>

Acked-by Stefano Babic <[email protected]>

---
v2: extend the commit message by adding mix/xtertype register change
remove one #ifdef as Marek suggested
change the print of USDHC/ESDHC to SDHC

---
 drivers/mmc/fsl_esdhc.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

drivers/mmc/fsl_esdhc.c +8 -2

index ec953f0..ddd1b4c 100644
@@ -58,7 +58,8 @@ struct fsl_esdhc {
 	uint	autoc12err;
 	uint	hostcapblt;
 	uint	wml;
-	char	reserved1[8];
+	uint    mixctrl;
+	char    reserved1[4];
 	uint	fevt;
 	char	reserved2[168];
 	uint	hostver;

@@ -298,8 +299,13 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	/* Send the command */
 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
+#if defined(CONFIG_FSL_USDHC)
+	esdhc_write32(&regs->mixctrl,
+	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
+#else
 	esdhc_write32(&regs->xfertyp, xfertyp);
-
+#endif
 	/* Wait for the command to complete */
 	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
 		;