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ARM: mach-shmobile: AG5EVM GIC Sparse IRQ fix

PATCH In review Magnus Damm 2 participants 2 messages Nov 22, 2011

Subsystems (4)
Arm (32-bit) Arm sub-architectures SuperH Arm/RISC-V/Renesas architecture
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Magnus Damm

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PATCH 1/1 ARM: mach-shmobile: AG5EVM GIC Sparse IRQ fix

From: Magnus Damm <[email protected]>

Fix IRQ support on the AG5EVM board. The sh73a0 and the AG5EVM board make use of the ARM GIC hardware block as main interrupt controller. The following commit changed the default behaviour for non-device tree platforms and broke AG5EVM irq support:

f37a53c ARM: gic: fix irq_alloc_descs handling for sparse irq

Without this fix the following warning triggers at boot:

NR_IRQS:1024 nr_irqs:1024 1024

------------[ cut here ]------------
WARNING: at arch/arm/common/gic.c:607 gic_init+0x90/0x2e4()

Cannot allocate irq_descs @ IRQ16, assuming pre-allocated [<c000c868>] (unwind_backtrace+0x0/0xe0) from [<c001857c>] (warn_slowpath_commo) [<c001857c>] (warn_slowpath_common+0x48/0x60) from [<c00185d8>] (warn_slowpath_) [<c00185d8>] (warn_slowpath_fmt+0x2c/0x3c) from [<c029ee08>] (gic_init+0x90/0x2) [<c029ee08>] (gic_init+0x90/0x2e4) from [<c029f278>] (sh73a0_init_irq+0x30/0x18) [<c029f278>] (sh73a0_init_irq+0x30/0x184) from [<c029c0b4>] (init_IRQ+0x14/0x1c) [<c029c0b4>] (init_IRQ+0x14/0x1c) from [<c029a5cc>] (start_kernel+0x15c/0x2b8) [<c029a5cc>] (start_kernel+0x15c/0x2b8) from [<4000803c>] (0x4000803c)

---[ end trace 1b75b31a2719ed1c ]---

With this fix applied interrupts work as expected.

Signed-off-by Magnus Damm <[email protected]>

---

 arch/arm/mach-shmobile/board-ag5evm.c |    1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-shmobile/board-ag5evm.c +1 -0
@@ -607,6 +607,7 @@ struct sys_timer ag5evm_timer = {
 
 MACHINE_START(AG5EVM, "ag5evm")
 	.map_io		= ag5evm_map_io,
+	.nr_irqs	= NR_IRQS_LEGACY,
 	.init_irq	= sh73a0_init_irq,
 	.handle_irq	= shmobile_handle_irq_gic,
 	.init_machine	= ag5evm_init,
Acked-by on v1 1/1
#1 lore raw
Quoted 22 lines · Magnus Damm

From: Magnus Damm <[email protected]>

Fix IRQ support on the AG5EVM board. The sh73a0 and the AG5EVM board make use of the ARM GIC hardware block as main interrupt controller. The following commit changed the default behaviour for non-device tree platforms and broke AG5EVM irq support:

f37a53c ARM: gic: fix irq_alloc_descs handling for sparse irq

Without this fix the following warning triggers at boot:

NR_IRQS:1024 nr_irqs:1024 1024

------------[ cut here ]------------
WARNING: at arch/arm/common/gic.c:607 gic_init+0x90/0x2e4()

Cannot allocate irq_descs @ IRQ16, assuming pre-allocated [<c000c868>] (unwind_backtrace+0x0/0xe0) from [<c001857c>] (warn_slowpath_commo) [<c001857c>] (warn_slowpath_common+0x48/0x60) from [<c00185d8>] (warn_slowpath_) [<c00185d8>] (warn_slowpath_fmt+0x2c/0x3c) from [<c029ee08>] (gic_init+0x90/0x2) [<c029ee08>] (gic_init+0x90/0x2e4) from [<c029f278>] (sh73a0_init_irq+0x30/0x18) [<c029f278>] (sh73a0_init_irq+0x30/0x184) from [<c029c0b4>] (init_IRQ+0x14/0x1c) [<c029c0b4>] (init_IRQ+0x14/0x1c) from [<c029a5cc>] (start_kernel+0x15c/0x2b8) [<c029a5cc>] (start_kernel+0x15c/0x2b8) from [<4000803c>] (0x4000803c)

Quoted 4 lines
---[ end trace 1b75b31a2719ed1c ]---

With this fix applied interrupts work as expected.

They work without the fix as well, right?

Quoted 2 lines
Signed-off-by Magnus Damm <[email protected]>

---

For both patches:

Acked-by Rob Herring <[email protected]>
Quoted 14 lines
 arch/arm/mach-shmobile/board-ag5evm.c |    1 +
 1 file changed, 1 insertion(+)
arch/arm/mach-shmobile/board-ag5evm.c +1 -0
@@ -607,6 +607,7 @@ struct sys_timer ag5evm_timer = {
 
 MACHINE_START(AG5EVM, "ag5evm")
 	.map_io		= ag5evm_map_io,
+	.nr_irqs	= NR_IRQS_LEGACY,
 	.init_irq	= sh73a0_init_irq,
 	.handle_irq	= shmobile_handle_irq_gic,
 	.init_machine	= ag5evm_init,