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armv7: miscellaneous fixes improvements

PATCH New Aneesh V 2 participants 6 messages Nov 22, 2011

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Arm (32-bit) Arm/actions semi architecture
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Aneesh V

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#0 lore raw

cover armv7: miscellaneous fixes improvements

Aneesh V (4):
armv7: disable L2 cache in cleanup_before_linux()
armv7: include armv7/cpu.c in SPL build
armv7: setup vector
start.S: remove omap3 specific code from start.S

 arch/arm/cpu/armv7/Makefile              |    4 +-
 arch/arm/cpu/armv7/cpu.c                 |    1 +
 arch/arm/cpu/armv7/omap3/lowlevel_init.S |    8 ++++++
 arch/arm/cpu/armv7/start.S               |   38 ++++++++++++-----------------
 arch/arm/include/asm/arch-omap3/omap3.h  |    1 +
 5 files changed, 28 insertions(+), 24 deletions(-)
author
#1 lore raw

PATCH 1/4 armv7: disable L2 cache in cleanup_before_linux()

We were not disabling external caches before jumping to kernel. We were flushing all caches including external caches and disabling caches globally in CP15 System Control register. Apparently this is not enough.

The bootstrap loader in Linux kernel that does decompression enables data-caches again, flush them after use and disable them before jumping to kernel proper. However, it's not aware of the external caches.

Since we have left external cache enabled, external cache will get used once caches are enabled globally, but it's not flushed because decompressor is not aware of external caches. When it jumps to kernel with caches disabled globally, we have stale data in the external cache and a coherency problem.

This was breaking the boot for OMAP4 with latest mainline kernel. The solution is to disable external caches in cleanup_before_linux(). With this fix kernel is booting again.

Cc Albert Aribaud <[email protected]>
Signed-off-by Aneesh V <[email protected]>
---
 arch/arm/cpu/armv7/cpu.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/cpu.c +1 -0
index 091e3e0..662c496 100644
@@ -65,6 +65,7 @@ int cleanup_before_linux(void)
 	 * dcache_disable() in turn flushes the d-cache and disables MMU
 	 */
 	dcache_disable();
+	v7_outer_cache_disable();
 
 	/*
 	 * After D-cache is flushed and before it is disabled there may
Signature · 1 line
1.7.1
author
#2 lore raw

PATCH 2/4 armv7: include armv7/cpu.c in SPL build

In reply to Aneesh V

This allows SPL to have default implementation of save_boot_params(), useful for SoCs that do not intend to override this default implementation

Cc Albert Aribaud <[email protected]>
Signed-off-by Aneesh V <[email protected]>
---
 arch/arm/cpu/armv7/Makefile |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/armv7/Makefile +2 -2
index 92a5a96..f97fa3d 100644
@@ -29,10 +29,10 @@ START	:= start.o
 
 ifndef CONFIG_SPL_BUILD
 COBJS	+= cache_v7.o
-COBJS	+= cpu.o
 endif
 
-COBJS  += syslib.o
+COBJS	+= cpu.o
+COBJS	+= syslib.o
 
 SRCS	:= $(START:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
Signature · 1 line
1.7.1
author
#3 lore raw

PATCH 3/4 armv7: setup vector

In reply to Aneesh V

The vector is not correctly setup in armv7 except for OMAP3. Correcting this.

Cc Albert Aribaud <[email protected]>
Signed-off-by Aneesh V <[email protected]>
---
 arch/arm/cpu/armv7/start.S |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/start.S +17 -0
index db8e9d2..f17763f 100644
@@ -32,6 +32,7 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <version.h>
+#include <asm/system.h>
 
 .globl _start
 _start: b	reset

@@ -143,6 +144,22 @@ reset:
 	orr	r0, r0, #0xd3
 	msr	cpsr,r0
 
+/*
+ * Setup vector:
+ * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
+ * Continue to use ROM code vector only in OMAP4 spl)
+ */
+#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
+	/* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
+	mrc	p15, 0, r0, c1, c0, 0	@ Read CP15 SCTRL Register
+	bic	r0, #CR_V		@ V = 0
+	mcr	p15, 0, r0, c1, c0, 0	@ Write CP15 SCTRL Register
+
+	/* Set vector address in CP15 VBAR register */
+	ldr	r0, =_start
+	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
+#endif
+
 #if defined(CONFIG_OMAP34XX)
 	/* Copy vectors to mask ROM indirect addr */
 	adr	r0, _start		@ r0 <- current position of code
Signature · 1 line
1.7.1
author
#4 lore raw

PATCH 4/4 start.S: remove omap3 specific code from start.S

In reply to Aneesh V
Cc Tom Rini <[email protected]>
Cc Albert Aribaud <[email protected]>
Signed-off-by Aneesh V <[email protected]>
---
 arch/arm/cpu/armv7/omap3/lowlevel_init.S |    8 ++++++++
 arch/arm/cpu/armv7/start.S               |   23 -----------------------
 arch/arm/include/asm/arch-omap3/omap3.h  |    1 +
 3 files changed, 9 insertions(+), 23 deletions(-)
arch/arm/cpu/armv7/omap3/lowlevel_init.S +8 -0
index a308ebd..2f6930b 100644
@@ -216,6 +216,14 @@ lowlevel_init:
 	ldr	sp, SRAM_STACK
 	str	ip, [sp]	/* stash old link register */
 	mov	ip, lr		/* save link reg across call */
+#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
+/*
+ * No need to copy/exec the clock code - DPLL adjust already done
+ * in NAND/oneNAND Boot.
+ */
+	ldr	r1, =SRAM_CLK_CODE
+	bl	cpy_clk_code
+#endif /* NAND Boot */
 	bl	s_init		/* go setup pll, mux, memory */
 	ldr	ip, [sp]	/* restore save ip */
 	mov	lr, ip		/* restore link reg */
arch/arm/cpu/armv7/start.S +0 -23
index f17763f..d23dc9d 100644
@@ -160,29 +160,6 @@ reset:
 	mcr	p15, 0, r0, c12, c0, 0	@Set VBAR
 #endif
 
-#if defined(CONFIG_OMAP34XX)
-	/* Copy vectors to mask ROM indirect addr */
-	adr	r0, _start		@ r0 <- current position of code
-	add	r0, r0, #4		@ skip reset vector
-	mov	r2, #64			@ r2 <- size to copy
-	add	r2, r0, r2		@ r2 <- source end address
-	mov	r1, #SRAM_OFFSET0	@ build vect addr
-	mov	r3, #SRAM_OFFSET1
-	add	r1, r1, r3
-	mov	r3, #SRAM_OFFSET2
-	add	r1, r1, r3
-next:
-	ldmia	r0!, {r3 - r10}		@ copy from source address [r0]
-	stmia	r1!, {r3 - r10}		@ copy to   target address [r1]
-	cmp	r0, r2			@ until source end address [r2]
-	bne	next			@ loop until equal */
-#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
-	/* No need to copy/exec the clock code - DPLL adjust already done
-	 * in NAND/oneNAND Boot.
-	 */
-	bl	cpy_clk_code		@ put dpll adjust code behind vectors
-#endif /* NAND Boot */
-#endif
 	/* the mask ROM code should have PLL and others stable */
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
arch/arm/include/asm/arch-omap3/omap3.h +1 -0
index 02eb865..2b5e9ae 100644
@@ -153,6 +153,7 @@ struct gpio {
 #define SRAM_OFFSET2			0x0000F800
 #define SRAM_VECT_CODE			(SRAM_OFFSET0 | SRAM_OFFSET1 | \
 					 SRAM_OFFSET2)
+#define SRAM_CLK_CODE			(SRAM_VECT_CODE + 64)
 
 #define OMAP3_PUBLIC_SRAM_BASE		0x40208000 /* Works for GP & EMU */
 #define OMAP3_PUBLIC_SRAM_END		0x40210000
Signature · 1 line
1.7.1