Allow aligned byte and word writes to IOAPIC registers.
PATCH 1/1 Allow aligned byte and word writes to IOAPIC registers.
This fixes byte accesses to IOAPIC_REG_SELECT as mandated by at least the ICH10 and Intel Series 5 chipset specs. It also makes ioapic_mmio_write consistent with ioapic_mmio_read, which also allows byte and word accesses.
--- virt/kvm/ioapic.c | 17 +++++++++++++---- 1 files changed, 13 insertions(+), 4 deletions(-)
virt/kvm/ioapic.c +13 -4
@@ -332,9 +332,18 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, (void*)addr, len, val);ASSERT (!(addr &0xf ));/* check alignment */ -if (len ==4 || len ==8 ) - data = *(u32 *) val; -else { +switch (len) { +case 8 : +case 4 : + data = *(u32 *) val; +break ; +case 2 : + data = *(u16 *) val; +break ; +case 1 : + data = *(u8 *) val; +break ; +default :printk (KERN_WARNING "ioapic: Unsupported size %d\n" , len);return 0 ; }
@@ -343,7 +352,7 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,spin_lock (&ioapic->lock);switch (addr) {case IOAPIC_REG_SELECT : - ioapic->ioregsel = data; + ioapic->ioregsel = data &0xFF ;/* 8-bit register */ break ;case IOAPIC_REG_WINDOW :
Signature · 1 line
1.7.7.3
Quoted 4 lines · Julian Stecklina
This fixes byte accesses to
IOAPIC_REG_SELECTas mandated by at least the ICH10 and Intel Series 5 chipset specs. It also makesioapic_mmio_writeconsistent withioapic_mmio_read, which also allows byte and word accesses.
Your patch indents with spaces, while Linux uses tabs for indents.
Quoted 32 lines
Signed-off-by Julian Stecklina <[email protected]>--- virt/kvm/ioapic.c | 17 +++++++++++++---- 1 files changed, 13 insertions(+), 4 deletions(-)virt/kvm/ioapic.c +12
-3@@ -332,9 +332,18 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, (void*)addr, len, val);ASSERT (!(addr &0xf ));/* check alignment */ -if (len ==4 || len ==8 ) - data = *(u32 *) val; -else { +switch (len) { +case 8 : +case 4 : + data = *(u32 *) val; +break ; +case 2 : + data = *(u16 *) val; +break ; +case 1 : + data = *(u8 *) val; +break ; +default :printk (KERN_WARNING "ioapic: Unsupported size %d\n" , len);return 0 ; }
virt/kvm/ioapic.c static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, · line 358
Quoted 8 lines
virt/kvm/ioapic.c +1
-1@@ -343,7 +352,7 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,spin_lock (&ioapic->lock);switch (addr) {case IOAPIC_REG_SELECT : - ioapic->ioregsel = data; + ioapic->ioregsel = data &0xFF ;/* 8-bit register */ break ;case IOAPIC_REG_WINDOW :
This is a bit over-permissive in that it allows 8-byte writes to the IOWIN register. I guess it's okay though.
Signature · 1 line
error compiling committee.c: too many arguments to function
On Wed, Nov 23, 2011, Avi Kivity wrote about "Re: [PATCH] Allow aligned byte and word writes to IOAPIC registers.":
Quoted 7 lines · Julian Stecklina
Quoted 4 lines
This fixes byte accesses to
IOAPIC_REG_SELECTas mandated by at least the ICH10 and Intel Series 5 chipset specs. It also makesioapic_mmio_writeconsistent withioapic_mmio_read, which also allows byte and word accesses.Your patch indents with spaces, while Linux uses tabs for indents.
You might want to run scripts/checkpatch.pl on your patches before sending them - this will catch this and many other stylistic faux pas.
Signature · 4 lines
Nadav Har'El | Wednesday, Nov 23 2011, [email protected] |----------------------------------------- Phone +972-523-790466, ICQ 13349191 |Why do doctors call what they do http://nadav.harel.org.il |practice? Think about it.
Quoted 7 lines · Avi Kivity
Quoted 4 lines · Julian Stecklina
This fixes byte accesses to
IOAPIC_REG_SELECTas mandated by at least the ICH10 and Intel Series 5 chipset specs. It also makesioapic_mmio_writeconsistent withioapic_mmio_read, which also allows byte and word accesses.Your patch indents with spaces, while Linux uses tabs for indents.
True. I'll post a revised version in a minute. I think this is my second patch to Linux in total, so I am slowly getting there... Thanks for the patience.
Regards, Julian
PATCH v2 1/1 KVM: Allow aligned byte and word writes to IOAPIC registers.
In reply to Avi KivityThis fixes byte accesses to IOAPIC_REG_SELECT as mandated by at least the ICH10 and Intel Series 5 chipset specs. It also makes ioapic_mmio_write consistent with ioapic_mmio_read, which also allows byte and word accesses.
--- virt/kvm/ioapic.c | 15 ++++++++++++--- 1 files changed, 12 insertions(+), 3 deletions(-)
virt/kvm/ioapic.c +12 -3
@@ -332,9 +332,18 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len, (void*)addr, len, val);ASSERT (!(addr &0xf ));/* check alignment */ -if (len ==4 || len ==8 ) +switch (len) { +case 8 : +case 4 : data = *(u32 *) val; -else { +break ; +case 2 : + data = *(u16 *) val; +break ; +case 1 : + data = *(u8 *) val; +break ; +default :printk (KERN_WARNING "ioapic: Unsupported size %d\n" , len);return 0 ; }
@@ -343,7 +352,7 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,spin_lock (&ioapic->lock);switch (addr) {case IOAPIC_REG_SELECT : - ioapic->ioregsel = data; + ioapic->ioregsel = data &0xFF ;/* 8-bit register */ break ;case IOAPIC_REG_WINDOW :
Signature · 1 line
1.7.7.3
Avi Kivity
AppliedRe: [PATCHv2] KVM: Allow aligned byte and word writes to IOAPIC registers.
Quoted 4 lines · Julian Stecklina
This fixes byte accesses to
IOAPIC_REG_SELECTas mandated by at least the ICH10 and Intel Series 5 chipset specs. It also makesioapic_mmio_writeconsistent withioapic_mmio_read, which also allows byte and word accesses.
Applied, thanks.
Signature · 1 line
error compiling committee.c: too many arguments to function