Versatile Express DT support

This patch gets rid of the MMIO_P2V and __MMPIO_P2V macros, defining constant virtual base for motherboard and tile peripherals instead.

Additionally, in preparation for the new motherboard memory map, the motherboard peripherals are using base pointers calculated in runtime, instead of compile-time calculated values.

Signed-off-by Pawel Moll <[email protected]>

---
 arch/arm/include/asm/hardware/arm_timer.h         |    5 ++
 arch/arm/mach-vexpress/core.h                     |   11 ++-
 arch/arm/mach-vexpress/ct-ca9x4.c                 |   52 +++-----------
 arch/arm/mach-vexpress/include/mach/ct-ca9x4.h    |   13 ++--
 arch/arm/mach-vexpress/include/mach/motherboard.h |   52 +++++++-------
 arch/arm/mach-vexpress/platsmp.c                  |    4 +-
 arch/arm/mach-vexpress/v2m.c                      |   76 +++++++++++++--------
 7 files changed, 104 insertions(+), 109 deletions(-)

arch/arm/include/asm/hardware/arm_timer.h +5 -0

index c0f4e7b..d6030ff 100644
@@ -9,7 +9,12 @@
  *
  * Integrator AP has 16-bit timers, Integrator CP, Versatile and Realview
  * can have 16-bit or 32-bit selectable via a bit in the control register.
+ *
+ * Every SP804 contains two identical timers.
  */
+#define TIMER_1_BASE	0x00
+#define TIMER_2_BASE	0x20
+
 #define TIMER_LOAD	0x00			/* ACVR rw */
 #define TIMER_VALUE	0x04			/* ACVR ro */
 #define TIMER_CTRL	0x08			/* ACVR rw */

arch/arm/mach-vexpress/core.h +8 -3

index f439715..d3dd491 100644
@@ -1,6 +1,3 @@
-#define __MMIO_P2V(x)	(((x) & 0xfffff) | (((x) & 0x0f000000) >> 4) | 0xf8000000)
-#define MMIO_P2V(x)	((void __iomem *)__MMIO_P2V(x))
-
 #define AMBA_DEVICE(name,busid,base,plat)	\
 struct amba_device name##_device = {		\
 	.dev		= {			\

@@ -17,3 +14,11 @@ struct amba_device name##_device = {		\
 	.irq		= IRQ_##base,		\
 	/* .dma		= DMA_##base,*/		\
 }
+
+/* 2MB large area for motherboard's peripherals static mapping */
+#define V2M_PERIPH 0xf8000000
+#define V2M_PERIPH_P2V(offset) ((void __iomem *)(V2M_PERIPH | (offset)))
+
+/* Tile's peripherals static mappings should start here */
+#define V2T_PERIPH 0xf8200000
+#define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))

arch/arm/mach-vexpress/ct-ca9x4.c +12 -40

index 2b1e836..bfd3919 100644
@@ -30,57 +30,26 @@
 
 #include <plat/clcd.h>
 
-#define V2M_PA_CS7	0x10000000
-
 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
 	{
-		.virtual	= __MMIO_P2V(CT_CA9X4_MPIC),
-		.pfn		= __phys_to_pfn(CT_CA9X4_MPIC),
-		.length		= SZ_16K,
-		.type		= MT_DEVICE,
-	}, {
-		.virtual	= __MMIO_P2V(CT_CA9X4_SP804_TIMER),
-		.pfn		= __phys_to_pfn(CT_CA9X4_SP804_TIMER),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
-	}, {
-		.virtual	= __MMIO_P2V(CT_CA9X4_L2CC),
-		.pfn		= __phys_to_pfn(CT_CA9X4_L2CC),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE,
+		.virtual        = V2T_PERIPH,
+		.pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
+		.length         = SZ_8K,
+		.type           = MT_DEVICE,
 	},
 };
 
 static void __init ct_ca9x4_map_io(void)
 {
-#ifdef CONFIG_LOCAL_TIMERS
-	twd_base = MMIO_P2V(A9_MPCORE_TWD);
-#endif
 	iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
 
 static void __init ct_ca9x4_init_irq(void)
 {
-	gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
-		 MMIO_P2V(A9_MPCORE_GIC_CPU));
-}
-
-#if 0
-static void __init ct_ca9x4_timer_init(void)
-{
-	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
-	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
-
-	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
-	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
-		"ct-timer0");
+	gic_init(0, 29, V2T_PERIPH_P2V(A9_MPCORE_GIC_DIST),
+		 V2T_PERIPH_P2V(A9_MPCORE_GIC_CPU));
 }
 
-static struct sys_timer ct_ca9x4_timer = {
-	.init	= ct_ca9x4_timer_init,
-};
-#endif
-
 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 {
 	v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);

@@ -193,6 +162,9 @@ static struct platform_device pmu_device = {
 
 static void __init ct_ca9x4_init_early(void)
 {
+#ifdef CONFIG_LOCAL_TIMERS
+	twd_base = V2T_PERIPH_P2V(A9_MPCORE_TWD);
+#endif
 	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 }
 

@@ -201,7 +173,7 @@ static void __init ct_ca9x4_init(void)
 	int i;
 
 #ifdef CONFIG_CACHE_L2X0
-	void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
+	void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
 
 	/* set RAM latencies to 1 cycle for this core tile. */
 	writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);

@@ -219,7 +191,7 @@ static void __init ct_ca9x4_init(void)
 #ifdef CONFIG_SMP
 static void ct_ca9x4_init_cpu_map(void)
 {
-	int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU));
+	int i, ncores = scu_get_core_count(V2T_PERIPH_P2V(A9_MPCORE_SCU));
 
 	if (ncores > nr_cpu_ids) {
 		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",

@@ -235,7 +207,7 @@ static void ct_ca9x4_init_cpu_map(void)
 
 static void ct_ca9x4_smp_enable(unsigned int max_cpus)
 {
-	scu_enable(MMIO_P2V(A9_MPCORE_SCU));
+	scu_enable(V2T_PERIPH_P2V(A9_MPCORE_SCU));
 }
 #endif
 

arch/arm/mach-vexpress/include/mach/ct-ca9x4.h +5 -8

index a34d3d4..8f962fb 100644
@@ -22,14 +22,11 @@
 #define CT_CA9X4_SYSWDT		(0x1e007000)
 #define CT_CA9X4_L2CC		(0x1e00a000)
 
-#define CT_CA9X4_TIMER0		(CT_CA9X4_SP804_TIMER + 0x000)
-#define CT_CA9X4_TIMER1		(CT_CA9X4_SP804_TIMER + 0x020)
-
-#define A9_MPCORE_SCU		(CT_CA9X4_MPIC + 0x0000)
-#define A9_MPCORE_GIC_CPU	(CT_CA9X4_MPIC + 0x0100)
-#define A9_MPCORE_GIT		(CT_CA9X4_MPIC + 0x0200)
-#define A9_MPCORE_TWD		(CT_CA9X4_MPIC + 0x0600)
-#define A9_MPCORE_GIC_DIST	(CT_CA9X4_MPIC + 0x1000)
+#define A9_MPCORE_SCU		0x0000
+#define A9_MPCORE_GIC_CPU	0x0100
+#define A9_MPCORE_GIT		0x0200
+#define A9_MPCORE_TWD		0x0600
+#define A9_MPCORE_GIC_DIST	0x1000
 
 /*
  * Interrupts.  Those in {} are for AMBA devices

arch/arm/mach-vexpress/include/mach/motherboard.h +25 -27

index 0a3a375..b4c498c 100644
@@ -39,33 +39,30 @@
 #define V2M_CF			(V2M_PA_CS7 + 0x0001a000)
 #define V2M_CLCD		(V2M_PA_CS7 + 0x0001f000)
 
-#define V2M_SYS_ID		(V2M_SYSREGS + 0x000)
-#define V2M_SYS_SW		(V2M_SYSREGS + 0x004)
-#define V2M_SYS_LED		(V2M_SYSREGS + 0x008)
-#define V2M_SYS_100HZ		(V2M_SYSREGS + 0x024)
-#define V2M_SYS_FLAGS		(V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSSET	(V2M_SYSREGS + 0x030)
-#define V2M_SYS_FLAGSCLR	(V2M_SYSREGS + 0x034)
-#define V2M_SYS_NVFLAGS		(V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSSET	(V2M_SYSREGS + 0x038)
-#define V2M_SYS_NVFLAGSCLR	(V2M_SYSREGS + 0x03c)
-#define V2M_SYS_MCI		(V2M_SYSREGS + 0x048)
-#define V2M_SYS_FLASH		(V2M_SYSREGS + 0x03c)
-#define V2M_SYS_CFGSW		(V2M_SYSREGS + 0x058)
-#define V2M_SYS_24MHZ		(V2M_SYSREGS + 0x05c)
-#define V2M_SYS_MISC		(V2M_SYSREGS + 0x060)
-#define V2M_SYS_DMA		(V2M_SYSREGS + 0x064)
-#define V2M_SYS_PROCID0		(V2M_SYSREGS + 0x084)
-#define V2M_SYS_PROCID1		(V2M_SYSREGS + 0x088)
-#define V2M_SYS_CFGDATA		(V2M_SYSREGS + 0x0a0)
-#define V2M_SYS_CFGCTRL		(V2M_SYSREGS + 0x0a4)
-#define V2M_SYS_CFGSTAT		(V2M_SYSREGS + 0x0a8)
-
-#define V2M_TIMER0		(V2M_TIMER01 + 0x000)
-#define V2M_TIMER1		(V2M_TIMER01 + 0x020)
-
-#define V2M_TIMER2		(V2M_TIMER23 + 0x000)
-#define V2M_TIMER3		(V2M_TIMER23 + 0x020)
+/*
+ * Offsets from SYSREGS base
+ */
+#define V2M_SYS_ID		0x000
+#define V2M_SYS_SW		0x004
+#define V2M_SYS_LED		0x008
+#define V2M_SYS_100HZ		0x024
+#define V2M_SYS_FLAGS		0x030
+#define V2M_SYS_FLAGSSET	0x030
+#define V2M_SYS_FLAGSCLR	0x034
+#define V2M_SYS_NVFLAGS		0x038
+#define V2M_SYS_NVFLAGSSET	0x038
+#define V2M_SYS_NVFLAGSCLR	0x03c
+#define V2M_SYS_MCI		0x048
+#define V2M_SYS_FLASH		0x03c
+#define V2M_SYS_CFGSW		0x058
+#define V2M_SYS_24MHZ		0x05c
+#define V2M_SYS_MISC		0x060
+#define V2M_SYS_DMA		0x064
+#define V2M_SYS_PROCID0		0x084
+#define V2M_SYS_PROCID1		0x088
+#define V2M_SYS_CFGDATA		0x0a0
+#define V2M_SYS_CFGCTRL		0x0a4
+#define V2M_SYS_CFGSTAT		0x0a8
 
 
 /*

@@ -117,6 +114,7 @@
 
 int v2m_cfg_write(u32 devfn, u32 data);
 int v2m_cfg_read(u32 devfn, u32 *data);
+void v2m_flags_set(u32 data);
 
 /*
  * Core tile IDs

arch/arm/mach-vexpress/platsmp.c +0 -0

index 2b5f7ac..e8be99d 100644

arch/arm/mach-vexpress/platsmp.c +0 -0

 }

arch/arm/mach-vexpress/v2m.c +48 -28

index 1fafc32..ee52b35 100644
@@ -39,29 +39,41 @@
 
 static struct map_desc v2m_io_desc[] __initdata = {
 	{
-		.virtual	= __MMIO_P2V(V2M_PA_CS7),
+		.virtual	= V2M_PERIPH,
 		.pfn		= __phys_to_pfn(V2M_PA_CS7),
 		.length		= SZ_128K,
 		.type		= MT_DEVICE,
 	},
 };
 
+static void __iomem *v2m_sysreg_base;
+
 static void __init v2m_timer_init(void)
 {
-	u32 scctrl;
-
-	/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
-	scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
-	scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
-	scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
-	writel(scctrl, MMIO_P2V(V2M_SYSCTL + SCCTRL));
-
-	writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
-	writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
-
-	sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
-	sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
-		"v2m-timer0");
+	void __iomem *sysctl_base;
+	void __iomem *timer01_base;
+
+	sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
+	WARN_ON(!sysctl_base);
+	if (sysctl_base) {
+		/* Select 1MHz TIMCLK as the reference clock for SP804 timers */
+		u32 scctrl = readl(sysctl_base + SCCTRL);
+		scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;
+		scctrl |= SCCTRL_TIMEREN1SEL_TIMCLK;
+		writel(scctrl, sysctl_base + SCCTRL);
+	}
+
+	timer01_base = ioremap(V2M_TIMER01, SZ_4K);
+	WARN_ON(!timer01_base);
+	if (timer01_base) {
+		writel(0, timer01_base + TIMER_1_BASE + TIMER_CTRL);
+		writel(0, timer01_base + TIMER_2_BASE + TIMER_CTRL);
+
+		sp804_clocksource_init(timer01_base + TIMER_2_BASE,
+				"v2m-timer1");
+		sp804_clockevents_init(timer01_base + TIMER_1_BASE,
+				IRQ_V2M_TIMER0, "v2m-timer0");
+	}
 }
 
 static struct sys_timer v2m_timer = {

@@ -81,14 +93,14 @@ int v2m_cfg_write(u32 devfn, u32 data)
 	devfn |= SYS_CFG_START | SYS_CFG_WRITE;
 
 	spin_lock(&v2m_cfg_lock);
-	val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
-	writel(val & ~SYS_CFG_COMPLETE, MMIO_P2V(V2M_SYS_CFGSTAT));
+	val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
+	writel(val & ~SYS_CFG_COMPLETE, v2m_sysreg_base + V2M_SYS_CFGSTAT);
 
-	writel(data, MMIO_P2V(V2M_SYS_CFGDATA));
-	writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+	writel(data, v2m_sysreg_base +  V2M_SYS_CFGDATA);
+	writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
 
 	do {
-		val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+		val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
 	} while (val == 0);
 	spin_unlock(&v2m_cfg_lock);
 

@@ -102,22 +114,28 @@ int v2m_cfg_read(u32 devfn, u32 *data)
 	devfn |= SYS_CFG_START;
 
 	spin_lock(&v2m_cfg_lock);
-	writel(0, MMIO_P2V(V2M_SYS_CFGSTAT));
-	writel(devfn, MMIO_P2V(V2M_SYS_CFGCTRL));
+	writel(0, v2m_sysreg_base + V2M_SYS_CFGSTAT);
+	writel(devfn, v2m_sysreg_base + V2M_SYS_CFGCTRL);
 
 	mb();
 
 	do {
 		cpu_relax();
-		val = readl(MMIO_P2V(V2M_SYS_CFGSTAT));
+		val = readl(v2m_sysreg_base + V2M_SYS_CFGSTAT);
 	} while (val == 0);
 
-	*data = readl(MMIO_P2V(V2M_SYS_CFGDATA));
+	*data = readl(v2m_sysreg_base + V2M_SYS_CFGDATA);
 	spin_unlock(&v2m_cfg_lock);
 
 	return !!(val & SYS_CFG_ERR);
 }
 
+void __init v2m_flags_set(u32 data)
+{
+	writel(~0, v2m_sysreg_base + V2M_SYS_FLAGSCLR);
+	writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
+}
+
 
 static struct resource v2m_pcie_i2c_resource = {
 	.start	= V2M_SERIAL_BUS_PCI,

@@ -203,7 +221,7 @@ static struct platform_device v2m_usb_device = {
 
 static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
 {
-	writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
+	writel(on != 0, v2m_sysreg_base + V2M_SYS_FLASH);
 }
 
 static struct physmap_flash_data v2m_flash_data = {

@@ -257,7 +275,7 @@ static struct platform_device v2m_cf_device = {
 
 static unsigned int v2m_mmci_status(struct device *dev)
 {
-	return readl(MMIO_P2V(V2M_SYS_MCI)) & (1 << 0);
+	return readl(v2m_sysreg_base + V2M_SYS_MCI) & (1 << 0);
 }
 
 static struct mmci_platform_data v2m_mmci_data = {

@@ -370,7 +388,7 @@ static void __init v2m_init_early(void)
 {
 	ct_desc->init_early();
 	clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
-	versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
 static void v2m_power_off(void)

@@ -399,7 +417,8 @@ static void __init v2m_populate_ct_desc(void)
 	u32 current_tile_id;
 
 	ct_desc = NULL;
-	current_tile_id = readl(MMIO_P2V(V2M_SYS_PROCID0)) & V2M_CT_ID_MASK;
+	current_tile_id = readl(v2m_sysreg_base + V2M_SYS_PROCID0)
+				& V2M_CT_ID_MASK;
 
 	for (i = 0; i < ARRAY_SIZE(ct_descs) && !ct_desc; ++i)
 		if (ct_descs[i]->id == current_tile_id)

@@ -413,6 +432,7 @@ static void __init v2m_populate_ct_desc(void)
 static void __init v2m_map_io(void)
 {
 	iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
+	v2m_sysreg_base = V2M_PERIPH_P2V(V2M_SYSREGS);
 	v2m_populate_ct_desc();
 	ct_desc->map_io();
 }

Signature · 8 lines

1.6.3.3



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Try this (untested):

arch/arm/plat-versatile/headsmp.S +1 -0

index d397a1f..0be2efc 100644
@@ -28,6 +28,7 @@ ENTRY(versatile_secondary_startup)
 pen:   ldr     r7, [r6]
        cmp     r7, r0
        bne     pen
+ENDPROC(versatile_secondary_startup)
 
        /*
         * we've been released from the holding pen: secondary_stack

arch/arm/mach-vexpress/platsmp.c +0 -2

index 2b5f7ac..124ffb1 100644
@@ -13,8 +13,6 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/unified.h>
-
 #include <mach/motherboard.h>
 #define V2M_PA_CS7 0x10000000
 

arch/arm/plat-versatile/headsmp.S ENTRY(versatile_secondary_startup) · line 31

Quoted 9 lines · Dave Martin

arch/arm/plat-versatile/headsmp.S +1 -0

index d397a1f..0be2efc 100644
@@ -28,6 +28,7 @@ ENTRY(versatile_secondary_startup)
 pen:	ldr	r7, [r6]
 	cmp	r7, r0
 	bne	pen
+ENDPROC(versatile_secondary_startup)

This is wrong. You're telling the assembler that this function ends here. It doesn't, it continues on. Put the ENDPROC at the end of the function.

arch/arm/mach-vexpress/v2m.c +0 -0

index ee52b35..fd7ee1f 100644

This patch provides hooks for DT-based tile machine implementations and adds Device Tree description for the motherboard.

Signed-off-by Pawel Moll <[email protected]>

---
 Documentation/devicetree/bindings/arm/vexpress    |  101 +++++++++++
 arch/arm/boot/dts/vexpress-v2m.dtsi               |  191 +++++++++++++++++++++
 arch/arm/mach-vexpress/Kconfig                    |    6 +
 arch/arm/mach-vexpress/core.h                     |   10 +
 arch/arm/mach-vexpress/include/mach/motherboard.h |    6 +
 arch/arm/mach-vexpress/v2m.c                      |  141 ++++++++++++++-
 6 files changed, 447 insertions(+), 8 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vexpress
 create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi

Documentation/devicetree/bindings/arm/vexpress new file +0 -0

new file mode 100644
index 0000000..4b2c3bf

Documentation/devicetree/bindings/arm/vexpress new file +6 -0

+
+Optional properties in the root node:
+- tile model name (use the same names as in the tile's Technical
+  Reference Manuals, eg. "V2P-CA5s")
+	model = "<model>";
+- tile's HBI number (unique ARM's board model ID, visible on the

Documentation/devicetree/bindings/arm/vexpress new file +36 -0

+
+The tile description must define "ranges", "interrupt-map-mask" and
+"interrupt-map" properties to translate the motherboard's address
+and interrupt space into one used by the tile's processor.
+
+Abbreviated example:
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "V2P-CA5s";
+	arm,hbi = <0x225>;
+	compatible = "arm,vexpress-v2p-ca5s";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &mb_serial0;
+		timer = &mb_timer01;
+	};
+
+	gic: interrupt-controller at 2c001000 {
+		compatible = "arm,cortex-a9-gic";
+	};
+
+	motherboard {
+		/* CS0 is visible at 0x08000000 */
+		ranges = <0 0 0x08000000 0x04000000>;
+		interrupt-map-mask = <0 0 63>;
+		/* Active high IRQ 0 is connected to GIC's SPI0 */
+		interrupt-map = <0 0  0 &gic 0  0 4>;
+	};
+}
+
+/include/ "vexpress-v2m-rs1.dtsi"

arch/arm/boot/dts/vexpress-v2m.dtsi new file +191 -0

new file mode 100644
index 0000000..364e44c
@@ -0,0 +1,191 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * Motherboard Express uATX
+ * V2M-P1
+ *
+ * HBI-0190D
+ *
+ * Original memory map ("Legacy memory map" in the board's
+ * Technical Reference Manual)
+ *
+ * WARNING! The hardware described in this file is independent from the
+ * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
+ * correspondence between the two configurations.
+ *
+ * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
+ * CHANGES TO vexpress-v2m-rs1.dtsi!
+ */
+
+/ {
+	motherboard {
+		compatible = "simple-bus";
+		#address-cells = <2>; /* SMB chipselect number and offset */
+		#size-cells = <1>;
+		#interrupt-cells = <1>;
+
+		flash at 0,00000000 {
+			compatible = "arm,vexpress-flash", "cfi-flash";
+			reg = <0 0x00000000 0x04000000>,
+			      <1 0x00000000 0x04000000>;
+			bank-width = <4>;
+		};
+
+		psram at 2,00000000 {
+			compatible = "mtd-ram";
+			reg = <2 0x00000000 0x02000000>;
+			bank-width = <4>;
+		};
+
+		ethernet at 3,02000000 {
+			compatible = "smsc,lan9118", "smsc,lan9115";
+			reg = <3 0x02000000 0x10000>;
+			interrupts = <15>;
+			phy-mode = "mii";
+			reg-io-width = <4>;
+			smsc,irq-active-high;
+			smsc,irq-push-pull;
+		};
+
+		usb at 3,03000000 {
+			compatible = "nxp,usb-isp1761";
+			reg = <3 0x03000000 0x20000>;
+			interrupts = <16>;
+			port1-otg;
+		};
+
+		iofpga at 7,00000000 {
+			compatible = "arm,amba-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 7 0 0x20000>;
+
+			sysreg at 00000 {
+				compatible = "arm,vexpress-sysreg";
+				reg = <0x00000 0x1000>;
+			};
+
+			sysctl at 01000 {
+				compatible = "arm,sp810", "arm,primecell";
+				reg = <0x01000 0x1000>;
+			};
+
+			/* PCI-E I2C bus */
+			mb_i2c_pcie: i2c at 02000 {
+				compatible = "arm,versatile-i2c";
+				reg = <0x02000 0x1000>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pcie-switch at 60 {
+					compatible = "idt,89hpes32h8";
+					reg = <0x60>;
+				};
+			};
+
+			aaci at 04000 {
+				compatible = "arm,pl041", "arm,primecell";
+				reg = <0x04000 0x1000>;
+				interrupts = <11>;
+			};
+
+			mmci at 05000 {
+				compatible = "arm,pl180", "arm,primecell";
+				reg = <0x05000 0x1000>;
+				interrupts = <9 10>;
+			};
+
+			kmi at 06000 {
+				compatible = "arm,pl050", "arm,primecell";
+				reg = <0x06000 0x1000>;
+				interrupts = <12>;
+			};
+
+			kmi at 07000 {
+				compatible = "arm,pl050", "arm,primecell";
+				reg = <0x07000 0x1000>;
+				interrupts = <13>;
+			};
+
+			mb_serial0: uart at 09000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x09000 0x1000>;
+				interrupts = <5>;
+			};
+
+			mb_serial1: uart at 0a000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x0a000 0x1000>;
+				interrupts = <6>;
+			};
+
+			mb_serial2: uart at 0b000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x0b000 0x1000>;
+				interrupts = <7>;
+			};
+
+			mb_serial3: uart at 0c000 {
+				compatible = "arm,pl011", "arm,primecell";
+				reg = <0x0c000 0x1000>;
+				interrupts = <8>;
+			};
+
+			wdt at 0f000 {
+				compatible = "arm,sp805", "arm,primecell";
+				reg = <0x0f000 0x1000>;
+				interrupts = <0>;
+			};
+
+			mb_timer01: timer at 11000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0x11000 0x1000>;
+				interrupts = <2>;
+			};
+
+			mb_timer23: timer at 12000 {
+				compatible = "arm,sp804", "arm,primecell";
+				reg = <0x12000 0x1000>;
+			};
+
+			/* DVI I2C bus */
+			mb_i2c_dvi: i2c at 16000 {
+				compatible = "arm,versatile-i2c";
+				reg = <0x16000 0x1000>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dvi-transmitter at 39 {
+					compatible = "sil,sii9022-tpi", "sil,sii9022";
+					reg = <0x39>;
+				};
+
+				dvi-transmitter at 60 {
+					compatible = "sil,sii9022-cpi", "sil,sii9022";
+					reg = <0x60>;
+				};
+			};
+
+			rtc at 17000 {
+				compatible = "arm,pl031", "arm,primecell";
+				reg = <0x17000 0x1000>;
+				interrupts = <4>;
+			};
+
+			compact-flash at 1a000 {
+				compatible = "ata-generic";
+				reg = <0x1a000 0x100
+				       0x1a100 0xf00>;
+				reg-shift = <2>;
+			};
+
+			clcd at 1f000 {
+				compatible = "arm,pl111", "arm,primecell";
+				reg = <0x1f000 0x1000>;
+				interrupts = <14>;
+			};
+		};
+	};
+};

arch/arm/mach-vexpress/Kconfig +6 -0

index 9311484..6a6fa22 100644
@@ -9,4 +9,10 @@ config ARCH_VEXPRESS_CA9X4
 	select ARM_ERRATA_751472
 	select ARM_ERRATA_753970
 
+config ARCH_VEXPRESS_DT
+	bool
+	select OF
+	help
+	  VE platform *requiring* Flattened Device Tree to boot.
+
 endmenu

arch/arm/mach-vexpress/core.h +10 -0

index d3dd491..21cc48b 100644
@@ -22,3 +22,13 @@ struct amba_device name##_device = {		\
 /* Tile's peripherals static mappings should start here */
 #define V2T_PERIPH 0xf8200000
 #define V2T_PERIPH_P2V(offset) ((void __iomem *)(V2T_PERIPH | (offset)))
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+extern struct sys_timer v2m_timer;
+
+void __init v2m_dt_map_io(void);
+void __init v2m_dt_init_early(void);
+struct of_dev_auxdata * __init v2m_dt_get_auxdata(void);
+
+#endif

arch/arm/mach-vexpress/include/mach/motherboard.h +6 -0

index b4c498c..31a9289 100644
@@ -117,6 +117,12 @@ int v2m_cfg_read(u32 devfn, u32 *data);
 void v2m_flags_set(u32 data);
 
 /*
+ * Miscellaneous
+ */
+#define SYS_MISC_MASTERSITE	(1 << 14)
+#define SYS_PROCIDx_HBI_MASK	0xfff
+
+/*
  * Core tile IDs
  */
 #define V2M_CT_ID_CA9		0x0c000191

arch/arm/mach-vexpress/v2m.c +22 -2

index ee52b35..fd7ee1f 100644
@@ -6,6 +6,10 @@
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
 #include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
 #include <linux/smsc911x.h>

@@ -17,6 +21,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
+#include <asm/system.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>

@@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
 
 static void __init v2m_timer_init(void)
 {
-	void __iomem *sysctl_base;
-	void __iomem *timer01_base;
+	void __iomem *sysctl_base = NULL;
+	void __iomem *timer01_base = NULL;
+	unsigned int timer01_irq = NO_IRQ;
+
+	if (of_have_populated_dt()) {
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+		int err;
+		const char *path;
+		struct device_node *node;
+
+		node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+		if (node)
+			sysctl_base = of_iomap(node, 0);
+
+		err = of_property_read_string(of_aliases, "timer", &path);
+		if (!err)
+			node = of_find_node_by_path(path);

arch/arm/mach-vexpress/v2m.c +4 -2

+	if (timer01_base && timer01_irq != NO_IRQ) {
 		writel(0, timer01_base + TIMER_1_BASE + TIMER_CTRL);
 		writel(0, timer01_base + TIMER_2_BASE + TIMER_CTRL);
 
 		sp804_clocksource_init(timer01_base + TIMER_2_BASE,
 				"v2m-timer1");
 		sp804_clockevents_init(timer01_base + TIMER_1_BASE,
-				IRQ_V2M_TIMER0, "v2m-timer0");
+				timer01_irq, "v2m-timer0");
 	}
 }
 
-static struct sys_timer v2m_timer = {
+/* Used also by DT-powered core tiles */
+struct sys_timer v2m_timer = {
 	.init	= v2m_timer_init,
 };
 

arch/arm/mach-vexpress/v2m.c +96 -0

+
+
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+
+void __init v2m_dt_map_io(void)
+{
+		iotable_init(v2m_rs1_io_desc, ARRAY_SIZE(v2m_rs1_io_desc));
+}
+
+static struct clk_lookup v2m_dt_lookups[] = {
+	{	/* AMBA bus clock */
+		.con_id		= "apb_pclk",
+		.clk		= &dummy_apb_pclk,
+	}, {	/* SP804 timers */
+		.dev_id		= "sp804",
+		.con_id		= "v2m-timer0",
+		.clk		= &v2m_sp804_clk,
+	}, {	/* SP804 timers */
+		.dev_id		= "sp804",
+		.con_id		= "v2m-timer1",
+		.clk		= &v2m_sp804_clk,
+	}, {	/* PL180 MMCI */
+		.dev_id		= "mb:mmci", /* 10005000.mmci */
+		.clk		= &osc2_clk,
+	}, {	/* PL050 KMI0 */
+		.dev_id		= "10006000.kmi",
+		.clk		= &osc2_clk,
+	}, {	/* PL050 KMI1 */
+		.dev_id		= "10007000.kmi",
+		.clk		= &osc2_clk,
+	}, {	/* PL011 UART0 */
+		.dev_id		= "10009000.uart",
+		.clk		= &osc2_clk,
+	}, {	/* PL011 UART1 */
+		.dev_id		= "1000a000.uart",
+		.clk		= &osc2_clk,
+	}, {	/* PL011 UART2 */
+		.dev_id		= "1000b000.uart",
+		.clk		= &osc2_clk,
+	}, {	/* PL011 UART3 */
+		.dev_id		= "1000c000.uart",
+		.clk		= &osc2_clk,
+	}, {	/* SP805 WDT */
+		.dev_id		= "1000f000.wdt",
+		.clk		= &v2m_ref_clk,
+	}, {	/* PL111 CLCD */
+		.dev_id		= "1001f000.clcd",
+		.clk		= &osc1_clk,
+	},
+};
+
+void __init v2m_dt_init_early(void)
+{
+	struct device_node *node;
+	const __be32 *reg;
+	u32 dt_hbi;
+
+	node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg");
+	reg = of_get_property(node, "reg", NULL);
+	if (WARN_ON(!reg))
+		return;
+
+	v2m_sysreg_base = V2M_PERIPH_P2V(be32_to_cpup(reg));
+
+	/* Confirm board type against DT property, if available */
+	if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
+		u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+		u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+				V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
+		u32 hbi = id & SYS_PROCIDx_HBI_MASK;
+
+		if (WARN_ON(dt_hbi != hbi))
+			pr_warning("vexpress: DT HBI (%x) is not matching "
+					"hardware (%x)!\n", dt_hbi, hbi);
+	}
+
+	clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
+	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
+
+	pm_power_off = v2m_power_off;
+	arm_pm_restart = v2m_restart;
+}
+
+static struct of_dev_auxdata v2m_dt_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,vexpress-flash", V2M_NOR0, "physmap-flash",
+			&v2m_flash_data),
+	OF_DEV_AUXDATA("arm,primecell", V2M_MMCI, "mb:mmci", &v2m_mmci_data),
+	{}
+};
+
+struct of_dev_auxdata * __init v2m_dt_get_auxdata(void)
+{
+	return v2m_dt_auxdata_lookup;
+}
+
+#endif

Signature · 8 lines

1.6.3.3



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[Since this text is now stable enough to be proofread, I'll list minor pedantic nits along with the other comments -- they aren't vital to the meaning though, and the documentation still "works" if they aren't acted on.]

Quoted 23 lines

arch/arm/mach-vexpress/v2m.c +17 -2

@@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
 
 static void __init v2m_timer_init(void)
 {
-     void __iomem *sysctl_base;
-     void __iomem *timer01_base;
+     void __iomem *sysctl_base = NULL;
+     void __iomem *timer01_base = NULL;
+     unsigned int timer01_irq = NO_IRQ;
+
+     if (of_have_populated_dt()) {
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+             int err;
+             const char *path;
+             struct device_node *node;
+
+             node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+             if (node)
+                     sysctl_base = of_iomap(node, 0);
+
+             err = of_property_read_string(of_aliases, "timer", &path);
+             if (!err)
+                     node = of_find_node_by_path(path);

arch/arm/mach-vexpress/v2m.c static void __iomem *v2m_sysreg_base; · line 84

Quoted 10 lines

arch/arm/mach-vexpress/v2m.c +10 -0

+             if (node) {
+                     timer01_base = of_iomap(node, 0);
+                     timer01_irq = irq_of_parse_and_map(node, 0);
+             }
+#endif
+     } else {
+             sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
+             timer01_base = ioremap(V2M_TIMER01, SZ_4K);
+             timer01_irq = IRQ_V2M_TIMER0;
+     }

Do we even have of_have_populated_dt() in a non-DT kernel?

Maybe change this to

#if defined(CONFIG_ARCH_VEXPRESS_DT)
        if (of_have_populated_dt()) {
                /* ... */
        } else
#endif
        /* follow on from previous else */
        {
                /* ... */
        }

...or if that feels a little unclear, maybe do this:

#if defined(CONFIG_ARCH_VEXPRESS_DT)
        if (of_have_populated_dt()) {
                /* ... */
        } else {
#else
        {
#endif
                /* ... */
        }

arch/arm/mach-vexpress/v2m.c static void __init v2m_timer_init(void) · line 95

Quoted 8 lines

arch/arm/mach-vexpress/v2m.c +1 -3

@@ -63,20 +92,20 @@ static void __init v2m_timer_init(void)
              writel(scctrl, sysctl_base + SCCTRL);
      }
 
-     timer01_base = ioremap(V2M_TIMER01, SZ_4K);
-     WARN_ON(!timer01_base);
-     if (timer01_base) {
+     WARN_ON(!timer01_base || timer01_irq != NO_IRQ);

Is that supposed to be !timer01_base || timer01_irq == NO_IRQ ?

If so, is might be better to write

WARN_ON(!(expr));

if (expr) {
        ...

so that the conditions are clear inverses.

arch/arm/mach-vexpress/v2m.c MACHINE_START(VEXPRESS, "ARM-Versatile Express") · line 501

Quoted 4 lines

arch/arm/mach-vexpress/v2m.c +0 -0

@@ -470,3 +499,99 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
      .timer          = &v2m_timer,
      .init_machine   = v2m_init,
 MACHINE_END

It would be useful to have a comment somewhere indicating that the DT_MACHINE_START() entries live in the corresponding ct-*.c files for DT-enabled coretiles.

Not essential, though ... most people do know how to use grep.

Quoted 4 lines · Dave Martin

[Since this text is now stable enough to be proofread, I'll list minor pedantic nits along with the other comments -- they aren't vital to the meaning though, and the documentation still "works" if they aren't acted on.]

[snip]

Most appreciated! I'll "process" all your suggestions, thanks!

Quoted 50 lines

Quoted 23 lines

arch/arm/mach-vexpress/v2m.c +17 -2

@@ -50,10 +55,34 @@ static void __iomem *v2m_sysreg_base;
 
 static void __init v2m_timer_init(void)
 {
-     void __iomem *sysctl_base;
-     void __iomem *timer01_base;
+     void __iomem *sysctl_base = NULL;
+     void __iomem *timer01_base = NULL;
+     unsigned int timer01_irq = NO_IRQ;
+
+     if (of_have_populated_dt()) {
+#if defined(CONFIG_ARCH_VEXPRESS_DT)
+             int err;
+             const char *path;
+             struct device_node *node;
+
+             node = of_find_compatible_node(NULL, NULL, "arm,sp810");
+             if (node)
+                     sysctl_base = of_iomap(node, 0);
+
+             err = of_property_read_string(of_aliases, "timer", &path);
+             if (!err)
+                     node = of_find_node_by_path(path);

arch/arm/mach-vexpress/v2m.c static void __iomem *v2m_sysreg_base; · line 84

Quoted 10 lines

arch/arm/mach-vexpress/v2m.c +10 -0

+             if (node) {
+                     timer01_base = of_iomap(node, 0);
+                     timer01_irq = irq_of_parse_and_map(node, 0);
+             }
+#endif
+     } else {
+             sysctl_base = ioremap(V2M_SYSCTL, SZ_4K);
+             timer01_base = ioremap(V2M_TIMER01, SZ_4K);
+             timer01_irq = IRQ_V2M_TIMER0;
+     }

Do we even have of_have_populated_dt() in a non-DT kernel?

Maybe change this to

#if defined(CONFIG_ARCH_VEXPRESS_DT)
        if (of_have_populated_dt()) {
                /* ... */
        } else
#endif
        /* follow on from previous else */
        {
                /* ... */
        }

...or if that feels a little unclear, maybe do this:

Quoted 9 lines

#if defined(CONFIG_ARCH_VEXPRESS_DT)
        if (of_have_populated_dt()) {
                /* ... */
        } else {
#else
        {
#endif
                /* ... */
        }

of_have_populated_dt() is safe, see "include/linux/of.h":

#ifdef CONFIG_OF
static inline bool of_have_populated_dt(void)

{       
        return allnodes != NULL;
}       
#else /* CONFIG_OF */
static inline bool of_have_populated_dt(void)
{       
        return false;
}       

#endif /* CONFIG_OF */

Quoted 10 lines

arch/arm/mach-vexpress/v2m.c static void __init v2m_timer_init(void) · line 95

Quoted 8 lines

arch/arm/mach-vexpress/v2m.c +1 -3

@@ -63,20 +92,20 @@ static void __init v2m_timer_init(void)
              writel(scctrl, sysctl_base + SCCTRL);
      }
 
-     timer01_base = ioremap(V2M_TIMER01, SZ_4K);
-     WARN_ON(!timer01_base);
-     if (timer01_base) {
+     WARN_ON(!timer01_base || timer01_irq != NO_IRQ);

Is that supposed to be !timer01_base || timer01_irq == NO_IRQ ?

Yes, I spotted and fixed this in the mean time.

Quoted 7 lines

If so, is might be better to write

WARN_ON(!(expr));

if (expr) {
        ...

so that the conditions are clear inverses.

Good point, will do.

Quoted 9 lines

arch/arm/mach-vexpress/v2m.c MACHINE_START(VEXPRESS, "ARM-Versatile Express") · line 501

Quoted 4 lines

arch/arm/mach-vexpress/v2m.c +0 -0

@@ -470,3 +499,99 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
      .timer          = &v2m_timer,
      .init_machine   = v2m_init,
 MACHINE_END

It would be useful to have a comment somewhere indicating that the DT_MACHINE_START() entries live in the corresponding ct-*.c files for DT-enabled coretiles.

Quoted 1 line

Not essential, though ... most people do know how to use grep.

Where exactly would you see that comment?

This patch adds Device Trees for ARM Ltd. CoreTile Express A5x2 and CoreTile Express A9x4 used with V2M motherboard and an initial implementation of the DT machine support (this code is separate from the current core tile code).

Signed-off-by Pawel Moll <[email protected]>

---
 arch/arm/boot/dts/vexpress-v2p-ca5s.dts |  132 ++++++++++++++++++++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts  |  146 +++++++++++++++++++++++++++++++
 arch/arm/mach-vexpress/Kconfig          |   21 +++++
 arch/arm/mach-vexpress/Makefile         |    1 +
 arch/arm/mach-vexpress/v2p-ca5s_ca9.c   |  115 ++++++++++++++++++++++++
 5 files changed, 415 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
 create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c

arch/arm/boot/dts/vexpress-v2p-ca5s.dts new file +132 -0

new file mode 100644
index 0000000..84e05cd
@@ -0,0 +1,132 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A5x2
+ * Cortex-A5 MPCore (V2P-CA5s)
+ *
+ * HBI-0225B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "V2P-CA5s";
+	arm,hbi = <0x225>;
+	compatible = "arm,vexpress-v2p-ca5s";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &mb_serial0;
+		serial1 = &mb_serial1;
+		serial2 = &mb_serial2;
+		serial3 = &mb_serial3;
+		i2c0 = &mb_i2c_dvi;
+		i2c1 = &mb_i2c_pcie;
+		timer = &mb_timer01;
+	};
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	hdlcd at 2a110000 {
+		compatible = "arm,hdlcd";
+		reg = <0x2a110000 0x1000>;
+		interrupts = <0 85 4>;
+	};
+
+	memory-controller at 2a150000 {
+		compatible = "arm,pl341", "arm,primecell";
+		reg = <0x2a150000 0x1000>;
+	};
+
+	memory-controller at 2a190000 {
+		compatible = "arm,pl354", "arm,primecell";
+		reg = <0x2a190000 0x1000>;
+		interrupts = <0 86 4>,
+			     <0 87 4>;
+	};
+
+	gic: interrupt-controller at 2c001000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x2c001000 0x1000>,
+		      <0x2c000100 0x100>;
+	};
+
+	L2: cache-controller at 2c0f0000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x2c0f0000 0x1000>;
+		interrupts = <0 84 4>;
+		cache-level = <2>;
+		arm,data-latency = <0>;
+		arm,tag-latency = <0>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <0 68 4>,
+			     <0 69 4>;
+	};
+
+	motherboard {
+		ranges = <0 0 0x08000000 0x04000000>,
+			 <1 0 0x14000000 0x04000000>,
+			 <2 0 0x18000000 0x04000000>,
+			 <3 0 0x1c000000 0x04000000>,
+			 <4 0 0x0c000000 0x04000000>,
+			 <5 0 0x10000000 0x04000000>;
+
+		interrupt-map-mask = <0 0 63>;
+		interrupt-map = <0 0  0 &gic 0  0 4>,
+				<0 0  1 &gic 0  1 4>,
+				<0 0  2 &gic 0  2 4>,
+				<0 0  3 &gic 0  3 4>,
+				<0 0  4 &gic 0  4 4>,
+				<0 0  5 &gic 0  5 4>,
+				<0 0  6 &gic 0  6 4>,
+				<0 0  7 &gic 0  7 4>,
+				<0 0  8 &gic 0  8 4>,
+				<0 0  9 &gic 0  9 4>,
+				<0 0 10 &gic 0 10 4>,
+				<0 0 11 &gic 0 11 4>,
+				<0 0 12 &gic 0 12 4>,
+				<0 0 13 &gic 0 13 4>,
+				<0 0 14 &gic 0 14 4>,
+				<0 0 15 &gic 0 15 4>,
+				<0 0 16 &gic 0 16 4>,
+				<0 0 17 &gic 0 17 4>,
+				<0 0 18 &gic 0 18 4>,
+				<0 0 19 &gic 0 19 4>,
+				<0 0 20 &gic 0 20 4>,
+				<0 0 21 &gic 0 21 4>,
+				<0 0 22 &gic 0 22 4>,
+				<0 0 23 &gic 0 23 4>,
+				<0 0 24 &gic 0 24 4>,
+				<0 0 25 &gic 0 25 4>,
+				<0 0 26 &gic 0 26 4>,
+				<0 0 27 &gic 0 27 4>,
+				<0 0 28 &gic 0 28 4>,
+				<0 0 29 &gic 0 29 4>,
+				<0 0 30 &gic 0 30 4>,
+				<0 0 31 &gic 0 31 4>,
+				<0 0 32 &gic 0 32 4>,
+				<0 0 33 &gic 0 33 4>,
+				<0 0 34 &gic 0 34 4>,
+				<0 0 35 &gic 0 35 4>,
+				<0 0 36 &gic 0 36 4>,
+				<0 0 37 &gic 0 37 4>,
+				<0 0 38 &gic 0 38 4>,
+				<0 0 39 &gic 0 39 4>,
+				<0 0 40 &gic 0 40 4>,
+				<0 0 41 &gic 0 41 4>,
+				<0 0 42 &gic 0 42 4>;
+	};
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"

arch/arm/boot/dts/vexpress-v2p-ca9.dts new file +146 -0

new file mode 100644
index 0000000..ae6b70c
@@ -0,0 +1,146 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A9x4
+ * Cortex-A9 MPCore (V2P-CA9)
+ *
+ * HBI-0191B
+ */
+
+/dts-v1/;
+
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "V2P-CA9";
+	arm,hbi = <0x191>;
+	compatible = "arm,vexpress-v2p-ca9";
+	interrupt-parent = <&gic>;
+
+	aliases {
+		serial0 = &mb_serial0;
+		serial1 = &mb_serial1;
+		serial2 = &mb_serial2;
+		serial3 = &mb_serial3;
+		i2c0 = &mb_i2c_dvi;
+		i2c1 = &mb_i2c_pcie;
+		timer = &mb_timer01;
+	};
+
+	memory at 60000000 {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+
+	clcd at 10020000 {
+		compatible = "arm,pl111", "arm,primecell";
+		reg = <0x10020000 0x1000>;
+		interrupts = <0 44 4>;
+	};
+
+	memory-controller at 100e0000 {
+		compatible = "arm,pl341", "arm,primecell";
+		reg = <0x100e0000 0x1000>;
+	};
+
+	memory-controller at 100e1000 {
+		compatible = "arm,pl354", "arm,primecell";
+		reg = <0x100e1000 0x1000>;
+		interrupts = <0 45 4>,
+			     <0 46 4>;
+	};
+
+	timer at 100e4000 {
+		compatible = "arm,sp804", "arm,primecell";
+		reg = <0x100e4000 0x1000>;
+		interrupts = <0 48 4>,
+			     <0 49 4>;
+	};
+
+	watchdog at 100e5000 {
+		compatible = "arm,sp805", "arm,primecell";
+		reg = <0x100e5000 0x1000>;
+		interrupts = <0 51 4>;
+	};
+
+	gic: interrupt-controller at 1e001000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <3>;
+		#address-cells = <0>;
+		interrupt-controller;
+		reg = <0x1e001000 0x1000>,
+		      <0x1e000100 0x100>;
+	};
+
+	L2: cache-controller at 1e00a000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x1e00a000 0x1000>;
+		interrupts = <0 43 4>;
+		cache-level = <2>;
+		arm,data-latency = <0>;
+		arm,tag-latency = <0>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <0 60 4>,
+			     <0 61 4>,
+			     <0 62 4>,
+			     <0 63 4>;
+	};
+
+	motherboard {
+		ranges = <0 0 0x40000000 0x04000000>,
+			 <1 0 0x44000000 0x04000000>,
+			 <2 0 0x48000000 0x04000000>,
+			 <3 0 0x4c000000 0x04000000>,
+			 <7 0 0x10000000 0x00020000>;
+
+		interrupt-map-mask = <0 0 63>;
+		interrupt-map = <0 0  0 &gic 0  0 4>,
+				<0 0  1 &gic 0  1 4>,
+				<0 0  2 &gic 0  2 4>,
+				<0 0  3 &gic 0  3 4>,
+				<0 0  4 &gic 0  4 4>,
+				<0 0  5 &gic 0  5 4>,
+				<0 0  6 &gic 0  6 4>,
+				<0 0  7 &gic 0  7 4>,
+				<0 0  8 &gic 0  8 4>,
+				<0 0  9 &gic 0  9 4>,
+				<0 0 10 &gic 0 10 4>,
+				<0 0 11 &gic 0 11 4>,
+				<0 0 12 &gic 0 12 4>,
+				<0 0 13 &gic 0 13 4>,
+				<0 0 14 &gic 0 14 4>,
+				<0 0 15 &gic 0 15 4>,
+				<0 0 16 &gic 0 16 4>,
+				<0 0 17 &gic 0 17 4>,
+				<0 0 18 &gic 0 18 4>,
+				<0 0 19 &gic 0 19 4>,
+				<0 0 20 &gic 0 20 4>,
+				<0 0 21 &gic 0 21 4>,
+				<0 0 22 &gic 0 22 4>,
+				<0 0 23 &gic 0 23 4>,
+				<0 0 24 &gic 0 24 4>,
+				<0 0 25 &gic 0 25 4>,
+				<0 0 26 &gic 0 26 4>,
+				<0 0 27 &gic 0 27 4>,
+				<0 0 28 &gic 0 28 4>,
+				<0 0 29 &gic 0 29 4>,
+				<0 0 30 &gic 0 30 4>,
+				<0 0 31 &gic 0 31 4>,
+				<0 0 32 &gic 0 32 4>,
+				<0 0 33 &gic 0 33 4>,
+				<0 0 34 &gic 0 34 4>,
+				<0 0 35 &gic 0 35 4>,
+				<0 0 36 &gic 0 36 4>,
+				<0 0 37 &gic 0 37 4>,
+				<0 0 38 &gic 0 38 4>,
+				<0 0 39 &gic 0 39 4>,
+				<0 0 40 &gic 0 40 4>,
+				<0 0 41 &gic 0 41 4>,
+				<0 0 42 &gic 0 42 4>;
+	};
+};
+
+/include/ "vexpress-v2m.dtsi"

arch/arm/mach-vexpress/Kconfig +0 -0

index 2180888..0f31125 100644

arch/arm/mach-vexpress/Kconfig config ARCH_VEXPRESS_RS1 · line 29

Quoted 4 lines

arch/arm/mach-vexpress/Kconfig +4 -0

+config ARCH_VEXPRESS_V2P_CA5S_CA9
+	bool "CoreTile Express A5x2 and A9x4 based platform support"
+	select ARCH_VEXPRESS_RS1
+	select ARCH_VEXPRESS_DT

Shouldn't we depend on CPU_V7, ARM_GIC and CACHE_PL310 here? I get a lot of moaning from Kconfig about unmet dependencies. I think the coretiles do have a CPU etc. on them...

arch/arm/mach-vexpress/Kconfig config ARCH_VEXPRESS_RS1 · line 31

Quoted 2 lines

arch/arm/mach-vexpress/Kconfig +2 -0

+	select ARM_ERRATA_720789
+	select ARM_ERRATA_751472

The workarounds for these errata both erroneously depend on CONFIG_SMP; however, I don't think that's a bug in these patches -- selecting those options here feels correct.

arch/arm/mach-vexpress/Kconfig config ARCH_VEXPRESS_RS1 · line 32

Quoted 1 line

arch/arm/mach-vexpress/Kconfig +1 -0

+	select ARM_ERRATA_753970

Will has a patch, now in Russell's fixes branch, which renames this to PL310_ERRATA_753970 for compatibility with other people's patches. This erratum workaround depends on CACHE_PL310, but since the PL310 is a property of the CoreTile which must be configured in, that dependency seems reasonable.

Quoted 8 lines · Dave Martin

arch/arm/mach-vexpress/Kconfig config ARCH_VEXPRESS_RS1 · line 29

Quoted 4 lines

arch/arm/mach-vexpress/Kconfig +4 -0

+config ARCH_VEXPRESS_V2P_CA5S_CA9
+	bool "CoreTile Express A5x2 and A9x4 based platform support"
+	select ARCH_VEXPRESS_RS1
+	select ARCH_VEXPRESS_DT

Shouldn't we depend on CPU_V7, ARM_GIC and CACHE_PL310 here? I get a lot of moaning from Kconfig about unmet dependencies. I think the coretiles do have a CPU etc. on them...

CPU_V7 and ARM_GIC - definitely, thanks for spotting that.

CACHE_PL310 - I don't think so, as it's just a special case of CACHE_L2X0, which is optional. The tile works fine with the L2 cache disabled.

Quoted 6 lines

arch/arm/mach-vexpress/Kconfig config ARCH_VEXPRESS_RS1 · line 31

Quoted 2 lines

arch/arm/mach-vexpress/Kconfig +2 -0

+	select ARM_ERRATA_720789
+	select ARM_ERRATA_751472

The workarounds for these errata both erroneously depend on CONFIG_SMP; however, I don't think that's a bug in these patches -- selecting those options here feels correct.

Yes, I've just mirrored what the ARCH_VEXPRESS_CA9X4 selects.

Quoted 7 lines

arch/arm/mach-vexpress/Kconfig config ARCH_VEXPRESS_RS1 · line 32

Quoted 1 line

arch/arm/mach-vexpress/Kconfig +1 -0

+	select ARM_ERRATA_753970

Will has a patch, now in Russell's fixes branch, which renames this to PL310_ERRATA_753970 for compatibility with other people's patches. This erratum workaround depends on CACHE_PL310, but since the PL310 is a property of the CoreTile which must be configured in, that dependency seems reasonable.

As the PL310 is optional I think I'll just do:

        select PL310_ERRATA_753970 if CACHE_PL310

Hello again,

This version of the series (hopefully) addresses all the suggestions made by Dave, Rob and Russell.

The compatible values are specific for the tiles now and the memory map variant is defined as a custom property in the motherboard node.

Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT.

All comments, as always, welcomed!

Pawel

Pawel Moll (4):
ARM: vexpress: Get rid of MMIO_P2V
ARM: vexpress: Add DT support in v2m
ARM: vexpress: Initial RS1 memory map support
ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4

 Documentation/devicetree/bindings/arm/vexpress    |  101 ++++++++
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi           |  192 +++++++++++++++
 arch/arm/boot/dts/vexpress-v2m.dtsi               |  191 +++++++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca5s.dts           |  132 ++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts            |  146 +++++++++++
 arch/arm/include/asm/hardware/arm_timer.h         |    5 +
 arch/arm/mach-vexpress/Kconfig                    |   35 +++
 arch/arm/mach-vexpress/Makefile                   |    1 +
 arch/arm/mach-vexpress/Makefile.boot              |    6 +
 arch/arm/mach-vexpress/core.h                     |   21 ++-
 arch/arm/mach-vexpress/ct-ca9x4.c                 |   52 +---
 arch/arm/mach-vexpress/include/mach/ct-ca9x4.h    |   13 +-
 arch/arm/mach-vexpress/include/mach/debug-macro.S |   37 +++-
 arch/arm/mach-vexpress/include/mach/motherboard.h |   58 +++--
 arch/arm/mach-vexpress/include/mach/uncompress.h  |   13 +-
 arch/arm/mach-vexpress/platsmp.c                  |    4 +-
 arch/arm/mach-vexpress/v2m.c                      |  265 ++++++++++++++++++---

 arch/arm/mach-vexpress/v2p-ca5s_ca9.c             |  115 +++++++++
 18 files changed, 1272 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vexpress
 create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
 create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
 create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c

Quoted 39 lines · Pawel Moll

Hello again,

This version of the series (hopefully) addresses all the suggestions made by Dave, Rob and Russell.

The compatible values are specific for the tiles now and the memory map variant is defined as a custom property in the motherboard node.

Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT.

All comments, as always, welcomed!

Pawel

Pawel Moll (4):
ARM: vexpress: Get rid of MMIO_P2V
ARM: vexpress: Add DT support in v2m
ARM: vexpress: Initial RS1 memory map support
ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4

 Documentation/devicetree/bindings/arm/vexpress    |  101 ++++++++
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi           |  192 +++++++++++++++
 arch/arm/boot/dts/vexpress-v2m.dtsi               |  191 +++++++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca5s.dts           |  132 ++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts            |  146 +++++++++++
 arch/arm/include/asm/hardware/arm_timer.h         |    5 +
 arch/arm/mach-vexpress/Kconfig                    |   35 +++
 arch/arm/mach-vexpress/Makefile                   |    1 +
 arch/arm/mach-vexpress/Makefile.boot              |    6 +
 arch/arm/mach-vexpress/core.h                     |   21 ++-
 arch/arm/mach-vexpress/ct-ca9x4.c                 |   52 +---
 arch/arm/mach-vexpress/include/mach/ct-ca9x4.h    |   13 +-
 arch/arm/mach-vexpress/include/mach/debug-macro.S |   37 +++-
 arch/arm/mach-vexpress/include/mach/motherboard.h |   58 +++--
 arch/arm/mach-vexpress/include/mach/uncompress.h  |   13 +-
 arch/arm/mach-vexpress/platsmp.c                  |    4 +-
 arch/arm/mach-vexpress/v2m.c                      |  265 ++++++++++++++++++---

Quoted 8 lines

 arch/arm/mach-vexpress/v2p-ca5s_ca9.c             |  115 +++++++++
 18 files changed, 1272 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vexpress
 create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
 create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
 create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c

Other than Dave's comments, looks good. For the series:

Acked-by Rob Herring <[email protected]>

There are a number of compatible strings for various peripherals defined without documentation, but you're not really using them so I think it's fine for now. BTW, I believe Dave said he was going to document some of the primecell peripherals. :)

Quoted 39 lines · Pawel Moll

Hello again,

This version of the series (hopefully) addresses all the suggestions made by Dave, Rob and Russell.

The compatible values are specific for the tiles now and the memory map variant is defined as a custom property in the motherboard node.

Tested on V2P-CA9 coretile both with ATAGs and DT and V2P-CA5s with DT.

All comments, as always, welcomed!

Pawel

Pawel Moll (4):
ARM: vexpress: Get rid of MMIO_P2V
ARM: vexpress: Add DT support in v2m
ARM: vexpress: Initial RS1 memory map support
ARM: vexpress: DT-based support for CoreTiles Express A5x2 and A9x4

 Documentation/devicetree/bindings/arm/vexpress    |  101 ++++++++
 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi           |  192 +++++++++++++++
 arch/arm/boot/dts/vexpress-v2m.dtsi               |  191 +++++++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca5s.dts           |  132 ++++++++++
 arch/arm/boot/dts/vexpress-v2p-ca9.dts            |  146 +++++++++++
 arch/arm/include/asm/hardware/arm_timer.h         |    5 +
 arch/arm/mach-vexpress/Kconfig                    |   35 +++
 arch/arm/mach-vexpress/Makefile                   |    1 +
 arch/arm/mach-vexpress/Makefile.boot              |    6 +
 arch/arm/mach-vexpress/core.h                     |   21 ++-
 arch/arm/mach-vexpress/ct-ca9x4.c                 |   52 +---
 arch/arm/mach-vexpress/include/mach/ct-ca9x4.h    |   13 +-
 arch/arm/mach-vexpress/include/mach/debug-macro.S |   37 +++-
 arch/arm/mach-vexpress/include/mach/motherboard.h |   58 +++--
 arch/arm/mach-vexpress/include/mach/uncompress.h  |   13 +-
 arch/arm/mach-vexpress/platsmp.c                  |    4 +-
 arch/arm/mach-vexpress/v2m.c                      |  265 ++++++++++++++++++---

Quoted 8 lines

 arch/arm/mach-vexpress/v2p-ca5s_ca9.c             |  115 +++++++++
 18 files changed, 1272 insertions(+), 115 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/vexpress
 create mode 100644 arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
 create mode 100644 arch/arm/boot/dts/vexpress-v2m.dtsi
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca5s.dts
 create mode 100644 arch/arm/boot/dts/vexpress-v2p-ca9.dts
 create mode 100644 arch/arm/mach-vexpress/v2p-ca5s_ca9.c

Other than Dave's comments, looks good. For the series:

Acked-by Rob Herring <[email protected]>

There are a number of compatible strings for various peripherals defined without documentation, but you're not really using them so I think it's fine for now. BTW, I believe Dave said he was going to document some of the primecell peripherals. :)

Oh, btw, git am reports a few whitespace errors on the last full post of the series (v2).

Can you shove the series through checkpatch.pl and/or git am and fix any minor issues, now that the series is relatively stable?

Quoted 5 lines · Dave Martin

Oh, btw, git am reports a few whitespace errors on the last full post of the series (v2).

Can you shove the series through checkpatch.pl and/or git am and fix any minor issues, now that the series is relatively stable?

I did, actually:

8<--------------------------------------------------------------------

$ scripts/checkpatch.pl 0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch 
total: 0 errors, 0 warnings, 363 lines checked

0001-ARM-vexpress-Get-rid-of-MMIO_P2V.patch has no obvious style problems and is ready for submission.

$ scripts/checkpatch.pl 0002-ARM-vexpress-Add-DT-support-in-v2m.patch 
total: 0 errors, 0 warnings, 505 lines checked

0002-ARM-vexpress-Add-DT-support-in-v2m.patch has no obvious style problems and is ready for submission.

$ scripts/checkpatch.pl 0003-ARM-vexpress-Initial-RS1-memory-map-support.patch 
WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#308: FILE: arch/arm/mach-vexpress/include/mach/uncompress.h:25:
+#define AMBA_PERIPH_ID0(base)	(*(volatile unsigned char *)((base) + 0xfe0))

total: 0 errors, 1 warnings, 368 lines checked

0003-ARM-vexpress-Initial-RS1-memory-map-support.patch has style problems, please review.

If any of these errors are false positives, please report them to the maintainer, see CHECKPATCH in MAINTAINERS.

$ scripts/checkpatch.pl 0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch 
total: 0 errors, 0 warnings, 424 lines checked

0004-ARM-vexpress-DT-based-support-for-CoreTiles-Express-.patch has no obvious style problems and is ready for submission. 8<--------------------------------------------------------------------

In the past I noticed that same - sometimes git am is complaining when chechpatch is clean. I never was determined to figure out why, though...

Other than Dave's comments, looks good. For the series:

Acked-by Rob Herring <[email protected]>

There are a number of compatible strings for various peripherals defined without documentation, but you're not really using them so I think it's fine for now. BTW, I believe Dave said he was going to document some of the primecell peripherals. :)

Quoted 3 lines · Rob Herring

Other than Dave's comments, looks good. For the series:

Acked-by Rob Herring <[email protected]>

Thanks!

Quoted 4 lines

There are a number of compatible strings for various peripherals defined without documentation, but you're not really using them so I think it's fine for now. BTW, I believe Dave said he was going to document some of the primecell peripherals. :)

Yep, we agreed with Dave that the ones I'll take care of soon are MMCI (PL180) and the VE sysregs, the rest is his :-)

On that subject - some time ago I sent a patch adding "sil" vendor string, as this one the only non-documented one I used:

http://article.gmane.org/gmane.linux.drivers.devicetree/9362/

Okay. I'll apply.

But that's just a vendor. There's still binding docs needed for the actual sil9022 device and some others.