i.mx: add the initial i.mx6q core/board support

This patch-set add the initial support for freescale i.mx6q support. freescale i.mx6q is a quad core built on arm cortex_a9 complex.

The patch-set has been tested ok on freescale i.mx6q Armadillo2 board and also make sure it does not break i.mx5 support

The v1 patch-set has also been tested Ok by: Dirk Behme

The patch-set is based on Stefano's uart clean up patch:
http://patchwork.ozlabs.org/patch/127115/

Jason Liu (5):
i.mx: introduce the armv7/imx-common folder
i.mx: add the initial support for freescale i.MX6Q processor i.mx: mxc_gpio: add the i.mx6q support
i.mx: fsl_esdhc: add the i.mx6q support
i.mx: i.mx6q: add the initial support for i.mx6q ARM2 board

 MAINTAINERS                                        |    1 +
 Makefile                                           |    8 +
 arch/arm/cpu/armv7/imx-common/Makefile             |   47 +
 arch/arm/cpu/armv7/imx-common/cpu.c                |  108 ++
 arch/arm/cpu/armv7/{mx5 => imx-common}/speed.c     |    0
 arch/arm/cpu/armv7/{mx5 => imx-common}/timer.c     |   17 +-
 arch/arm/cpu/armv7/mx5/Makefile                    |    2 +-
 arch/arm/cpu/armv7/mx5/soc.c                       |   77 -
 arch/arm/cpu/armv7/mx6/Makefile                    |   48 +
 arch/arm/cpu/armv7/mx6/clock.c                     |  366 +++++
 arch/arm/cpu/armv7/mx6/iomux-v3.c                  |   71 +
 .../cpu/armv7/{mx5/speed.c => mx6/lowlevel_init.S} |   27 +-
 arch/arm/cpu/armv7/mx6/soc.c                       |   82 +
 arch/arm/include/asm/arch-mx6/ccm_regs.h           |  892 +++++++++++
 .../mx5/speed.c => include/asm/arch-mx6/clock.h}   |   45 +-
 .../mx5/speed.c => include/asm/arch-mx6/gpio.h}    |   30 +-
 arch/arm/include/asm/arch-mx6/imx-regs.h           |  236 +++
 arch/arm/include/asm/arch-mx6/iomux-v3.h           |  103 ++
 arch/arm/include/asm/arch-mx6/mx6x_pins.h          | 1683 ++++++++++++++++++++
 .../speed.c => include/asm/arch-mx6/sys_proto.h}   |   31 +-
 board/freescale/mx6qarm2/Makefile                  |   42 +
 board/freescale/mx6qarm2/imximage.cfg              |  167 ++
 board/freescale/mx6qarm2/mx6qarm2.c                |  155 ++
 boards.cfg                                         |    1 +
 drivers/gpio/mxc_gpio.c                            |    4 +-
 drivers/mmc/fsl_esdhc.c                            |   12 +-
 include/configs/mx6qarm2.h                         |  162 ++
 27 files changed, 4251 insertions(+), 166 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/imx-common/Makefile
 create mode 100644 arch/arm/cpu/armv7/imx-common/cpu.c
 copy arch/arm/cpu/armv7/{mx5 => imx-common}/speed.c (100%)
 rename arch/arm/cpu/armv7/{mx5 => imx-common}/timer.c (84%)
 mode change 100644 => 100755
 create mode 100644 arch/arm/cpu/armv7/mx6/Makefile
 create mode 100644 arch/arm/cpu/armv7/mx6/clock.c
 create mode 100644 arch/arm/cpu/armv7/mx6/iomux-v3.c
 copy arch/arm/cpu/armv7/{mx5/speed.c => mx6/lowlevel_init.S} (58%)
 create mode 100644 arch/arm/cpu/armv7/mx6/soc.c
 create mode 100644 arch/arm/include/asm/arch-mx6/ccm_regs.h
 copy arch/arm/{cpu/armv7/mx5/speed.c => include/asm/arch-mx6/clock.h} (59%)
 copy arch/arm/{cpu/armv7/mx5/speed.c => include/asm/arch-mx6/gpio.h} (64%)
 create mode 100644 arch/arm/include/asm/arch-mx6/imx-regs.h
 create mode 100644 arch/arm/include/asm/arch-mx6/iomux-v3.h
 create mode 100644 arch/arm/include/asm/arch-mx6/mx6x_pins.h
 rename arch/arm/{cpu/armv7/mx5/speed.c => include/asm/arch-mx6/sys_proto.h} (65%)
 create mode 100644 board/freescale/mx6qarm2/Makefile
 create mode 100644 board/freescale/mx6qarm2/imximage.cfg
 create mode 100644 board/freescale/mx6qarm2/mx6qarm2.c
 create mode 100644 include/configs/mx6qarm2.h

1.7.4.1

In order to support the coming MX6 platform and to reducde the duplicated code, we had better move some common files or functions to the imx-common folder for sharing.

This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature added but just fix the checkpatch errors in the old file and remove the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6

---
V2:extend the commit message to reflect all the changes in the patch
rename cpu_info.c to cpu.c file under imx-common as Stefano comments

---
 Makefile                                       |    8 ++
 arch/arm/cpu/armv7/imx-common/Makefile         |   47 ++++++++++
 arch/arm/cpu/armv7/imx-common/cpu.c            |  108 ++++++++++++++++++++++++
 arch/arm/cpu/armv7/{mx5 => imx-common}/speed.c |    0
 arch/arm/cpu/armv7/{mx5 => imx-common}/timer.c |   17 ++--
 arch/arm/cpu/armv7/mx5/Makefile                |    2 +-
 arch/arm/cpu/armv7/mx5/soc.c                   |   77 -----------------
 7 files changed, 173 insertions(+), 86 deletions(-)

index d84b350..977da65 100644
@@ -293,6 +293,14 @@ LIBS += post/libpost.o
 ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
 LIBS += $(CPUDIR)/omap-common/libomap-common.o
 endif
+
+ifeq ($(SOC),mx5)
+LIBS += $(CPUDIR)/imx-common/libimx-common.o
+endif
+ifeq ($(SOC),mx6)
+LIBS += $(CPUDIR)/imx-common/libimx-common.o
+endif
+
 ifeq ($(SOC),s5pc1xx)
 LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
 endif

similarity index 100%
rename from arch/arm/cpu/armv7/mx5/speed.c
rename to arch/arm/cpu/armv7/imx-common/speed.c

old mode 100644
new mode 100755
similarity index 84%
rename from arch/arm/cpu/armv7/mx5/timer.c
rename to arch/arm/cpu/armv7/imx-common/timer.c
index 2544b08..98e9f4a
@@ -39,10 +39,11 @@ struct mxc_gpt {
 static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
 
 /* General purpose timers bitfields */
-#define GPTCR_SWR       (1<<15)	/* Software reset */
-#define GPTCR_FRR       (1<<9)	/* Freerun / restart */
-#define GPTCR_CLKSOURCE_32 (4<<6)	/* Clock source */
-#define GPTCR_TEN       (1)	/* Timer enable */
+#define GPTCR_SWR		(1 << 15)	/* Software reset */
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart */
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source */
+#define GPTCR_TEN		1		/* Timer enable */
+#define CLK_32KHZ		32768		/* 32Khz input */
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -68,7 +69,7 @@ int timer_init(void)
 	__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
 
 	val = __raw_readl(&cur_gpt->counter);
-	lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
+	lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
 	timestamp = 0;
 
 	return 0;

@@ -77,11 +78,11 @@ int timer_init(void)
 ulong get_timer_masked(void)
 {
 	ulong val = __raw_readl(&cur_gpt->counter);
-	val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
+	val /= (CLK_32KHZ / CONFIG_SYS_HZ);
 	if (val >= lastinc)
 		timestamp += (val - lastinc);
 	else
-		timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
+		timestamp += ((0xFFFFFFFF / (CLK_32KHZ / CONFIG_SYS_HZ))
 				- lastinc) + val;
 	lastinc = val;
 	return timestamp;

@@ -96,7 +97,7 @@ ulong get_timer(ulong base)
 void __udelay(unsigned long usec)
 {
 	unsigned long now, start, tmo;
-	tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
+	tmo = usec * (CLK_32KHZ / 1000) / 1000;
 
 	if (!tmo)
 		tmo = 1;

index e8be9c9..ecd1184 100644
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	= soc.o clock.o iomux.o timer.o speed.o
+COBJS	= soc.o clock.o iomux.o
 SOBJS = lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

1.7.4.1

Some bits in this register is w1c, so clear it here.

i.MX6Q is freescale quad core processors with ARM cortex_a9 complex. This patch is to add the initial support for this processor.

---
v3:cosmetic: line too long, extra blank line,
use AIPS1_BASE_ADDR to comply with mx5 naming,
remove the extra AIPS setting

v2:put aips init to c code as Marek suggest
remove the parenthesis such as (2)
remork get_usdhcx_clk() to get_usdhc_clk(port) remove the iomux base init and assign it staticly correct the chip rev print-message(rev1.0)

for better readable, the pin definition on oneline will have some checkpatch warning(line too long), I have seen there is such condition in Linux kernel and u-boot mainline code.

---
 arch/arm/cpu/armv7/mx6/Makefile           |   48 +
 arch/arm/cpu/armv7/mx6/clock.c            |  366 +++++++
 arch/arm/cpu/armv7/mx6/iomux-v3.c         |   71 ++
 arch/arm/cpu/armv7/mx6/lowlevel_init.S    |   24 +
 arch/arm/cpu/armv7/mx6/soc.c              |   82 ++
 arch/arm/include/asm/arch-mx6/ccm_regs.h  |  892 +++++++++++++++
 arch/arm/include/asm/arch-mx6/clock.h     |   50 +
 arch/arm/include/asm/arch-mx6/gpio.h      |   35 +
 arch/arm/include/asm/arch-mx6/imx-regs.h  |  236 ++++
 arch/arm/include/asm/arch-mx6/iomux-v3.h  |  103 ++
 arch/arm/include/asm/arch-mx6/mx6x_pins.h | 1683 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx6/sys_proto.h |   38 +
 12 files changed, 3628 insertions(+), 0 deletions(-)

new file mode 100644
index 0000000..b0da028
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= soc.o clock.o iomux-v3.o
+SOBJS   = lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

new file mode 100644
index 0000000..1864356
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+.section ".text.init", "x"
+
+.globl lowlevel_init
+lowlevel_init:
+
+	mov pc, lr

new file mode 100644
index 0000000..20c4e57
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2011
+ * Stefano Babic, DENX Software Engineering, <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __ASM_ARCH_MX6_GPIO_H
+#define __ASM_ARCH_MX6_GPIO_H
+
+/* GPIO registers */
+struct gpio_regs {
+	u32	gpio_dr;
+	u32	gpio_dir;
+	u32	gpio_psr;
+};
+
+#endif	/* __ASM_ARCH_MX6_GPIO_H */

new file mode 100644
index 0000000..668e77a

1.7.4.1

Part of the diff is not shown here. View the raw message.

The questions is that which location and encode schema we need follow, take a look at mx5, it is different with mx51 and mx53, so before the new tapout of i.mx6q, I don't have a clear vision about it.

---
V2: add Stefano's ack

---
 drivers/gpio/mxc_gpio.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

index a7f36b2..908808d 100644
@@ -40,10 +40,10 @@ static unsigned long gpio_ports[] = {
 	[0] = GPIO1_BASE_ADDR,
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
 	[3] = GPIO4_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX53)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6Q)
 	[4] = GPIO5_BASE_ADDR,
 	[5] = GPIO6_BASE_ADDR,
 	[6] = GPIO7_BASE_ADDR,

1.7.4.1

The mmc host controller on the i.mx6q is called usdhc which is redesigned based on the freescale esdhc controller.

The usdhc controller is almost compatible with esdhc except it adds one mix register to support debug/SD3.0 and move the low bit 0-6 of XFERTYP register to the mix control reg low bit 0-6. Thus on i.mx6q, we have the following compared with the previous soc: (can refer to RM of chapter 56.3.3)

i.mx6q:
mix control:
bit 31 - bit 7: Added for debug/SD3.0 support
bit 6 - bit 0: move in the XFERTYP register bit 6-0 on previous soc XFERTYP register:
bit 31 - bit 7: the same as before,
bit 6 - bit 0: no-use

previous soc
mix control: no
XFERTYP register:
bit 31 - bit 0: xfertype information

---
v3: cc Andy for mmc maintainer
v2: extend the commit message by adding mix/xtertype register change
remove one #ifdef as Marek suggested
change the print of USDHC/ESDHC to SDHC

---
 drivers/mmc/fsl_esdhc.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

index ec953f0..ddd1b4c 100644
@@ -58,7 +58,8 @@ struct fsl_esdhc {
 	uint	autoc12err;
 	uint	hostcapblt;
 	uint	wml;
-	char	reserved1[8];
+	uint    mixctrl;
+	char    reserved1[4];
 	uint	fevt;
 	char	reserved2[168];
 	uint	hostver;

@@ -298,8 +299,13 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	/* Send the command */
 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
+#if defined(CONFIG_FSL_USDHC)
+	esdhc_write32(&regs->mixctrl,
+	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
+	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
+#else
 	esdhc_write32(&regs->xfertyp, xfertyp);
-
+#endif
 	/* Wait for the command to complete */
 	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
 		;

@@ -482,7 +488,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 
 	mmc = malloc(sizeof(struct mmc));
 
-	sprintf(mmc->name, "FSL_ESDHC");
+	sprintf(mmc->name, "FSL_SDHC");
 	regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
 	/* First reset the eSDHC controller */

1.7.4.1

Applied to mmc-next branch, thanks!

Andy

Add the initial support for Freescale i.MX6Q Armadillo2 board
Support: MMC boot from slot 0/1, debug UART(UART4), usdhc.

There is two MMC slots on the boards:
mmc dev 0 -> connect USDHC3 -> the lower slot on the board, mmc dev 1 -> connect USDHC4 -> the upper slot on the board,

---
v3: based on the uart clean up patch:http://patchwork.ozlabs.org/patch/127115/
add CONFIG_MXC_UART_BASE,remove CONFIG_MX6Q_UART4 in board config file

v2:fix sd3 card detection GPIO
remove unneeded parentheses such as (IRAM_SIZE)
remove clean and distclean targets in Makefile
remove CONFIG_MACH_TYPE setup since linux use DT
some cleanup/improvement for the config file from Dirk remove imx_iomux_v3_init call since assign the base in iomux-v3.c improve the commit message to add the mmc slot description

---
 MAINTAINERS                           |    1 +
 board/freescale/mx6qarm2/Makefile     |   42 ++++++++
 board/freescale/mx6qarm2/imximage.cfg |  167 +++++++++++++++++++++++++++++++++
 board/freescale/mx6qarm2/mx6qarm2.c   |  155 ++++++++++++++++++++++++++++++
 boards.cfg                            |    1 +
 include/configs/mx6qarm2.h            |  162 ++++++++++++++++++++++++++++++++
 6 files changed, 528 insertions(+), 0 deletions(-)

index f6f6b72..52d86bd 100644
@@ -568,6 +568,7 @@ Jason Liu <[email protected]>
 
 	mx53evk         i.MX53
 	mx53loco        i.MX53
+	mx6qarm2	i.MX6Q
 
 Enric Balletbo i Serra <[email protected]>
 

index c83d861..f50ec57 100644
@@ -177,6 +177,7 @@ mx53evk                      arm         armv7       mx53evk             freesca
 mx53loco                     arm         armv7       mx53loco            freescale      mx5		mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
 mx53smd                      arm         armv7       mx53smd             freescale      mx5		mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
 vision2                      arm         armv7       vision2             ttcontrol      mx5		vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
+mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6		mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
 cm_t35                       arm         armv7       cm_t35              -              omap3
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3

1.7.4.1

Jason,

I have no open issues with your patches. I have applied them (at the moment) to u-boot-imx, next branch.

I know that the patches were sent after the patches window was closed. However, they do not introduce so big changes to current IMX code, as MX5 did in the past, and I will not be against to merge them into the master branch in the next pull request, if nobody complains about it.

Best regards,
Stefano babic

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

+1

Thanks

Dirk