ARM: OMAP2+: Interrupt controllers adaptation to DT

Add a function to initialize the OMAP2/3 interrupt controller (INTC) using a device tree node.

Replace some printk() with the proper pr_ macro.

Signed-off-by Benoit Cousson <[email protected]>

Cc Tony Lindgren <[email protected]>

---
 .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++++++++
 arch/arm/mach-omap2/common.h                       |   10 ++++++
 arch/arm/mach-omap2/irq.c                          |   35 ++++++++++++++++++--
 3 files changed, 69 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

Documentation/devicetree/bindings/arm/omap/intc.txt new file +27 -0

new file mode 100644
index 0000000..f2583e6
@@ -0,0 +1,27 @@
+* OMAP Interrupt Controller
+
+OMAP2/3 are using a TI interrupt controller that can support several
+configurable number of interrupts.
+
+Main node required properties:
+
+- compatible : should be:
+	"ti,omap2-intc"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 1.
+
+  The cell contains the interrupt number in the range [0-128].
+- ti,intc-size: Number of interrupts handled by the interrupt controller.
+- reg: physical base address and size of the intc registers map.
+
+Example:
+
+	intc: interrupt-controller at 1 {
+		compatible = "ti,omap2-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		ti,intc-size = <96>;
+		reg = <0x48200000 0x1000>;
+	};
+

arch/arm/mach-omap2/common.h +10 -0

index 012bac7..bcfccc2 100644
@@ -156,6 +156,16 @@ void omap3_intc_resume_idle(void);
 void omap2_intc_handle_irq(struct pt_regs *regs);
 void omap3_intc_handle_irq(struct pt_regs *regs);
 
+struct device_node;
+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node *parent);
+#else
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	return 0;
+}
+#endif
+
 /*
  * wfi used in low power code. Directly opcode is used instead
  * of instruction to avoid mulit-omap build break

arch/arm/mach-omap2/irq.c +13 -3

index 42b1d65..cafc663 100644
@@ -17,6 +17,9 @@
 #include <mach/hardware.h>
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/irqdomain.h>
 
 
 /* selected INTC register offsets */

@@ -166,7 +169,7 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 		/* Static mapping, never released */
 		bank->base_reg = ioremap(base, SZ_4K);
 		if (!bank->base_reg) {
-			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+			pr_err("Could not ioremap irq bank%i\n", i);
 			continue;
 		}
 

@@ -179,8 +182,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 		nr_banks++;
 	}
 
-	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+	pr_info("Total of %ld interrupts on %d active controller%s\n",
+		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 }
 
 void __init omap2_init_irq(void)

@@ -236,6 +239,32 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
 	omap_intc_handle_irq(base_addr, regs);
 }
 
+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+	u32 nr_irqs;
+
+	if (WARN_ON(!node))

On 12/07/2011 02:50 PM, Benoit Cousson wrote:

Quoted 11 lines

arch/arm/mach-omap2/irq.c +11 -0

+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+	u32 nr_irqs;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	if (of_address_to_resource(node, 0,&res)) {
+		WARN(1, "unable to get intc registers\n");

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 258

Quoted 6 lines

arch/arm/mach-omap2/irq.c +6 -0

+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(node, "ti,intc-size",&nr_irqs)) {
+		WARN(1, "unable to get intc-size\n");
+		return -EINVAL;

There is no default value that makes sense?

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 262

Quoted 4 lines

arch/arm/mach-omap2/irq.c +4 -0

+	}
+
+	omap_init_irq(res.start, nr_irqs);
+	irq_domain_add_simple(node, 0);

Have you read the NO_IRQ thread...

Is 0 ever a valid interrupt for a driver? If so, you must not use 0 for the base. I would pick 16 to skip over legacy ISA irqs.

irqdomains should always be enabled regardless of CONFIG_OF. So either you can leave it as is if OF is always enabled for OMAP, or you should move domain setup into omap_init_irq.

Quoted 1 line · Rob Herring

On 12/07/2011 02:50 PM, Benoit Cousson wrote:

[...]

Quoted 12 lines

Quoted 12 lines

(quoted diff) +2 -0

+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node

*parent)

arch/arm/mach-omap2/irq.c +9 -0

+{
+    struct resource res;
+    u32 nr_irqs;
+
+    if (WARN_ON(!node))
+        return -ENODEV;
+
+    if (of_address_to_resource(node, 0,&res)) {
+        WARN(1, "unable to get intc registers\n");

Quoted 8 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 258

Quoted 6 lines

arch/arm/mach-omap2/irq.c +6 -0

+        return -EINVAL;
+    }
+
+    if (of_property_read_u32(node, "ti,intc-size",&nr_irqs)) {
+        WARN(1, "unable to get intc-size\n");
+        return -EINVAL;

There is no default value that makes sense?

So far we have 96 or 128, so I can put 96 as a default and just keep the warning without returning an error.

Quoted 6 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 262

Quoted 4 lines

arch/arm/mach-omap2/irq.c +4 -0

+    }
+
+    omap_init_irq(res.start, nr_irqs);
+    irq_domain_add_simple(node, 0);

Have you read the NO_IRQ thread...

Yeah, I tried, but that's a long email thread with some unclear conclusion...
The point is that the few users of that API today are using 0 as a base as well, so I thought it was still valid.

Quoted 2 lines

Is 0 ever a valid interrupt for a driver? If so, you must not use 0 for the base. I would pick 16 to skip over legacy ISA irqs.

I do not have any 0 interrupts right now, my concern is that I still have some legacy non-DT drivers that expect the previous hwirq = irq mapping.

Quoted 4 lines

irqdomains should always be enabled regardless of CONFIG_OF. So either you can leave it as is if OF is always enabled for OMAP, or you should move domain setup into omap_init_irq.

OK, but it looks like I cannot really modify the current INTC to DT without having fully adapted the OMAP drivers to use irq_of_parse_and_map. Or did I miss something?

Quoted 44 lines · Benoit

Quoted 1 line · Rob Herring

On 12/07/2011 02:50 PM, Benoit Cousson wrote:

[...]

Quoted 12 lines

Quoted 12 lines

(quoted diff) +2 -0

+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node

*parent)

arch/arm/mach-omap2/irq.c +9 -0

+{
+    struct resource res;
+    u32 nr_irqs;
+
+    if (WARN_ON(!node))
+        return -ENODEV;
+
+    if (of_address_to_resource(node, 0,&res)) {
+        WARN(1, "unable to get intc registers\n");

Quoted 8 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 258

Quoted 6 lines

arch/arm/mach-omap2/irq.c +6 -0

+        return -EINVAL;
+    }
+
+    if (of_property_read_u32(node, "ti,intc-size",&nr_irqs)) {
+        WARN(1, "unable to get intc-size\n");
+        return -EINVAL;

There is no default value that makes sense?

So far we have 96 or 128, so I can put 96 as a default and just keep the warning without returning an error.

Quoted 6 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 262

Quoted 4 lines

arch/arm/mach-omap2/irq.c +4 -0

+    }
+
+    omap_init_irq(res.start, nr_irqs);
+    irq_domain_add_simple(node, 0);

Have you read the NO_IRQ thread...

Yeah, I tried, but that's a long email thread with some unclear conclusion...
The point is that the few users of that API today are using 0 as a base as well, so I thought it was still valid.

Quoted 2 lines

Is 0 ever a valid interrupt for a driver? If so, you must not use 0 for the base. I would pick 16 to skip over legacy ISA irqs.

Quoted 3 lines

I do not have any 0 interrupts right now, my concern is that I still have some legacy non-DT drivers that expect the previous hwirq = irq mapping.

I guess it depends how easily you can shift all the irq defines. You allow specifying the base so that you can set it to 0 for non-DT and -1 (dynamic allocation) for DT.

Quoted 4 lines

Quoted 3 lines

irqdomains should always be enabled regardless of CONFIG_OF. So either you can leave it as is if OF is always enabled for OMAP, or you should move domain setup into omap_init_irq.

Quoted 4 lines

OK, but it looks like I cannot really modify the current INTC to DT without having fully adapted the OMAP drivers to use irq_of_parse_and_map. Or did I miss something?

No, the drivers should not need to be modified as long as they get the irq's from platform device resources. You just want to make sure the INTC has no knowledge of it's irq base so it can change.

Quoted 45 lines · Rob Herring

Quoted 44 lines · Benoit

Quoted 1 line · Rob Herring

On 12/07/2011 02:50 PM, Benoit Cousson wrote:

[...]

Quoted 12 lines

Quoted 12 lines

(quoted diff) +2 -0

+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node

*parent)

arch/arm/mach-omap2/irq.c +9 -0

+{
+    struct resource res;
+    u32 nr_irqs;
+
+    if (WARN_ON(!node))
+        return -ENODEV;
+
+    if (of_address_to_resource(node, 0,&res)) {
+        WARN(1, "unable to get intc registers\n");

Quoted 8 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 258

Quoted 6 lines

arch/arm/mach-omap2/irq.c +6 -0

+        return -EINVAL;
+    }
+
+    if (of_property_read_u32(node, "ti,intc-size",&nr_irqs)) {
+        WARN(1, "unable to get intc-size\n");
+        return -EINVAL;

There is no default value that makes sense?

So far we have 96 or 128, so I can put 96 as a default and just keep the warning without returning an error.

Quoted 6 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 262

Quoted 4 lines

arch/arm/mach-omap2/irq.c +4 -0

+    }
+
+    omap_init_irq(res.start, nr_irqs);
+    irq_domain_add_simple(node, 0);

Have you read the NO_IRQ thread...

Yeah, I tried, but that's a long email thread with some unclear conclusion...
The point is that the few users of that API today are using 0 as a base as well, so I thought it was still valid.

Quoted 2 lines

Is 0 ever a valid interrupt for a driver? If so, you must not use 0 for the base. I would pick 16 to skip over legacy ISA irqs.

Quoted 7 lines

Quoted 3 lines

I do not have any 0 interrupts right now, my concern is that I still have some legacy non-DT drivers that expect the previous hwirq = irq mapping.

I guess it depends how easily you can shift all the irq defines. You allow specifying the base so that you can set it to 0 for non-DT and -1 (dynamic allocation) for DT.

The issue, is that the IRQs are not defined anymore but hard coded in the hwmod database. And the idea is that this is reflecting exactly the hwirq from the spec, so I do not want to add any artificial offset for the domain in the original data.

Quoted 4 lines

Quoted 4 lines

Quoted 3 lines

irqdomains should always be enabled regardless of CONFIG_OF. So either you can leave it as is if OF is always enabled for OMAP, or you should move domain setup into omap_init_irq.

Quoted 8 lines

Quoted 4 lines

OK, but it looks like I cannot really modify the current INTC to DT without having fully adapted the OMAP drivers to use irq_of_parse_and_map. Or did I miss something?

No, the drivers should not need to be modified as long as they get the irq's from platform device resources. You just want to make sure the INTC has no knowledge of it's irq base so it can change.

OK, the driver will not have to change but the IRQ value will not be the same in the case of DT since it will use the irq_create_of_mapping.

Currently, the driver IRQ resource is 7 for example for the twl, this is the hwirq (= irq). If I use a domain with a base of 16, the resource will still be 7 except if the resource is created from OF, then it will be 23.

The only way I have today to maintain the legacy drivers to work without hacking the OMAP resource code is to keep the base_irq at 0.

Since I do not have any hwirq at 0 so far, is it a big deal to keep the base_irq at 0 for the moment?
It will be easier to transition to DT that way without breaking the existing drivers.

Quoted 80 lines · Benoit

Quoted 45 lines · Rob Herring

Quoted 44 lines · Benoit

Quoted 1 line · Rob Herring

On 12/07/2011 02:50 PM, Benoit Cousson wrote:

[...]

Quoted 12 lines

Quoted 12 lines

(quoted diff) +2 -0

+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node

*parent)

arch/arm/mach-omap2/irq.c +9 -0

+{
+    struct resource res;
+    u32 nr_irqs;
+
+    if (WARN_ON(!node))
+        return -ENODEV;
+
+    if (of_address_to_resource(node, 0,&res)) {
+        WARN(1, "unable to get intc registers\n");

Quoted 8 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 258

Quoted 6 lines

arch/arm/mach-omap2/irq.c +6 -0

+        return -EINVAL;
+    }
+
+    if (of_property_read_u32(node, "ti,intc-size",&nr_irqs)) {
+        WARN(1, "unable to get intc-size\n");
+        return -EINVAL;

There is no default value that makes sense?

So far we have 96 or 128, so I can put 96 as a default and just keep the warning without returning an error.

Quoted 6 lines

arch/arm/mach-omap2/irq.c asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs · line 262

Quoted 4 lines

arch/arm/mach-omap2/irq.c +4 -0

+    }
+
+    omap_init_irq(res.start, nr_irqs);
+    irq_domain_add_simple(node, 0);

Have you read the NO_IRQ thread...

Yeah, I tried, but that's a long email thread with some unclear conclusion...
The point is that the few users of that API today are using 0 as a base as well, so I thought it was still valid.

Quoted 2 lines

Is 0 ever a valid interrupt for a driver? If so, you must not use 0 for the base. I would pick 16 to skip over legacy ISA irqs.

Quoted 7 lines

Quoted 3 lines

I do not have any 0 interrupts right now, my concern is that I still have some legacy non-DT drivers that expect the previous hwirq = irq mapping.

I guess it depends how easily you can shift all the irq defines. You allow specifying the base so that you can set it to 0 for non-DT and -1 (dynamic allocation) for DT.

The issue, is that the IRQs are not defined anymore but hard coded in the hwmod database. And the idea is that this is reflecting exactly the hwirq from the spec, so I do not want to add any artificial offset for the domain in the original data.

Quoted 4 lines

Quoted 4 lines

Quoted 3 lines

irqdomains should always be enabled regardless of CONFIG_OF. So either you can leave it as is if OF is always enabled for OMAP, or you should move domain setup into omap_init_irq.

Quoted 8 lines

Quoted 4 lines

OK, but it looks like I cannot really modify the current INTC to DT without having fully adapted the OMAP drivers to use irq_of_parse_and_map. Or did I miss something?

No, the drivers should not need to be modified as long as they get the irq's from platform device resources. You just want to make sure the INTC has no knowledge of it's irq base so it can change.

OK, the driver will not have to change but the IRQ value will not be the same in the case of DT since it will use the irq_create_of_mapping.

Currently, the driver IRQ resource is 7 for example for the twl, this is the hwirq (= irq). If I use a domain with a base of 16, the resource will still be 7 except if the resource is created from OF, then it will be 23.

Quoted 3 lines

The only way I have today to maintain the legacy drivers to work without hacking the OMAP resource code is to keep the base_irq at 0.

For non-DT case, that is fine. It should not be hard to support 0 for legacy and !0 for DT.

Quoted 4 lines

Since I do not have any hwirq at 0 so far, is it a big deal to keep the base_irq at 0 for the moment?
It will be easier to transition to DT that way without breaking the existing drivers.

As long as it is trivial to change later. I'm afraid that if it is not changed, then we won't know if it is trivial.

Quoted 87 lines · Rob Herring

Quoted 86 lines · Benoit

Quoted 49 lines · Rob Herring

Quoted 48 lines · Benoit

Quoted 1 line · Rob Herring

On 12/07/2011 02:50 PM, Benoit Cousson wrote:

[...]

Quoted 13 lines

Quoted 13 lines

(quoted diff) +2 -0

+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct

device_node
*parent)

(quoted diff) +9 -0

+{
+    struct resource res;
+    u32 nr_irqs;
+
+    if (WARN_ON(!node))
+        return -ENODEV;
+
+    if (of_address_to_resource(node, 0,&res)) {
+        WARN(1, "unable to get intc registers\n");

Quoted 8 lines

Review

Quoted 6 lines

(quoted diff) +6 -0

+        return -EINVAL;
+    }
+
+    if (of_property_read_u32(node, "ti,intc-size",&nr_irqs)) {
+        WARN(1, "unable to get intc-size\n");
+        return -EINVAL;

There is no default value that makes sense?

So far we have 96 or 128, so I can put 96 as a default and just keep the
warning without returning an error.

Quoted 6 lines

Review

Quoted 4 lines

(quoted diff) +4 -0

+    }
+
+    omap_init_irq(res.start, nr_irqs);
+    irq_domain_add_simple(node, 0);

Have you read the NO_IRQ thread...

Yeah, I tried, but that's a long email thread with some unclear conclusion...
The point is that the few users of that API today are using 0 as a base
as well, so I thought it was still valid.

Quoted 3 lines

Is 0 ever a valid interrupt for a driver? If so, you must not use 0 for
the base. I would pick 16 to skip over legacy ISA irqs.

Quoted 7 lines

Quoted 3 lines

I do not have any 0 interrupts right now, my concern is that I still have some legacy non-DT drivers that expect the previous hwirq = irq mapping.

I guess it depends how easily you can shift all the irq defines. You allow specifying the base so that you can set it to 0 for non-DT and -1 (dynamic allocation) for DT.

The issue, is that the IRQs are not defined anymore but hard coded in the hwmod database. And the idea is that this is reflecting exactly the hwirq from the spec, so I do not want to add any artificial offset for the domain in the original data.

Quoted 6 lines

Quoted 6 lines

Quoted 5 lines

irqdomains should always be enabled regardless of CONFIG_OF. So either
you can leave it as is if OF is always enabled for OMAP, or you should
move domain setup into omap_init_irq.

Quoted 8 lines

Quoted 4 lines

OK, but it looks like I cannot really modify the current INTC to DT without having fully adapted the OMAP drivers to use irq_of_parse_and_map. Or did I miss something?

No, the drivers should not need to be modified as long as they get the irq's from platform device resources. You just want to make sure the INTC has no knowledge of it's irq base so it can change.

OK, the driver will not have to change but the IRQ value will not be the same in the case of DT since it will use the irq_create_of_mapping.

Currently, the driver IRQ resource is 7 for example for the twl, this is the hwirq (= irq). If I use a domain with a base of 16, the resource will still be 7 except if the resource is created from OF, then it will be 23.

Quoted 6 lines

Quoted 3 lines

The only way I have today to maintain the legacy drivers to work without hacking the OMAP resource code is to keep the base_irq at 0.

For non-DT case, that is fine. It should not be hard to support 0 for legacy and !0 for DT.

Mmm, I'm probably missing something here.

My point is that even in the DT case I do have some devices that are initialized without DT for the moment and thus cannot get access to the interrupt-controller node and then cannot retrieve the domain information.

How can I ensure the proper hwirq -> irq translation then for such devices? Only the one created by DT will have the correct irq number.

Adding some hacks to add a +16 is clearly possible, but that will be a dirty hacks in the OMAP core code that will have to be removed later. So I'd rather keep the domain with a 0 offset to avoid all these temporary hacks.

Quoted 7 lines

Quoted 4 lines

Since I do not have any hwirq at 0 so far, is it a big deal to keep the base_irq at 0 for the moment?
It will be easier to transition to DT that way without breaking the existing drivers.

As long as it is trivial to change later. I'm afraid that if it is not changed, then we won't know if it is trivial.

As soon as every devices are initialized from DT, the irq_base will become transparent, since both the IRQ handler and the IRQ resource will use the irq_domain_to_irq to get the irq from the hwirq. At that time adding 16 will then be straightforward.
That's why I prefer that approach which is the one that generate the minimal temporary effort.

Regards,
Benoit

On 12/09/2011 10:06 AM, Cousson, Benoit wrote:

Quoted 8 lines

Mmm, I'm probably missing something here.

My point is that even in the DT case I do have some devices that are initialized without DT for the moment and thus cannot get access to the interrupt-controller node and then cannot retrieve the domain information.

How can I ensure the proper hwirq -> irq translation then for such devices? Only the one created by DT will have the correct irq number.

Okay, I missed that aspect of it. So I guess 0 base is fine for now.

On 12/09/2011 10:06 AM, Cousson, Benoit wrote:

Quoted 6 lines

My point is that even in the DT case I do have some devices that are initialized without DT for the moment and thus cannot get access to the interrupt-controller node and then cannot retrieve the domain information.

How can I ensure the proper hwirq -> irq translation then for such devices? Only the one created by DT will have the correct irq number.

Okay, I missed that aspect of it. So I guess 0 base is fine for now.

Rob

From 3083589f48604aab3d801179810c2af8339525ae Mon Sep 17 00:00:00 2001

Quoted 1 line · Rob Herring

On 12/09/2011 10:06 AM, Cousson, Benoit wrote:

[...]

Quoted 7 lines

Quoted 6 lines

My point is that even in the DT case I do have some devices that are initialized without DT for the moment and thus cannot get access to the interrupt-controller node and then cannot retrieve the domain information.

How can I ensure the proper hwirq -> irq translation then for such devices? Only the one created by DT will have the correct irq number.

Quoted 3 lines

Okay, I missed that aspect of it. So I guess 0 base is fine for now.

Rob

Following that discussion, I made a patch (included below) last week to add domain support just before this one for DT migration. I'm now wondering if it makes sense to do it like that considering your recent patch: irq: convert generic-chip to use irq_domain.

What do you think?

Thanks,
Benoit

---
From 3083589f48604aab3d801179810c2af8339525ae Mon Sep 17 00:00:00 2001
From: Benoit Cousson <[email protected]>
Date: Thu, 8 Dec 2011 22:16:51 +0100
Subject: [PATCH] ARM: OMAP2/3: intc: Add irqdomain support

Introduce the usage of the irqdomain to prepare the DT support. The irq_base is still hard coded to 0 to allow non-DT drivers to work with the previous assumption that was hwirq = irq.

Signed-off-by Benoit Cousson <[email protected]>

Cc Tony Lindgren <[email protected]>

Cc Rob Herring <[email protected]>

---
 arch/arm/mach-omap2/irq.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

arch/arm/mach-omap2/irq.c +17 -1

index 42b1d65..2f65dfd 100644
@@ -17,6 +17,7 @@
 #include <mach/hardware.h>
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
+#include <linux/irqdomain.h>
 
 
 /* selected INTC register offsets */

@@ -57,6 +58,8 @@ static struct omap_irq_bank {
 	},
 };
 
+static struct irq_domain domain;
+
 /* Structure to save interrupt controller context */
 struct omap3_intc_regs {
 	u32 sysconfig;

@@ -158,6 +161,17 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 	if (WARN_ON(!omap_irq_base))
 		return;
 
+	/*
+	 * XXX: Use a 0 irq_base for the moment since the legacy devices
+	 * created statically are expected a hwirq = irq mapping.
+	 * A proper offset will be added later, when IRQ resource creation
+	 * will be handled by DT.
+	 */
+	domain.irq_base = 0;
+	domain.nr_irq = nr_irqs;
+	domain.ops = &irq_domain_simple_ops;
+	irq_domain_add(&domain);
+
 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 		struct omap_irq_bank *bank = irq_banks + i;
 

@@ -225,8 +239,10 @@ out:
 		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
 		irqnr &= ACTIVEIRQ_MASK;
 
-		if (irqnr)
+		if (irqnr) {
+			irqnr = irq_domain_to_irq(&domain, irqnr);
 			handle_IRQ(irqnr, regs);
+		}
 	} while (irqnr);
 }
 

arch/arm/mach-omap2/common.h +0 -0

index 012bac7..bcfccc2 100644
@@ -156,6 +156,16 @@ void omap3_intc_resume_idle(void);
  void omap2_intc_handle_irq(struct pt_regs *regs);

arch/arm/mach-omap2/common.h +2 -0

+#endif
+
  /*
   * wfi used in low power code. Directly opcode is used instead
   * of instruction to avoid mulit-omap build break

arch/arm/mach-omap2/irq.c +32 -3

index 42b1d65..cafc663 100644
@@ -17,6 +17,9 @@
  #include<mach/hardware.h>
  #include<asm/exception.h>
  #include<asm/mach/irq.h>
+#include<linux/of.h>
+#include<linux/of_address.h>
+#include<linux/irqdomain.h>
 
 
  /* selected INTC register offsets */

@@ -166,7 +169,7 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
  		/* Static mapping, never released */
  		bank->base_reg = ioremap(base, SZ_4K);
  		if (!bank->base_reg) {
-			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+			pr_err("Could not ioremap irq bank%i\n", i);
  			continue;
  		}
 

@@ -179,8 +182,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
  		nr_banks++;
  	}
 
-	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-	       nr_of_irqs, nr_banks, nr_banks>  1 ? "s" : "");
+	pr_info("Total of %ld interrupts on %d active controller%s\n",
+		nr_of_irqs, nr_banks, nr_banks>  1 ? "s" : "");
  }
 
  void __init omap2_init_irq(void)

@@ -236,6 +239,32 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
  	omap_intc_handle_irq(base_addr, regs);
  }
 
+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+	u32 nr_irqs;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	if (of_address_to_resource(node, 0,&res)) {
+		WARN(1, "unable to get intc registers\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(node, "ti,intc-size",&nr_irqs)) {
+		WARN(1, "unable to get intc-size\n");
+		return -EINVAL;
+	}
+
+	omap_init_irq(res.start, nr_irqs);
+	irq_domain_add_simple(node, 0);
+
+	return 0;
+}
+#endif
+
  #ifdef CONFIG_ARCH_OMAP3
  static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];