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ARM: EXYNOS4: Modified files for SPI consolidation work

PATCH New Padmavathi Venna 2 participants 2 messages Dec 14, 2011

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Arm (32-bit) Arm sub-architectures Arm Samsung Exynos
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Padmavathi Venna

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#0 lore raw

PATCH v3 1/1 ARM: EXYNOS4: Modified files for SPI consolidation work

As SPI platform devices are consolidated to plat-samsung, some corresponding changes are required in the respective machine folder. Setup files are added for SPI GPIO configurations and platform data initialization.

Signed-off-by Padmavathi Venna <[email protected]>
---
 arch/arm/mach-exynos/Kconfig                   |    5 ++
 arch/arm/mach-exynos/Makefile                  |    1 +
 arch/arm/mach-exynos/clock.c                   |   73 ++++++++++++++----------
 arch/arm/mach-exynos/include/mach/irqs.h       |    3 +
 arch/arm/mach-exynos/include/mach/map.h        |    7 ++
 arch/arm/mach-exynos/include/mach/spi-clocks.h |   17 ++++++
 arch/arm/mach-exynos/setup-spi.c               |   72 +++++++++++++++++++++++
 7 files changed, 148 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/mach-exynos/include/mach/spi-clocks.h
 create mode 100644 arch/arm/mach-exynos/setup-spi.c
arch/arm/mach-exynos/Kconfig +5 -0
index 0afcc3b..c925fec 100644
@@ -148,6 +148,11 @@ config EXYNOS4_SETUP_USB_PHY
 	help
 	  Common setup code for USB PHY controller
 
+config EXYNOS4_SETUP_SPI
+	bool
+	help
+	  Common setup code for SPI GPIO configurations.
+
 # machine support
 
 if ARCH_EXYNOS4
arch/arm/mach-exynos/Makefile +1 -0
index 57e5296..979fdd3 100644
@@ -60,3 +60,4 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7)	+= setup-i2c7.o
 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)	+= setup-keypad.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 obj-$(CONFIG_EXYNOS4_SETUP_USB_PHY)	+= setup-usb-phy.o
+obj-$(CONFIG_EXYNOS4_SETUP_SPI)		+= setup-spi.o
arch/arm/mach-exynos/clock.c +43 -30

97 lines not on this page · raw message

arch/arm/mach-exynos/include/mach/irqs.h +3 -0
index f7d73b1..1d401c9 100644
@@ -74,6 +74,9 @@
 #define IRQ_IIC5		IRQ_SPI(63)
 #define IRQ_IIC6		IRQ_SPI(64)
 #define IRQ_IIC7		IRQ_SPI(65)
+#define IRQ_SPI0		IRQ_SPI(66)
+#define IRQ_SPI1		IRQ_SPI(67)
+#define IRQ_SPI2		IRQ_SPI(68)
 
 #define IRQ_USB_HOST		IRQ_SPI(70)
 #define IRQ_USB_HSOTG		IRQ_SPI(71)
arch/arm/mach-exynos/include/mach/map.h +7 -0
index 03e2c99..64dca73 100644
@@ -88,6 +88,10 @@
 #define EXYNOS4_PA_SYSMMU_TV		0x12E20000
 #define EXYNOS4_PA_SYSMMU_MFC_L		0x13620000
 #define EXYNOS4_PA_SYSMMU_MFC_R		0x13630000
+#define EXYNOS4_PA_SPI0			0x13920000
+#define EXYNOS4_PA_SPI1			0x13930000
+#define EXYNOS4_PA_SPI2			0x13940000
+
 
 #define EXYNOS4_PA_GPIO1		0x11400000
 #define EXYNOS4_PA_GPIO2		0x11000000

@@ -149,6 +153,9 @@
 #define S3C_PA_RTC			EXYNOS4_PA_RTC
 #define S3C_PA_WDT			EXYNOS4_PA_WATCHDOG
 #define S3C_PA_UART			EXYNOS4_PA_UART
+#define S3C_PA_SPI0			EXYNOS4_PA_SPI0
+#define S3C_PA_SPI1			EXYNOS4_PA_SPI1
+#define S3C_PA_SPI2			EXYNOS4_PA_SPI2
 
 #define S5P_PA_CHIPID			EXYNOS4_PA_CHIPID
 #define S5P_PA_EHCI			EXYNOS4_PA_EHCI
arch/arm/mach-exynos/include/mach/spi-clocks.h new file +17 -0
new file mode 100644
index 0000000..9774389
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
+ *
+ * Copyright (C) 2011 Samsung Electronics Co. Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_SPI_CLKS_H
+#define __ASM_ARCH_SPI_CLKS_H __FILE__
+
+/* Must source from SCLK_SPI */
+#define EXYNOS4_SPI_SRCCLK_SCLK		0
+
+#endif /* __ASM_ARCH_SPI_CLKS_H */
+
arch/arm/mach-exynos/setup-spi.c new file +72 -0

72 lines not on this page · raw message

Signature · 1 line
1.7.0.4
#1 lore raw

PATCH v3 1/1 ARM: EXYNOS4: Modified files for SPI consolidation work

Hi Padma,

Some minor nitpicks ...

Quoted 7 lines · Padmavathi Venna

As SPI platform devices are consolidated to plat-samsung, some corresponding changes are required in the respective machine folder. Setup files are added for SPI GPIO configurations and platform data initialization.

Signed-off-by Padmavathi Venna<[email protected]>

---

[snip]

arch/arm/mach-exynos/clock.c static struct clksrc_clk clk_sclk_mmc3 = { · line 1240

Quoted 4 lines
arch/arm/mach-exynos/clock.c +4 -0
+static struct clksrc_clk clk_sclk_spi0 = {
+	.clk		= {
+		.name		= "sclk_spi",
+		.devname		= "s3c64xx-spi.0",

Single TAB would align properly.

+ .devname = "s3c64xx-spi.0",

Review

Quoted 2 lines
(quoted diff) +2 -0
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit		= (1<<  16),

+ .ctrlbit = (1 << 16),

arch/arm/mach-exynos/clock.c static struct clksrc_clk clk_sclk_mmc3 = { · line 1252

Quoted 10 lines
arch/arm/mach-exynos/clock.c +10 -0
+	},
+	.sources =&clkset_group,
+	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi1 = {
+	.clk		= {
+		.name		= "sclk_spi",
+		.devname		= "s3c64xx-spi.1",

+ .devname = "s3c64xx-spi.1",

Review

Quoted 2 lines
(quoted diff) +2 -0
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit		= (1<<  20),

+ .ctrlbit = (1 << 20),

arch/arm/mach-exynos/clock.c static struct clksrc_clk clk_sclk_mmc3 = { · line 1264

Quoted 10 lines
arch/arm/mach-exynos/clock.c +10 -0
+	},
+	.sources =&clkset_group,
+	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+	.reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk clk_sclk_spi2 = {
+	.clk		= {
+		.name		= "sclk_spi",
+		.devname		= "s3c64xx-spi.2",

+ .devname = "s3c64xx-spi.2",

Review

Quoted 2 lines
(quoted diff) +2 -0
+		.enable		= exynos4_clksrc_mask_peril1_ctrl,
+		.ctrlbit		= (1<<  24),

+ .ctrlbit = (1 << 24),

Quoted 5 lines
arch/arm/mach-exynos/clock.c +5 -0
+	},
+	.sources =&clkset_group,
+	.reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+	.reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};

[ snip ]

arch/arm/mach-exynos/setup-spi.c line 31

Quoted 6 lines
arch/arm/mach-exynos/setup-spi.c new file +6 -0
+int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
+			      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

                           ^^^^

TAB instead of SPACE for indenting?

+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

arch/arm/mach-exynos/setup-spi.c line 50

Quoted 6 lines
arch/arm/mach-exynos/setup-spi.c new file +6 -0
+int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
+			      S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

			^^^^

Ditto.

+ S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);

arch/arm/mach-exynos/setup-spi.c line 69

Quoted 11 lines
arch/arm/mach-exynos/setup-spi.c new file +9 -0
+	return 0;
+}
+#endif
 
 
+int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+{
+	s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
+	s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
+			      S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);

			^^^^

Ditto.

+ S3C_GPIO_SFN(5), S3C_GPIO_PULL_UP);

Quoted 3 lines
arch/arm/mach-exynos/setup-spi.c new file +3 -0
+	return 0;
+}
+#endif
Signature · 1 line
Tushar Behera