powerpc/83xx/km: update SDRAM parameters for km8321 boards
PATCH 1/4 powerpc/83xx/km: update SDRAM parameters for km8321 boards
From: Marco Schmid <[email protected]>
Measurements during HW basic test showed, that the SDRAM timing has to be optimized. This patch adapted these timings accordingly.
--- include/configs/km/km8321-common.h | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-)
include/configs/km/km8321-common.h +14 -10
@@ -70,7 +70,8 @@#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN) + SDRAM_CFG_SREN | \ + SDRAM_CFG_HSE)#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
@@ -82,7 +83,7 @@ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_MODE 0x47860252 +#define CONFIG_SYS_DDR_MODE 0x47860242#define CONFIG_SYS_DDR_MODE2 0x8080c000#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
@@ -94,20 +95,20 @@ (0 << TIMING_CFG0_WRT_SHIFT) | \ (0 << TIMING_CFG0_RWT_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ +#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ (2 << TIMING_CFG1_WRTORD_SHIFT) | \ (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (2 << TIMING_CFG1_WRREC_SHIFT) | \ - (6 << TIMING_CFG1_REFREC_SHIFT) | \ - (2 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (2 << TIMING_CFG1_PRETOACT_SHIFT)) + (3 << TIMING_CFG1_WRREC_SHIFT) | \ + (7 << TIMING_CFG1_REFREC_SHIFT) | \ + (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ + (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + (3 << TIMING_CFG1_PRETOACT_SHIFT))#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ (5 << TIMING_CFG2_CPO_SHIFT))
@@ -122,7 +123,10 @@/* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP 0x80000000 +#define CONFIG_SYS_LCRR_EADC 0x00010000 +#define CONFIG_SYS_LCRR_CLKDIV 0x00000002 +#define CONFIG_SYS_LBC_LBCR 0x00000000/*
Signature · 1 line
1.7.1
PATCH 2/4 powerpc/83xx/km: remove obsolete defines for tuda1
CONFIG_SYS_LCRR is unused and CONFIG_SYS_LBC_LBCR is already defined in the common header file, so remove them.
--- include/configs/tuda1.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-)
include/configs/tuda1.h +0 -6
@@ -41,12 +41,6 @@#define CONFIG_SYS_APP2_SIZE 256/* Megabytes */ /* -* Local Bus Configuration & Clock Setup -*/ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) -#define CONFIG_SYS_LBC_LBCR 0x00000000 - -/* * Init Local Bus Memory Controller: * * Bank Bus Machine PortSz Size Device
Signature · 1 line
1.7.1
PATCH 2/4 powerpc/83xx/km: remove obsolete defines for tuda1
Hello Holger,
Quoted 9 lines · Holger Brunck
CONFIG_SYS_LCRRis unused andCONFIG_SYS_LBC_LBCRis already defined in the common header file, so remove them.Signed-off-by Holger Brunck <[email protected]>cc Kim Phillips <[email protected]>cc Valentin Longchamp <[email protected]>--- include/configs/tuda1.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-)
bye,
Heiko
Signature · 2 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
PATCH 3/4 powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
In reply to Holger BrunckThese boards are from a u-boot point of view identical. So collect the two headerfiles to one, to decrease maintenance.
---
MAINTAINERS | 5 +-
boards.cfg | 3 +-
include/configs/tuxa1.h | 123 ----------------------------------
include/configs/{tuda1.h => tuxx1.h} | 23 +++---
4 files changed, 16 insertions(+), 138 deletions(-)
delete mode 100644 include/configs/tuxa1.h
rename include/configs/{tuda1.h => tuxx1.h} (84%)MAINTAINERS +3 -2
@@ -436,11 +436,12 @@ Heiko Schocher <[email protected]> municse MPC5200 sc3 PPC405GP suvd3 MPC8321 - tuda1 MPC8321 - tuxa1 MPC8321 uc101 MPC5200 ve8313 MPC8313 +Holger Brunck <[email protected]> + tuxx1 MPC8321 + Peter De Schrijver <[email protected]> ML2 PPC4xx
boards.cfg +1 -2
@@ -590,8 +590,7 @@ MPC837XERDB powerpc mpc83xx mpc837xerdb freesca kmeter1 powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile suvd3 powerpc mpc83xx km83xx keymile -tuda1 powerpc mpc83xx km83xx keymile -tuxa1 powerpc mpc83xx km83xx keymile +tuxx1 powerpc mpc83xx km83xx keymile MERGERBOX powerpc mpc83xx mergerbox matrix_vision MVBLM7 powerpc mpc83xx mvblm7 matrix_vision SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
include/configs/tuxa1.h deleted +0 -123
123 lines not on this page · raw message
include/configs/tuxx1.h renamed from include/configs/tuda1.h +12 -11
@@ -13,6 +13,7 @@* * (C) Copyright 2010-2011 * Lukas Roggli, KEYMILE Ltd, lukas.roggli at keymile.com +* Holger Brunck, Keymile GmbH, holger.bruncl at keymile.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as
@@ -26,9 +27,9 @@/* * High Level Configuration Options */ -#define CONFIG_TUDA1 /* TUDA1 board specific */ -#define CONFIG_HOSTNAME tuda1 -#define CONFIG_KM_BOARD_NAME "tuda1" +#define CONFIG_TUXXX /* TUXX1 board specific */ +#define CONFIG_HOSTNAME tuxx1 +#define CONFIG_KM_BOARD_NAME "tuxx1"#define CONFIG_SYS_TEXT_BASE 0xF0000000
@@ -43,15 +44,15 @@/* * Init Local Bus Memory Controller: * -* Bank Bus Machine PortSz Size Device -* ---- --- ------- ------ ----- ------ -* 2 Local GPCM 8 bit 256MB PAXG -* 3 Local GPCM 8 bit 256MB PINC3 +* Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 +* ---- --- ------- ------ ----- --------------------- +* 2 Local GPCM 8 bit 256MB PAXG LPXF +* 3 Local GPCM 8 bit 256MB PINC3 PINC2 * */ /* -* PAXG on the local bus CS2 +* Configuration for C2 on the local bus */ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE
@@ -71,7 +72,7 @@ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD)/* -* PINC3 on the local bus CS3 +* Configuration for C3 on the local bus */ /* Access window base at PINC3 base */ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE
@@ -97,7 +98,7 @@/* * MMU Setup */ -/* PAXG: icache cacheable, but dcache-inhibit and guarded */ +/* APP1: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ BATL_PP_RW | \ BATL_MEMCOHERENCE)
@@ -112,7 +113,7 @@ BATL_GUARDEDSTORAGE)#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -/* PINC3: icache cacheable, but dcache-inhibit and guarded */ +/* APP2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ BATL_PP_RW | \ BATL_MEMCOHERENCE)
Signature · 1 line
1.7.1
PATCH 3/4 powerpc/83xx/km: merge tuxa and tuda1 boards to tuxx1
Hello Holger,
Quoted 7 lines · Holger Brunck
These boards are from a u-boot point of view identical. So collect the two headerfiles to one, to decrease maintenance.
Signed-off-by Holger Brunck <[email protected]>cc Kim Phillips <[email protected]>cc Valentin Longchamp <[email protected]>cc Heiko Schocher <[email protected]>
Quoted 8 lines
---
MAINTAINERS | 5 +-
boards.cfg | 3 +-
include/configs/tuxa1.h | 123 ----------------------------------
include/configs/{tuda1.h => tuxx1.h} | 23 +++---
4 files changed, 16 insertions(+), 138 deletions(-)
delete mode 100644 include/configs/tuxa1.h
rename include/configs/{tuda1.h => tuxx1.h} (84%)bye,
Heiko
Signature · 2 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
PATCH 4/4 powerpc/83xx/km: add support for 8321 based tuge1 board
In reply to Holger BrunckThis board is similar to our tuxx1 target. But on this board there is only one application specific chip select configured.
--- MAINTAINERS | 1 + boards.cfg | 1 + include/configs/tuxx1.h | 24 +++++++++++++++++++----- 3 files changed, 21 insertions(+), 5 deletions(-)
MAINTAINERS +1 -0
@@ -440,6 +440,7 @@ Heiko Schocher <[email protected]> ve8313 MPC8313 Holger Brunck <[email protected]> + tuge1 MPC8321 tuxx1 MPC8321 Peter De Schrijver <[email protected]>
boards.cfg +1 -0
@@ -590,6 +590,7 @@ MPC837XERDB powerpc mpc83xx mpc837xerdb freesca kmeter1 powerpc mpc83xx km83xx keymile kmsupx5 powerpc mpc83xx km83xx keymile suvd3 powerpc mpc83xx km83xx keymile +tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2 tuxx1 powerpc mpc83xx km83xx keymile MERGERBOX powerpc mpc83xx mergerbox matrix_vision MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
include/configs/tuxx1.h +19 -5
@@ -27,9 +27,13 @@/* * High Level Configuration Options */ -#define CONFIG_TUXXX /* TUXX1 board specific */ +#define CONFIG_TUXXX /* TUXX1 board (tuxa1/tuda1) specific */ #define CONFIG_HOSTNAME tuxx1 +#ifdef CONFIG_KM_DISABLE_APP2 +#define CONFIG_KM_BOARD_NAME "tuge1" +#else #define CONFIG_KM_BOARD_NAME "tuxx1" +#endif #define CONFIG_SYS_TEXT_BASE 0xF0000000
@@ -38,16 +42,18 @@#define CONFIG_SYS_APP1_BASE 0xA0000000/* PAXG */ #define CONFIG_SYS_APP1_SIZE 256/* Megabytes */ +#ifndef CONFIG_KM_DISABLE_APP2 #define CONFIG_SYS_APP2_BASE 0xB0000000/* PINC3 */ #define CONFIG_SYS_APP2_SIZE 256/* Megabytes */ +#endif /* * Init Local Bus Memory Controller: * -* Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 -* ---- --- ------- ------ ----- --------------------- -* 2 Local GPCM 8 bit 256MB PAXG LPXF -* 3 Local GPCM 8 bit 256MB PINC3 PINC2 +* Bank Bus Machine PortSz Size Device on TUDA1 TUXA1 TUGE1 +* ---- --- ------- ------ ----- ---------------------------- +* 2 Local GPCM 8 bit 256MB PAXG LPXF PAXI +* 3 Local GPCM 8 bit 256MB PINC3 PINC2 unused * */
@@ -71,6 +77,7 @@ OR_GPCM_TRLX_SET | \ OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) +#ifndef CONFIG_KM_DISABLE_APP2 /* * Configuration for C3 on the local bus */
@@ -94,6 +101,7 @@#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ MxMR_WLFx_2X) +#endif /* * MMU Setup
@@ -113,6 +121,11 @@ BATL_GUARDEDSTORAGE)#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#ifdef CONFIG_KM_DISABLE_APP2 +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#else /* APP2: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ BATL_PP_RW | \
@@ -125,6 +138,7 @@ BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) +#endif #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U#define CONFIG_SYS_IBAT7L (0)
Signature · 1 line
1.7.1
PATCH 4/4 powerpc/83xx/km: add support for 8321 based tuge1 board
Hello Holger,
Quoted 7 lines · Holger Brunck
This board is similar to our tuxx1 target. But on this board there is only one application specific chip select configured.
Signed-off-by Holger Brunck <[email protected]>cc Kim Phillips <[email protected]>cc Valentin Longchamp <[email protected]>cc Heiko Schocher <[email protected]>
Quoted 5 lines
--- MAINTAINERS | 1 + boards.cfg | 1 + include/configs/tuxx1.h | 24 +++++++++++++++++++----- 3 files changed, 21 insertions(+), 5 deletions(-)
bye,
Heiko
Signature · 2 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
PATCH 1/4 powerpc/83xx/km: update SDRAM parameters for km8321 boards
In reply to Holger BrunckHello Holger,
Quoted 5 lines · Holger Brunck
From: Marco Schmid <[email protected]>
Measurements during HW basic test showed, that the SDRAM timing has to be optimized. This patch adapted these timings accordingly.
Quoted 7 lines
Signed-off-by Marco Schmid <[email protected]>Signed-off-by Holger Brunck <[email protected]>cc Kim Phillips <[email protected]>cc Valentin Longchamp <[email protected]>--- include/configs/km/km8321-common.h | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-)
bye,
Heiko
Signature · 2 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
PATCH 1/4 powerpc/83xx/km: update SDRAM parameters for km8321 boards
In reply to Holger BrunckQuoted 10 lines · On Wed, 14 Dec 2011 16:21:42 +0100 Holger Brunck <[email protected]>…
From: Marco Schmid <[email protected]>
Measurements during HW basic test showed, that the SDRAM timing has to be optimized. This patch adapted these timings accordingly.
Signed-off-by Marco Schmid <[email protected]>Signed-off-by Holger Brunck <[email protected]>cc Kim Phillips <[email protected]>cc Valentin Longchamp <[email protected]>---
applied 1-4 out of 4 patches to mpc83xx.
Thanks,
Kim