i.mx6q: Add the ethernet function support

PATCH New Jason Liu 3 participants 9 messages Dec 16, 2011 – Dec 19, 2011

Subsystems (2)

Network drivers Arm (32-bit)

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Jason Liu

author

2011-12-16 15:17 UTC #0 lore raw

v2 cover i.mx6q: Add the ethernet function support

This patch add the ethernet function support for i.mx6q/arm2 board.

The patch has been tested ok by: Dirk Behme <[email protected]> on freescale i.mx6qarm2 board.

Jason Liu (3):
i.mx: i.mx6q: Add the enet clock function
fec: add the i.mx6q enet driver support
i.mx6q: arm2: Add the enet function support

 arch/arm/cpu/armv7/mx6/clock.c      |    5 ++
 board/freescale/mx6qarm2/mx6qarm2.c |   90 +++++++++++++++++++++++++++++++++++
 drivers/net/fec_mxc.c               |   10 ++++
 drivers/net/fec_mxc.h               |    7 ++-
 include/configs/mx6qarm2.h          |   12 ++++-
 5 files changed, 121 insertions(+), 3 deletions(-)

Signature · 1 line

1.7.4.1

Jason Liu

author

2011-12-16 15:17 UTC #1 lore raw

PATCH v2 1/3 i.mx: i.mx6q: Add the enet clock function

Cc Stefano Babic <[email protected]>

Signed-off-by Jason Liu <[email protected]>

Acked-by Stefano Babic <[email protected]>

---
v2: Add Stefano's ack

---
 arch/arm/cpu/armv7/mx6/clock.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/mx6/clock.c +5 -0

index b143535..fa3a124 100644
@@ -285,6 +285,11 @@ u32 imx_get_uartclk(void)
 	return get_uart_clk();
 }
 
+u32 imx_get_fecclk(void)
+{
+	return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {

Signature · 1 line

1.7.4.1

Stefano Babic

2011-12-16 16:21 UTC #2 lore raw

PATCH v2 1/3 i.mx: i.mx6q: Add the enet clock function

Quoted 6 lines · Jason Liu

Cc Stefano Babic <[email protected]>
Signed-off-by Jason Liu <[email protected]>
Acked-by Stefano Babic <[email protected]>
---
v2: Add Stefano's ack

Jason,

if you prefer it is not required to send a new version with only the ACK. Patchworks has already applied my ACK to the previous patch.

Howerver, nothing against if it is better for you to repost the whole patchset.

Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Stefano Babic

2011-12-19 06:45 UTC #3 lore raw

PATCH v2 1/3 i.mx: i.mx6q: Add the enet clock function

In reply to Jason Liu

Quoted 7 lines · Jason Liu

Cc Stefano Babic <[email protected]>
Signed-off-by Jason Liu <[email protected]>
Acked-by Stefano Babic <[email protected]>
---
v2: Add Stefano's ack
---

Applied to u-boot-imx, next branch, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Jason Liu

author

2011-12-16 15:17 UTC #4 lore raw

PATCH v2 2/3 fec: add the i.mx6q enet driver support

In reply to Jason Liu

Cc Stefano Babic <[email protected]>

Signed-off-by Jason Liu <[email protected]>

Acked-by Stefano Babic <[email protected]>

---
v2: Add Stefano's ack

---
 drivers/net/fec_mxc.c |   10 ++++++++++
 drivers/net/fec_mxc.h |    7 ++++++-
 2 files changed, 16 insertions(+), 1 deletions(-)

drivers/net/fec_mxc.c +10 -0

index b05a4c0..3affda8 100644
@@ -384,6 +384,14 @@ static int fec_open(struct eth_device *edev)
 	writel(1 << 2, &fec->eth->x_cntrl);
 	fec->rbd_index = 0;
 
+#if defined(CONFIG_MX6Q)
+	/* Enable ENET HW endian SWAP */
+	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
+		&fec->eth->ecntrl);
+	/* Enable ENET store and forward mode */
+	writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
+		&fec->eth->x_wmrk);
+#endif
 	/*
 	 * Enable FEC-Lite controller
 	 */

@@ -485,6 +493,8 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
 	if (fec->xcv_type == SEVENWIRE)
 		rcntrl |= FEC_RCNTRL_FCE;
+	else if (fec->xcv_type == RGMII)
+		rcntrl |= FEC_RCNTRL_RGMII;
 	else if (fec->xcv_type == RMII)
 		rcntrl |= FEC_RCNTRL_RMII;
 	else	/* MII mode */

drivers/net/fec_mxc.h +6 -1

index 8b26645..39337bf 100644
@@ -196,6 +196,7 @@ struct ethernet_regs {
 #define FEC_RCNTRL_PROM			0x00000008
 #define FEC_RCNTRL_BC_REJ		0x00000010
 #define FEC_RCNTRL_FCE			0x00000020
+#define FEC_RCNTRL_RGMII		0x00000040
 #define FEC_RCNTRL_RMII			0x00000100
 
 #define FEC_TCNTRL_GTS			0x00000001

@@ -206,6 +207,9 @@ struct ethernet_regs {
 
 #define FEC_ECNTRL_RESET		0x00000001	/* reset the FEC */
 #define FEC_ECNTRL_ETHER_EN		0x00000002	/* enable the FEC */
+#define FEC_ECNTRL_DBSWAP		0x00000100
+
+#define FEC_X_WMRK_STRFWD		0x00000100
 
 #if defined(CONFIG_MX25) || defined(CONFIG_MX53)
 /* defines for MIIGSK */

@@ -261,7 +265,8 @@ enum xceiver_type {
 	SEVENWIRE,	/* 7-wire       */
 	MII10,		/* MII 10Mbps   */
 	MII100,		/* MII 100Mbps  */
-	RMII		/* RMII */
+	RMII,		/* RMII */
+	RGMII,		/* RGMII */
 };
 
 /**

Signature · 1 line

1.7.4.1

Stefano Babic

2011-12-19 06:45 UTC #5 lore raw

PATCH v2 2/3 fec: add the i.mx6q enet driver support

Quoted 4 lines · Jason Liu

Cc Stefano Babic <[email protected]>
Signed-off-by Jason Liu <[email protected]>
Acked-by Stefano Babic <[email protected]>

Applied to u-boot-imx, next branch, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Jason Liu

author

2011-12-16 15:17 UTC #6 lore raw

PATCH v2 3/3 i.mx6q: arm2: Add the enet function support

In reply to Jason Liu

This enable the network function on the i.mx6q armadillo2 board(arm2), thus we can use tftp to load image from network.

Cc Stefano Babic <[email protected]>

Signed-off-by Jason Liu <[email protected]>

Tested-by Dirk Behme <[email protected]>

---
v2: use constant define and remove ETHPRIME config

---
 board/freescale/mx6qarm2/mx6qarm2.c |   90 +++++++++++++++++++++++++++++++++++
 include/configs/mx6qarm2.h          |   12 ++++-
 2 files changed, 100 insertions(+), 2 deletions(-)

board/freescale/mx6qarm2/mx6qarm2.c +90 -0

index 89e0e76..9894245 100644
@@ -29,6 +29,8 @@
 #include <asm/gpio.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -40,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

@@ -79,11 +85,35 @@ iomux_v3_cfg_t usdhc4_pads[] = {
 	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
+iomux_v3_cfg_t enet_pads[] = {
+	MX6Q_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC3_BASE_ADDR, 1},

@@ -132,9 +162,69 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#define MII_MMD_ACCESS_CTRL_REG		0xd
+#define MII_MMD_ACCESS_ADDR_DATA_REG	0xe
+#define MII_DBG_PORT_REG		0x1d
+#define MII_DBG_PORT2_REG		0x1e
+
+int fecmxc_mii_postcall(int phy)
+{
+	unsigned short val;
+
+	/*
+	 * Due to the i.MX6Q Armadillo2 board HW design,there is
+	 * no 125Mhz clock input from SOC. In order to use RGMII,
+	 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
+	 */
+	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
+	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
+	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
+	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
+	val &= 0xffe3;
+	val |= 0x18;
+	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
+
+	/* For the RGMII phy, we need enable tx clock delay */
+	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
+	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
+	val |= 0x0100;
+	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
+
+	miiphy_write("FEC", phy, MII_BMCR, 0xa100);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+	if (ret) {
+		printf("FEC MXC: %s:failed\n", __func__);
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC");
+	if (!dev) {
+		printf("FEC MXC: Unable to get FEC device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		printf("FEC MXC: Unable to register FEC mii postcall\n");
+		return ret;
+	}
+
+	return 0;
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+	setup_iomux_enet();
 
 	return 0;
 }

include/configs/mx6qarm2.h +10 -2

index a7b363d..124a7a6 100644
@@ -56,6 +56,16 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define	CONFIG_FEC_MXC
+#define	CONFIG_MII
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define	CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1

@@ -66,8 +76,6 @@
 #include <config_cmd_default.h>
 
 #undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
 
 #define CONFIG_BOOTDELAY		3

Signature · 1 line

1.7.4.1

Marek Vasut

2011-12-17 03:13 UTC #7 lore raw

PATCH v2 3/3 i.mx6q: arm2: Add the enet function support

Quoted 89 lines

This enable the network function on the i.mx6q armadillo2 board(arm2), thus we can use tftp to load image from network.

Cc Stefano Babic <[email protected]>

Signed-off-by Jason Liu <[email protected]>

Tested-by Dirk Behme <[email protected]>

---
v2: use constant define and remove ETHPRIME config

---
 board/freescale/mx6qarm2/mx6qarm2.c |   90
+++++++++++++++++++++++++++++++++++ include/configs/mx6qarm2.h          | 
 12 ++++-
 2 files changed, 100 insertions(+), 2 deletions(-)

(quoted diff) +0 -0

b/board/freescale/mx6qarm2/mx6qarm2.c index 89e0e76..9894245 100644

board/freescale/mx6qarm2/mx6qarm2.c +40 -0

@@ -29,6 +29,8 @@
 #include <asm/gpio.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -40,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
 	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

@@ -79,11 +85,35 @@ iomux_v3_cfg_t usdhc4_pads[] = {
 	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
+iomux_v3_cfg_t enet_pads[] = {
+	MX6Q_PAD_KEY_COL1__ENET_MDIO        | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_KEY_COL2__ENET_MDC         | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC3_BASE_ADDR, 1},

@@ -132,9 +162,69 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
+#define MII_MMD_ACCESS_CTRL_REG		0xd
+#define MII_MMD_ACCESS_ADDR_DATA_REG	0xe
+#define MII_DBG_PORT_REG		0x1d
+#define MII_DBG_PORT2_REG		0x1e
+
+int fecmxc_mii_postcall(int phy)
+{
+	unsigned short val;
+
+	/*

board/freescale/mx6qarm2/mx6qarm2.c int board_mmc_init(bd_t *bis) · line 184

Quoted 10 lines

board/freescale/mx6qarm2/mx6qarm2.c +10 -0

+	 * Due to the i.MX6Q Armadillo2 board HW design,there is
+	 * no 125Mhz clock input from SOC. In order to use RGMII,
+	 * We need enable AR8031 ouput a 125MHz clk from CLK_25M
+	 */
+	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7);
+	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016);
+	miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007);
+	miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val);
+	val &= 0xffe3;
+	val |= 0x18;

Magic.

Quoted 51 lines

board/freescale/mx6qarm2/mx6qarm2.c +40 -0

+	miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val);
+
+	/* For the RGMII phy, we need enable tx clock delay */
+	miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5);
+	miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val);
+	val |= 0x0100;
+	miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val);
+
+	miiphy_write("FEC", phy, MII_BMCR, 0xa100);
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	struct eth_device *dev;
+	int ret;
+
+	ret = cpu_eth_init(bis);
+	if (ret) {
+		printf("FEC MXC: %s:failed\n", __func__);
+		return ret;
+	}
+
+	dev = eth_get_dev_by_name("FEC");
+	if (!dev) {
+		printf("FEC MXC: Unable to get FEC device entry\n");
+		return -EINVAL;
+	}
+
+	ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall);
+	if (ret) {
+		printf("FEC MXC: Unable to register FEC mii postcall\n");
+		return ret;
+	}
+
+	return 0;
+}
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+	setup_iomux_enet();
 
 	return 0;
 }

include/configs/mx6qarm2.h +0 -0

index a7b363d..124a7a6 100644

include/configs/mx6qarm2.h line 64

Quoted 9 lines

include/configs/mx6qarm2.h +6 -0

@@ -56,6 +56,16 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define	CONFIG_FEC_MXC
+#define	CONFIG_MII

Indent.

Quoted 15 lines

include/configs/mx6qarm2.h +4 -2

+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define	CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_FEC_MXC_PHYADDR		0
+
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_CONS_INDEX		1

@@ -66,8 +76,6 @@
 #include <config_cmd_default.h>
 
 #undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
 
 #define CONFIG_BOOTDELAY		3

Stefano Babic

2011-12-19 06:45 UTC #8 lore raw

PATCH v2 3/3 i.mx6q: arm2: Add the enet function support

In reply to Jason Liu

Quoted 8 lines · Jason Liu

This enable the network function on the i.mx6q armadillo2 board(arm2), thus we can use tftp to load image from network.
Cc Stefano Babic <[email protected]>
Signed-off-by Jason Liu <[email protected]>
Tested-by Dirk Behme <[email protected]>
---

Applied to u-boot-imx, next branch, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
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