Added SPL support

index 2d6d359..78db3a5 100644
@@ -26,7 +26,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * early system init of muxing and clocks.

@@ -55,12 +55,12 @@ void s_init(u32 in_ddr)
 void init_timer(void)
 {
 	/* Reset the Timer */
-	writel(0x2, (&timerreg->tsicrreg));
+	writel(0x2, (&timer_base->tscir));
 
 	/* Wait until the reset is done */
-	while (readl(&timerreg->tiocpcfgreg) & 1)
+	while (readl(&timer_base->tiocp_cfg) & 1)
 		;
 
 	/* Start the Timer */
-	writel(0x1, (&timerreg->tclrreg));
+	writel(0x1, (&timer_base->tclr));
 }

index 4ca6c45..7070e7d 100644
@@ -101,6 +101,9 @@ static void enable_per_clocks(void)
 	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 		;
 
+	/* Select the Master osc 24 MHZ as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
+
 	/* UART0 */
 	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)

76 lines not on this page · raw message

index 9638b4c..ba6b59b 100644
@@ -76,7 +76,7 @@ struct emif_regs {
 	unsigned int sdrmcsr;		/* offset 0x3C */
 	unsigned int res2[8];
 	unsigned int sdritr;		/* offset 0x60 */
-	unsigned int res3[20];
+	unsigned int res3[32];
 	unsigned int ddrphycr;		/* offset 0xE4 */
 	unsigned int ddrphycsr;		/* offset 0xE8 */
 	unsigned int ddrphycr2;		/* offset 0xEC */

@@ -161,10 +161,10 @@ struct ddr_regs {
 	unsigned int dt0wiratio1;	/* offset 0x0F4 */
 	unsigned int dt0giratio0;	/* offset 0x0FC */
 	unsigned int dt0giratio1;	/* offset 0x100 */
-	unsigned int resv6[2];
+	unsigned int resv6[1];
 	unsigned int dt0fwsratio0;	/* offset 0x108 */
 	unsigned int dt0fwsratio1;	/* offset 0x10C */
-	unsigned int resv7[5];
+	unsigned int resv7[4];
 	unsigned int dt0wrsratio0;	/* offset 0x120 */
 	unsigned int dt0wrsratio1;	/* offset 0x124 */
 	unsigned int resv8[3];

index 1e265c6..09ed650 100644
@@ -20,13 +20,6 @@
 #define _SYS_PROTO_H_
 
 #define BOARD_REV_ID	0x0
-struct {
-	u32 board_type_v1;
-	u32 board_type_v2;
-	u32 mtype;
-	char *board_string;
-	char *nand_string;
-} board_sysinfo;
 
 u32 get_cpu_rev(void);
 u32 get_sysboot_value(void);

index b471c9b..2a61ef0 100644
@@ -17,6 +17,7 @@
 #define __CONFIG_AM335X_EVM_H
 
 #define CONFIG_AM335X
+#define CONFIG_AM33XX
 #define CONFIG_CMD_MEMORY	/* for mtest */
 #undef CONFIG_GZIP
 #undef CONFIG_ZLIB

@@ -30,7 +31,7 @@
 #define CONFIG_AM335X_CONFIG_DDR
 #define CONFIG_ENV_SIZE			0x400
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 * 1024))
-#define CONFIG_SYS_PROMPT		"AM335X# "
+#define CONFIG_SYS_PROMPT		"U-Boot# "
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
 

@@ -47,14 +48,12 @@
 
 /* Clock Defines */
 #define V_OSCK				24000000  /* Clock output from T2 */
-#define V_SCLK				(V_OSCK >> 1)
+#define V_SCLK				(V_OSCK)
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for
-						   initial data */
 #define CONFIG_CMD_ECHO
 
 /* max number of command args */
-#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_MAXARGS		16
 
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		512

@@ -74,7 +73,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
 					+ (8 * 1024 * 1024))
 
-#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
 #define CONFIG_SYS_HZ			1000 /* 1ms clock */
 

@@ -88,7 +86,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 						GENERATED_GBL_DATA_SIZE)
  /* Platform/Board specific defs */
-#define CONFIG_SYS_CLK_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_HZ			1000

@@ -99,7 +96,6 @@
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		(48000000)
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM4		0x481A6000	/* UART3 on IA BOard */
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \

index 78db3a5..312643c 100644
@@ -64,3 +64,10 @@ void init_timer(void)
 	/* Start the Timer */
 	writel(0x1, (&timer_base->tclr));
 }
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif

index 7070e7d..98cfd93 100644
@@ -108,6 +108,11 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
+
+	/* MMC0*/
+	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
+	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
+		;
 }
 
 static void mpu_pll_config(void)

164 lines not on this page · raw message

index 8f27409..df11752 100644
@@ -258,6 +258,20 @@ static struct module_pin_mux uart0_pin_mux[] = {
 	{-1},
 };
 
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
 /*
  * Configure the pin mux for the module
  */

@@ -276,3 +290,9 @@ void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
 }
+
+
+void enable_mmc0_pin_mux(void)
+{
+	configure_module_pin_mux(mmc0_pin_mux);
+}

index ef12ecd..6603501 100644
@@ -28,6 +28,7 @@
 #include <part.h>
 #include <i2c.h>
 #include <twl4030.h>
+#include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>

index 2a61ef0..086d4ef 100644
@@ -76,6 +76,15 @@
 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
 #define CONFIG_SYS_HZ			1000 /* 1ms clock */
 
+#define CONFIG_MMC
+#define CONFIG_AM335X_HSMMC_BASE	0x48060100
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
  /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
 #define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */

index 312643c..647edaa 100644
@@ -21,17 +21,52 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/common_def.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
+struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
+
+#ifdef CONFIG_SPL_BUILD
+u32 am33xx_boot_device = BOOT_DEVICE_MMC1;
+
+u32 omap_boot_device(void)
+{
+	return am33xx_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	switch (omap_boot_device()) {
+	case BOOT_DEVICE_MMC2:
+		return MMCSD_MODE_RAW;
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FAT;
+		break;
+	case BOOT_DEVICE_NAND:
+		return NAND_MODE_HW_ECC;
+		break;
+	default:
+		puts("spl: ERROR:  unknown device - can't select boot mode\n");
+		hang();
+	}
+}
+
+/* UART Defines */
+#define UART_RESET		(0x1 << 1)
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+#endif
 
 /*
  * early system init of muxing and clocks.
  */
-void s_init(u32 in_ddr)
+void s_init(void)
 {
 	/* WDT1 is already running when the bootloader gets control
 	 * Disable it to avoid "random" resets

@@ -43,12 +78,37 @@ void s_init(u32 in_ddr)
 	while (readl(&wdtimer->wdtwwps) != 0x0)
 		;
 
+#ifdef CONFIG_SPL_BUILD
 	/* Setup the PLLs and the clocks for the peripherals */
-#ifdef CONFIG_SETUP_PLL
 	pll_init();
+
+	/* UART softreset */
+	u32 regVal;
+
+	enable_uart0_pin_mux();
+
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_RESET;
+	writel(regVal, &uart_base->uartsyscfg);
+	while ((readl(&uart_base->uartsyssts) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	regVal = readl(&uart_base->uartsyscfg);
+	regVal |= UART_SMART_IDLE_EN;
+	writel(regVal, &uart_base->uartsyscfg);
+
+	/* Initialize the Timer */
+	init_timer();
+
+	preloader_console_init();
+
+	config_ddr();
 #endif
-	if (!in_ddr)
-		config_ddr();
+
+	/* Enable MMC0 */
+	enable_mmc0_pin_mux();
 }
 
 /* Initialize timer */

@@ -71,3 +131,9 @@ int board_mmc_init(bd_t *bis)
 	return omap_mmc_init(0);
 }
 #endif
+
+void setup_clocks_for_console(void)
+{
+	/* Not yet implemented */
+	return;
+}

index 1318365..2f4164d 100644
@@ -46,7 +46,7 @@ void dram_init_banksize(void)
 }
 
 
-#ifdef CONFIG_AM335X_CONFIG_DDR
+#ifdef CONFIG_SPL_BUILD
 static void data_macro_config(int dataMacroNum)
 {
 	struct ddr_data data;

index d177652..62688eb 100644
@@ -223,8 +223,9 @@ void board_init_r(gd_t *id, ulong dummy)
 	debug(">>spl:board_init_r()\n");
 
 	timer_init();
+#ifdef CONFIG_I2C
 	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
+#endif
 	boot_device = omap_boot_device();
 	debug("boot device - %d\n", boot_device);
 	switch (boot_device) {

@@ -249,6 +250,14 @@ void board_init_r(gd_t *id, ulong dummy)
 	}
 }
 
+void __omap_rev_string(char *str)
+{
+	sprintf(str, "Revision detection unimplemented");
+}
+
+void omap_rev_string(char *str)
+	__attribute__((weak, alias("__omap_rev_string")));
+
 void preloader_console_init(void)
 {
 	const char *u_boot_rev = U_BOOT_VERSION;

new file mode 100644
index 0000000..767932d
@@ -0,0 +1,22 @@
+/*
+ * common_def.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COMMON_DEF_H__
+#define __COMMON_DEF_H__
+
+extern void enable_uart0_pin_mux(void);
+extern void enable_mmc0_pin_mux(void);
+
+#endif/*__COMMON_DEF_H__ */

index 0ec22eb..aac2e48 100644
@@ -78,4 +78,9 @@
 #define DDRPHY_0_CONFIG_BASE		(CTRL_BASE + 0x1400)
 #define DDRPHY_CONFIG_BASE		DDRPHY_0_CONFIG_BASE
 
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+
 #endif /* __AM33XX_HARDWARE_H */

index 09ed650..6c58f1b 100644
@@ -29,4 +29,5 @@ int print_cpuinfo(void);
 #endif
 
 u32 get_device_type(void);
+void setup_clocks_for_console(void);
 #endif

index d3cb857..ef19d13 100644
@@ -39,16 +39,24 @@ void preloader_console_init(void);
 /* Boot device */
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1
+#if defined(CONFIG_OMAP54XX) || defined(CONFIG_OMAP44XX)
 #define BOOT_DEVICE_XIPWAIT	2
 #define BOOT_DEVICE_NAND	3
 #define BOOT_DEVICE_ONE_NAND	4
 #define BOOT_DEVICE_MMC1	5
 #define BOOT_DEVICE_MMC2	6
+#elif defined(CONFIG_AM33XX)	/* AM33XX */
+#define BOOT_DEVICE_NAND	5
+#define BOOT_DEVICE_MMC1	8
+#define BOOT_DEVICE_MMC2	0 /* eMMC, TODO */
+#define BOOT_DEVICE_UART	65
+#endif
 
 /* Boot type */
 #define	MMCSD_MODE_UNDEFINED	0
 #define MMCSD_MODE_RAW		1
 #define MMCSD_MODE_FAT		2
+#define NAND_MODE_HW_ECC	3
 
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);

deleted file mode 100644
index 1696d60..0000000
@@ -1,24 +0,0 @@
-/*
- * common_def.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __COMMON_DEF_H__
-#define __COMMON_DEF_H__
-
-extern void enable_uart0_pin_mux(void);
-extern void configure_evm_pin_mux(unsigned char daughter_board_id,
-					unsigned short daughter_board_profile,
-					unsigned char daughter_board_flag);
-
-#endif/*__COMMON_DEF_H__ */

index b4eddd8..6a9f788 100644
@@ -16,7 +16,7 @@
 #include <common.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
-#include "common_def.h"
+#include <asm/arch/common_def.h>
 #include <serial.h>
 
 DECLARE_GLOBAL_DATA_PTR;

index df11752..c2a61bd 100644
@@ -14,7 +14,7 @@
  */
 
 #include <config.h>
-#include "common_def.h"
+#include <asm/arch/common_def.h>
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 

index 086d4ef..020278c 100644
@@ -27,8 +27,6 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 
-#define CONFIG_SETUP_PLL
-#define CONFIG_AM335X_CONFIG_DDR
 #define CONFIG_ENV_SIZE			0x400
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 * 1024))
 #define CONFIG_SYS_PROMPT		"U-Boot# "

@@ -119,7 +117,42 @@
 
 #define CONFIG_ENV_IS_NOWHERE
 
-#define CONFIG_SYS_TEXT_BASE		0x402f0400
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_TEXT_BASE		0x402F0400
+#define CONFIG_SPL_MAX_SIZE		(46 * 1024)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+/*
+ * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
+ * 64 bytes before this address should be set aside for u-boot.img's
+ * header. That is 0x800FFFC0--0x80100000 should not be used for any
+ * other needs.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80800000
+#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+
+/* Since SPL did all of this for us, we don't need to do it twice. */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
 
 /* Unsupported features */
 #undef CONFIG_USE_IRQ