add nand spl boot for qi_lb60 board

PATCH Superseded Xiangfu Liu 4 participants 7 messages Jan 6, 2012 – Mar 6, 2012

Subsystems (3)

Memory technology devices (MTD) MIPS NAND flash

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Xiangfu Liu

author

2012-01-06 10:17 UTC #0 lore raw

PATCH v2 1/1 add nand spl boot for qi_lb60 board

Signed-off-by Xiangfu Liu <[email protected]>

---
 arch/mips/cpu/xburst/cpu.c           |    4 +
 arch/mips/cpu/xburst/start_spl.S     |   65 ++++++++++++++++++++
 drivers/mtd/nand/jz4740_nand.c       |   40 +++++++++++-
 include/configs/qi_lb60.h            |    3 +
 nand_spl/board/qi/qi_lb60/Makefile   |  112 ++++++++++++++++++++++++++++++++++
 nand_spl/board/qi/qi_lb60/nand_spl.c |   37 +++++++++++
 nand_spl/board/qi/qi_lb60/u-boot.lds |   63 +++++++++++++++++++
 7 files changed, 321 insertions(+), 3 deletions(-)
 create mode 100644 arch/mips/cpu/xburst/start_spl.S
 create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
 create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
 create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

arch/mips/cpu/xburst/cpu.c +4 -0

index e976341..afd166c 100644
@@ -42,6 +42,8 @@
 		:			\
 		: "i" (op), "R" (*(unsigned char *)(addr)))
 
+#ifndef CONFIG_NAND_SPL
+
 void __attribute__((weak)) _machine_restart(void)
 {
 	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;

@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 		cache_op(Hit_Invalidate_D, addr);
 }
 
+#endif
+
 void flush_icache_all(void)
 {
 	u32 addr, t = 0;

arch/mips/cpu/xburst/start_spl.S new file +65 -0

65 lines not on this page · raw message

drivers/mtd/nand/jz4740_nand.c +37 -3

index 3ec34f3..7ef07a5 100644
@@ -15,6 +15,10 @@
 #include <asm/io.h>
 #include <asm/jz4740.h>
 
+#ifdef CONFIG_NAND_SPL
+  #define printf(arg...) do {} while (0)
+#endif
+
 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)

@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		for (k = 0; k < 9; k++)
 			writeb(read_ecc[k], &emc->nfpar[k]);
 	}
-	/* Set PRDY */
+
 	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
 
 	/* Wait for completion */

@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		status = readl(&emc->nfints);
 	} while (!(status & EMC_NFINTS_DECF));
 
-	/* disable ecc */
+	/* Disable ECC */
 	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
 
 	/* Check decoding */

@@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		return 0;
 
 	if (status & EMC_NFINTS_UNCOR) {
-		printf("uncorrectable ecc\n");
+		printf("JZ4740 uncorrectable ECC\n");
 		return -1;
 	}

@@ -230,6 +234,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 	return errcnt;
 }
 
+#ifdef CONFIG_NAND_SPL
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+
+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
+	for (i = 0; i < len; i += 2)
+		buf[i] = readw(this->IO_ADDR_R);
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
+	for (i = 0; i < len; i++)
+		buf[i] = readb(this->IO_ADDR_R);
+#else
+	#error JZ4740_NANDBOOT_CFG not defined or wrong
+#endif
+}
+
+uint8_t nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	return readb(this->IO_ADDR_R);
+}
+#endif
+
 /*
  * Main initialization routine
  */

@@ -247,6 +277,10 @@ int board_nand_init(struct nand_chip *nand)
 	nand->IO_ADDR_W		= JZ_NAND_DATA_ADDR;
 	nand->cmd_ctrl		= jz_nand_cmd_ctrl;
 	nand->dev_ready		= jz_nand_device_ready;
+#ifdef CONFIG_NAND_SPL
+	nand->read_byte		= nand_read_byte;
+	nand->read_buf		= nand_read_buf;
+#endif
 	nand->ecc.hwctl		= jz_nand_hwctl;
 	nand->ecc.correct	= jz_nand_rs_correct_data;
 	nand->ecc.calculate	= jz_nand_rs_calculate_ecc;

include/configs/qi_lb60.h +3 -0

index f989595..c40e4cc 100644
@@ -35,6 +35,9 @@
 #define CONFIG_BOOTARGS		"mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait"
 #define CONFIG_BOOTCOMMAND	"nand read 0x80600000 0x400000 0x200000;bootm"
 
+#define JZ4740_NANDBOOT_CFG	JZ4740_NANDBOOT_B8R3
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+
 /*
  * Command line configuration.
  */

nand_spl/board/qi/qi_lb60/Makefile new file +112 -0

112 lines not on this page · raw message

nand_spl/board/qi/qi_lb60/nand_spl.c new file +37 -0

new file mode 100644
index 0000000..6a0358a
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Xiangfu Liu <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+void nand_spl_boot(void)
+{
+	__gpio_as_sdram_16bit_4720();
+	__gpio_as_uart0();
+
+	pll_init();
+	serial_init();
+	sdram_init();
+
+	nand_boot();
+}

nand_spl/board/qi/qi_lb60/u-boot.lds new file +63 -0

63 lines not on this page · raw message

Signature · 1 line

1.7.5.4

Scott Wood

2012-01-06 22:36 UTC #1 lore raw

PATCH v2 1/1 add nand spl boot for qi_lb60 board

Quoted 14 lines · Xiangfu Liu

Signed-off-by Xiangfu Liu <[email protected]>

---
 arch/mips/cpu/xburst/cpu.c           |    4 +
 arch/mips/cpu/xburst/start_spl.S     |   65 ++++++++++++++++++++
 drivers/mtd/nand/jz4740_nand.c       |   40 +++++++++++-
 include/configs/qi_lb60.h            |    3 +
 nand_spl/board/qi/qi_lb60/Makefile   |  112 ++++++++++++++++++++++++++++++++++
 nand_spl/board/qi/qi_lb60/nand_spl.c |   37 +++++++++++
 nand_spl/board/qi/qi_lb60/u-boot.lds |   63 +++++++++++++++++++
 7 files changed, 321 insertions(+), 3 deletions(-)
 create mode 100644 arch/mips/cpu/xburst/start_spl.S
 create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
 create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
 create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

We are transitioning from nand_spl/ to spl/. Please try to work within the new infrastructure. You may run into problems with size in spl/, due to gc-sections not removing strings on components you don't need -- I plan to fix those issues (for NAND), hopefully this merge window, by requiring all files to be explicitly asked for. Feel free to fix them first if you'd like. :-)

Quoted 83 lines

arch/mips/cpu/xburst/cpu.c +4 -0

index e976341..afd166c 100644
@@ -42,6 +42,8 @@
 		:			\
 		: "i" (op), "R" (*(unsigned char *)(addr)))
 
+#ifndef CONFIG_NAND_SPL
+
 void __attribute__((weak)) _machine_restart(void)
 {
 	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;

@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 		cache_op(Hit_Invalidate_D, addr);
 }
 
+#endif
+
 void flush_icache_all(void)
 {
 	u32 addr, t = 0;

arch/mips/cpu/xburst/start_spl.S new file +55 -0

new file mode 100644
index 0000000..f137ccd
@@ -0,0 +1,65 @@
+/*
+ *  Startup Code for MIPS32 XBURST CPU-core
+ *
+ *  Copyright (c) 2010 Xiangfu Liu <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 3 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#include <asm/jz4740.h>
+
+	.set noreorder
+
+	.globl _start
+	.text
+_start:
+	.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
+reset:
+	/*
+	 * STATUS register
+	 * CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
+	 */
+	li	t0, 0x0040FC04
+	mtc0	t0, CP0_STATUS
+	/*
+	 * CAUSE register
+	 * IV=1, use the specical interrupt vector (0x200)
+	 */
+	li	t1, 0x00800000
+	mtc0	t1, CP0_CAUSE
+
+	bal     1f
+	 nop

arch/mips/cpu/xburst/start_spl.S line 65

Quoted 10 lines

arch/mips/cpu/xburst/start_spl.S new file +10 -0

+	.word   _GLOBAL_OFFSET_TABLE_
+1:
+	move    gp, ra
+	lw      t1, 0(ra)
+	move	gp, t1
+
+	la	sp, 0x80004000
+	la	t9, nand_spl_boot
+	j	t9
+	 nop

Shinya, do the MIPS parts look OK?

arch/mips/cpu/xburst/start_spl.S

Quoted 6 lines

arch/mips/cpu/xburst/start_spl.S new file +6 -0

+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL -O2

Why -O2 and not the -Os that you should already be inheriting from config.mk?

arch/mips/cpu/xburst/start_spl.S

Quoted 9 lines

arch/mips/cpu/xburst/start_spl.S new file +9 -0

+# The JZ4740 CPU can load two areas of data from NAND flash to internal SRAM,
+# one is the normal area up to 8KB starting from NAND flash address 0, the
+# other is the backup area up to 8KB starting from NAND flash address 0x2000.
+
+# After reset, the boot program will first read the normal area data from NAND
+# flash using hardware Reed-Solomon ECC. If no ECC error is detected or ECC
+# error is correctable, the boot program then branches to internal SRAM at 4
+# bytes offset. ff it detects an uncorrectable ECC error, it will continue to
+# read the backup area of data from NAND flash using hardware Reed-Solomon ECC.

Why must the payload come at offset 256K, rather than 16K?

arch/mips/cpu/xburst/start_spl.S

Quoted 11 lines

arch/mips/cpu/xburst/start_spl.S new file +11 -0

+
+# those 'dd' commands is for create such two 8KB for JZ4740 CPU
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin
+	dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1
+	cat $< $(nandobj)junk1 > $(nandobj)junk2
+	dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3
+	cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4
+	dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5
+	cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6
+	dd bs=1024 count=256 if=$(nandobj)junk6 of=$@
+	rm -f $(nandobj)junk*

This is overcomplicated and difficult to follow.

Try something like this:

# This target is misnamed, but that's the toplevel Makefile's fault $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin

	dd if=$< of=$@ conv=sync bs=8192 count=1
	dd if=$< of=$@ conv=sync,notrunc oflag=append \
		bs=8192 count=1
	dd if=/dev/zero of=$@ conv=sync,notrunc oflag=append \
		bs=245760 count=1

Or consider using --pad-to or the linker script to add the 8K padding (also add an assert for too-large like arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds does). If you also get rid of the need to pad to 256k, this step then becomes "cat $< $< > $@".

Quoted 23 lines

nand_spl/board/qi/qi_lb60/u-boot.lds new file +17 -0

new file mode 100644
index 0000000..7042388
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2005
+ * Ingenic Semiconductor, <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

nand_spl/board/qi/qi_lb60/u-boot.lds line 27

Quoted 10 lines

nand_spl/board/qi/qi_lb60/u-boot.lds new file +10 -0

+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
+
+OUTPUT_ARCH(mips)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;

include/configs/qi_lb60.h says CONFIG_NAND_SPL_TEXT_BASE is 0x80000000, not zero.

-Scott

Xiangfu Liu

author

2012-01-10 15:13 UTC #2 lore raw

PATCH v2 1/1 add nand spl boot for qi_lb60 board

Hi Scott

thanks for your comments. PATCH v3 have sent out for you to review.

Quoted 7 lines · Scott Wood

We are transitioning from nand_spl/ to spl/. Please try to work within the new infrastructure. You may run into problems with size in spl/, due to gc-sections not removing strings on components you don't need -- I plan to fix those issues (for NAND), hopefully this merge window, by requiring all files to be explicitly asked for. Feel free to fix them first if you'd like. :-)

I'd like to move the new spl/. I have one question about the new spl/ I didn't see the new spl/ link to nand_spl/nand_boot.c. so how the new spl/ using nand_boot()?

can we add a new define 'CONFIG_SPL_START_S_NAME', since qi_lb60 using start_spl.S for SPL, not start.S.

I think better I make the nand_spl/ working. then move to the new spl/ :)

Quoted 9 lines

nand_spl/board/qi/qi_lb60/Makefile line 29
Quoted 6 lines
nand_spl/board/qi/qi_lb60/Makefile new file +6 -0
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_NAND_SPL_TEXT_BASE)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL -O2
Why -O2 and not the -Os that you should already be inheriting from config.mk?

when I remove the -O2. it give me error:
jz4740.c:(.text.sdram_init+0x14): undefined reference to `memcpy'
so I keep the -O2 there. please anyone give me some advice on how to fix this. that will be great.

thanks again
xiangfu

Daniel Schwierzeck

2012-01-10 16:24 UTC #3 lore raw

PATCH v2 1/1 add nand spl boot for qi_lb60 board

Quoted 15 lines · Xiangfu Liu

Hi Scott
thanks for your comments. PATCH v3 have sent out for you to review.
Quoted 8 lines · Scott Wood
We are transitioning from nand_spl/ to spl/. ?Please try to work within the new infrastructure. ?You may run into problems with size in spl/, due to gc-sections not removing strings on components you don't need -- I plan to fix those issues (for NAND), hopefully this merge window, by requiring all files to be explicitly asked for. ?Feel free to fix them first if you'd like. :-)

Quoted 6 lines

I'd like to move the new spl/. I have one question about the new spl/ I didn't see the new spl/ link to nand_spl/nand_boot.c. so how the new spl/ using nand_boot()?
can we add a new define 'CONFIG_SPL_START_S_NAME', since qi_lb60 using start_spl.S for SPL, not start.S.

you could create a spl/ directory under arch/mips/cpu/xburst/ and move your start_spl.S
to arch/mips/cpu/xburst/spl/start.S.

Then define in your board config:

#define CONFIG_SPL
#define CONFIG_SPL_TEXT_BASE YOUR_SPL_TEXT_BASE
#define CONFIG_SPL_START_S_PATH "arch/mips/cpu/xburst/spl"

Add defines CONFIG_SPL_XXX_SUPPORT where XXX is an additional library you need in your SPL binary. I guees you need at least CONFIG_SPL_NAND_SUPPORT. Have a look at spl/Makefile or doc/README.SPL for reference.

You should also move your files from nand_spl/board/qi/qi_lb60/ to board/qi/qi_lb60/ and
rename u-boot.lds to u-boot-spl.lds. The spl Makefile will automatically use this script.

Quoted 17 lines

I think better I make the nand_spl/ working. then move to the new spl/ :)
Quoted 11 lines
nand_spl/board/qi/qi_lb60/Makefile line 29
Quoted 7 lines
nand_spl/board/qi/qi_lb60/Makefile new file +4 -0
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS ? ? ? ?= -Bstatic -T $(LDSCRIPT) -Ttext
$(CONFIG_NAND_SPL_TEXT_BASE)
nand_spl/board/qi/qi_lb60/Makefile new file +2 -0
+AFLAGS += -DCONFIG_NAND_SPL
+CFLAGS += -DCONFIG_NAND_SPL -O2
Why -O2 and not the -Os that you should already be inheriting from config.mk?

Quoted 5 lines

when I remove the -O2. it give me error:
?jz4740.c:(.text.sdram_init+0x14): undefined reference to `memcpy' so I keep the -O2 there. please anyone give me some advice on how to fix this.
that will be great.

If you use the SPL framework, memcpy won't be linked if you don't use it due to gc-sections.

Signature · 2 lines

Best regards,
Daniel

Scott Wood

2012-01-10 18:07 UTC #4 lore raw

PATCH v2 1/1 add nand spl boot for qi_lb60 board

In reply to Xiangfu Liu

Quoted 13 lines · Xiangfu Liu

Hi Scott
thanks for your comments. PATCH v3 have sent out for you to review.
Quoted 7 lines · Scott Wood
We are transitioning from nand_spl/ to spl/. Please try to work within the new infrastructure. You may run into problems with size in spl/, due to gc-sections not removing strings on components you don't need -- I plan to fix those issues (for NAND), hopefully this merge window, by requiring all files to be explicitly asked for. Feel free to fix them first if you'd like. :-)

Quoted 3 lines

I'd like to move the new spl/. I have one question about the new spl/ I didn't see the new spl/ link to nand_spl/nand_boot.c. so how the new spl/ using nand_boot()?

It's been moved to drivers/mtd/nand/nand_spl_simple.c and drivers/mtd/nand/nand_spl_load.c.

Quoted 2 lines

can we add a new define 'CONFIG_SPL_START_S_NAME', since qi_lb60 using start_spl.S for SPL, not start.S.

Heh, that didn't take long:
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/108574

Or, could we just leave start.o up to the arch Makefile, and just make sure the arch "library" is linked in first?

Quoted 13 lines

I think better I make the nand_spl/ working. then move to the new spl/ :)
Quoted 10 lines
nand_spl/board/qi/qi_lb60/Makefile line 29
Quoted 7 lines
nand_spl/board/qi/qi_lb60/Makefile new file +4 -0
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LDFLAGS    = -Bstatic -T $(LDSCRIPT) -Ttext
$(CONFIG_NAND_SPL_TEXT_BASE)
nand_spl/board/qi/qi_lb60/Makefile new file +2 -0
+AFLAGS    += -DCONFIG_NAND_SPL
+CFLAGS    += -DCONFIG_NAND_SPL -O2
Why -O2 and not the -Os that you should already be inheriting from config.mk?

Quoted 5 lines

when I remove the -O2. it give me error:
jz4740.c:(.text.sdram_init+0x14): undefined reference to `memcpy'
so I keep the -O2 there. please anyone give me some advice on how to fix this.
that will be great.

GCC requires memcpy even in freestanding environments. Can you fit a minimal memcpy in, such as what's currently bcopy in lib/string.c?

-Scott

Xiangfu Liu

author

2012-01-10 15:06 UTC #5 lore raw

PATCH v3 1/1 add nand spl boot for qi_lb60 board

In reply to Xiangfu Liu

Signed-off-by Xiangfu Liu <[email protected]>

---

Changes for v2:
-Add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-Cleanup jz4740_nand.c a little

Changes for v3:
-Remove CONFIG_NAND_SPL_TEXT_BASE, fix the wrong TEXT base under SPL u-boot.lds -Remove overcomplicated 'dd', pad to 32KB SPL instead of 256. comments added in Makefile -Cleanup the qi_lb60.h

 arch/mips/cpu/xburst/cpu.c           |    4 +
 arch/mips/cpu/xburst/start_spl.S     |   65 +++++++++++++
 drivers/mtd/nand/jz4740_nand.c       |   40 ++++++++-
 include/configs/qi_lb60.h            |  166 ++++++++++++++++------------------
 nand_spl/board/qi/qi_lb60/Makefile   |  124 +++++++++++++++++++++++++
 nand_spl/board/qi/qi_lb60/nand_spl.c |   37 ++++++++
 nand_spl/board/qi/qi_lb60/u-boot.lds |   62 +++++++++++++
 7 files changed, 407 insertions(+), 91 deletions(-)
 create mode 100644 arch/mips/cpu/xburst/start_spl.S
 create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
 create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
 create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

arch/mips/cpu/xburst/cpu.c +4 -0

index e976341..afd166c 100644
@@ -42,6 +42,8 @@
 		:			\
 		: "i" (op), "R" (*(unsigned char *)(addr)))
 
+#ifndef CONFIG_NAND_SPL
+
 void __attribute__((weak)) _machine_restart(void)
 {
 	struct jz4740_wdt *wdt = (struct jz4740_wdt *)JZ4740_WDT_BASE;

@@ -109,6 +111,8 @@ void invalidate_dcache_range(ulong start_addr, ulong stop)
 		cache_op(Hit_Invalidate_D, addr);
 }
 
+#endif
+
 void flush_icache_all(void)
 {
 	u32 addr, t = 0;

arch/mips/cpu/xburst/start_spl.S new file +65 -0

65 lines not on this page · raw message

drivers/mtd/nand/jz4740_nand.c +37 -3

index 3ec34f3..7ef07a5 100644
@@ -15,6 +15,10 @@
 #include <asm/io.h>
 #include <asm/jz4740.h>
 
+#ifdef CONFIG_NAND_SPL
+  #define printf(arg...) do {} while (0)
+#endif
+
 #define JZ_NAND_DATA_ADDR ((void __iomem *)0xB8000000)
 #define JZ_NAND_CMD_ADDR (JZ_NAND_DATA_ADDR + 0x8000)
 #define JZ_NAND_ADDR_ADDR (JZ_NAND_DATA_ADDR + 0x10000)

@@ -176,7 +180,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		for (k = 0; k < 9; k++)
 			writeb(read_ecc[k], &emc->nfpar[k]);
 	}
-	/* Set PRDY */
+
 	writel(readl(&emc->nfecr) | EMC_NFECR_PRDY, &emc->nfecr);
 
 	/* Wait for completion */

@@ -184,7 +188,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		status = readl(&emc->nfints);
 	} while (!(status & EMC_NFINTS_DECF));
 
-	/* disable ecc */
+	/* Disable ECC */
 	writel(readl(&emc->nfecr) & ~EMC_NFECR_ECCE, &emc->nfecr);
 
 	/* Check decoding */

@@ -192,7 +196,7 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 		return 0;
 
 	if (status & EMC_NFINTS_UNCOR) {
-		printf("uncorrectable ecc\n");
+		printf("JZ4740 uncorrectable ECC\n");
 		return -1;
 	}

@@ -230,6 +234,32 @@ static int jz_nand_rs_correct_data(struct mtd_info *mtd, u_char *dat,
 	return errcnt;
 }
 
+#ifdef CONFIG_NAND_SPL
+void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i;
+	struct nand_chip *this = mtd->priv;
+
+#if (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B16R2)
+	for (i = 0; i < len; i += 2)
+		buf[i] = readw(this->IO_ADDR_R);
+#elif (JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R3) || \
+	(JZ4740_NANDBOOT_CFG == JZ4740_NANDBOOT_B8R2)
+	for (i = 0; i < len; i++)
+		buf[i] = readb(this->IO_ADDR_R);
+#else
+	#error JZ4740_NANDBOOT_CFG not defined or wrong
+#endif
+}
+
+uint8_t nand_read_byte(struct mtd_info *mtd)
+{
+	struct nand_chip *this = mtd->priv;
+	return readb(this->IO_ADDR_R);
+}
+#endif
+
 /*
  * Main initialization routine
  */

@@ -247,6 +277,10 @@ int board_nand_init(struct nand_chip *nand)
 	nand->IO_ADDR_W		= JZ_NAND_DATA_ADDR;
 	nand->cmd_ctrl		= jz_nand_cmd_ctrl;
 	nand->dev_ready		= jz_nand_device_ready;
+#ifdef CONFIG_NAND_SPL
+	nand->read_byte		= nand_read_byte;
+	nand->read_buf		= nand_read_buf;
+#endif
 	nand->ecc.hwctl		= jz_nand_hwctl;
 	nand->ecc.correct	= jz_nand_rs_correct_data;
 	nand->ecc.calculate	= jz_nand_rs_calculate_ecc;

include/configs/qi_lb60.h +78 ~~-88~~

246 lines not on this page · raw message

nand_spl/board/qi/qi_lb60/Makefile new file +124 -0

124 lines not on this page · raw message

nand_spl/board/qi/qi_lb60/nand_spl.c new file +37 -0

new file mode 100644
index 0000000..6a0358a
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2012 Xiangfu Liu <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/jz4740.h>
+
+void nand_spl_boot(void)
+{
+	__gpio_as_sdram_16bit_4720();
+	__gpio_as_uart0();
+
+	pll_init();
+	serial_init();
+	sdram_init();
+
+	nand_boot();
+}

nand_spl/board/qi/qi_lb60/u-boot.lds new file +62 -0

62 lines not on this page · raw message

Signature · 1 line

1.7.5.4

Wolfgang Denk

2012-03-06 21:04 UTC #6 lore raw

PATCH v3 1/1 add nand spl boot for qi_lb60 board

Dear Xiangfu Liu,

Quoted 12 lines · In message <[email protected]> you…

Signed-off-by Xiangfu Liu <[email protected]>
---
Changes for v2:
-Add CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-Cleanup jz4740_nand.c a little
Changes for v3:
-Remove CONFIG_NAND_SPL_TEXT_BASE, fix the wrong TEXT base under SPL u-boot.lds -Remove overcomplicated 'dd', pad to 32KB SPL instead of 256. comments added in Makefile -Cleanup the qi_lb60.h

Quoted 12 lines

 arch/mips/cpu/xburst/cpu.c           |    4 +
 arch/mips/cpu/xburst/start_spl.S     |   65 +++++++++++++
 drivers/mtd/nand/jz4740_nand.c       |   40 ++++++++-
 include/configs/qi_lb60.h            |  166 ++++++++++++++++------------------
 nand_spl/board/qi/qi_lb60/Makefile   |  124 +++++++++++++++++++++++++
 nand_spl/board/qi/qi_lb60/nand_spl.c |   37 ++++++++
 nand_spl/board/qi/qi_lb60/u-boot.lds |   62 +++++++++++++
 7 files changed, 407 insertions(+), 91 deletions(-)
 create mode 100644 arch/mips/cpu/xburst/start_spl.S
 create mode 100644 nand_spl/board/qi/qi_lb60/Makefile
 create mode 100644 nand_spl/board/qi/qi_lb60/nand_spl.c
 create mode 100644 nand_spl/board/qi/qi_lb60/u-boot.lds

I don't want to see more boards added to the old /nand_spl/ infrastructure. You said you were converting to /spl/ instead?

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
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