atmel_lcdfb: Adjust HFP calculation so it matches the manual.
PATCH 1/2 atmel_lcdfb: Adjust HFP calculation so it matches the manual.
In the AT91SAM9263 Manual the HFP part in LCDTIM2 is described as follows:
* HFP: Horizontal Front Porch
Number of idle LCDDOTCK cycles at the end of the line.
Idle period is (HFP+2) LCDDOTCK cycles.
It is only a minor issue. I also changed all boards using atmel_lcdfb I found to respect the new calculation.
--- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 4 ++-- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- drivers/video/atmel_lcdfb.c | 4 ++-- 7 files changed, 9 insertions(+), 9 deletions(-)
arch/arm/mach-at91/board-cap9adk.c +1 -1
@@ -304,7 +304,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,
arch/arm/mach-at91/board-neocore926.c +1 -1
@@ -235,7 +235,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(5000), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,
arch/arm/mach-at91/board-sam9261ek.c +2 -2
@@ -370,7 +370,7 @@ static struct fb_videomode at91_stn_modes[] = { .xres = 320, .yres = 240, .pixclock = KHZ2PICOS(1440), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 0, .lower_margin = 0, .hsync_len = 1, .vsync_len = 1,
@@ -431,7 +431,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,
arch/arm/mach-at91/board-sam9263ek.c +1 -1
@@ -258,7 +258,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,
arch/arm/mach-at91/board-sam9m10g45ek.c +1 -1
@@ -197,7 +197,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 480, .yres = 272, .pixclock = KHZ2PICOS(9000), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 40, .lower_margin = 1, .hsync_len = 45, .vsync_len = 1,
arch/arm/mach-at91/board-sam9rlek.c +1 -1
@@ -154,7 +154,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,
drivers/video/atmel_lcdfb.c +2 -2
@@ -393,7 +393,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, var->lower_margin =min_t (u32, var->lower_margin,ATMEL_LCDC_VFP ); var->right_margin =min_t (u32, var->right_margin, - (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +1 ); + (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +2 ); var->hsync_len =min_t (u32, var->hsync_len, (ATMEL_LCDC_HPW >>ATMEL_LCDC_HPW_OFFSET ) +1 ); var->left_margin = min_t(u32, var->left_margin,
@@ -578,7 +578,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)lcdc_writel (sinfo,ATMEL_LCDC_TIM1 , value);/* Horizontal timing */ - value = (info->var.right_margin -1 ) <<ATMEL_LCDC_HFP_OFFSET ; + value = (info->var.right_margin -2 ) <<ATMEL_LCDC_HFP_OFFSET ; value |= (info->var.hsync_len -1 ) <<ATMEL_LCDC_HPW_OFFSET ; value |= (info->var.left_margin -1 );dev_dbg (info->device," * LCDTIM2 = %08lx\n" , value);
Signature · 1 line
1.7.3.4
PATCH 2/2 atmel_lcdfb: Use proper blanking on negative contrast polarity
If used with negative polarity the PWM unit cannot be disabled. This would result in a full contrast screen.
Instead let the PWM unit enabled using 0x0 as compare value which darkens the display.
In result no power saving is possible if inverted contrast polarity is used.
--- drivers/video/atmel_lcdfb.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)
drivers/video/atmel_lcdfb.c +4 -1
@@ -96,8 +96,11 @@ static int atmel_bl_update_status(struct backlight_device *bl) brightness =0 ;lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_VAL , brightness); -lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_CTR , +if (contrast_ctr &ATMEL_LCDC_POL_POSITIVE ) +lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_CTR , brightness ? contrast_ctr :0 ); +else +lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_CTR , contrast_ctr); bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
Signature · 1 line
1.7.3.4
PATCH 2/2 atmel_lcdfb: Use proper blanking on negative contrast polarity
On 10/05/2011 09:59 AM, Alexander Stein :
Quoted 6 lines
If used with negative polarity the PWM unit cannot be disabled. This would result in a full contrast screen.
Instead let the PWM unit enabled using0x0as compare value which darkens the display.
In result no power saving is possible if inverted contrast polarity is used.
Ok, this patch looks correct.
Quoted 1 line
Signed-off-by Alexander Stein <[email protected]>
Florian, you can propagate this one upstream.
Thanks you, best regards,
Quoted 21 lines
--- drivers/video/atmel_lcdfb.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-)drivers/video/atmel_lcdfb.c +4
-1@@ -96,8 +96,11 @@ static int atmel_bl_update_status(struct backlight_device *bl) brightness =0 ;lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_VAL , brightness); -lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_CTR , +if (contrast_ctr &ATMEL_LCDC_POL_POSITIVE ) +lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_CTR , brightness ? contrast_ctr :0 ); +else +lcdc_writel (sinfo,ATMEL_LCDC_CONTRAST_CTR , contrast_ctr); bl->props.fb_blank = bl->props.power = sinfo->bl_power = power;
Signature · 1 line
Nicolas Ferre
PATCH 1/2 atmel_lcdfb: Adjust HFP calculation so it matches the manual.
In reply to Alexander SteinQuoted 7 lines · Alexander Stein
In the AT91SAM9263 Manual the HFP part in LCDTIM2 is described as follows:
* HFP: Horizontal Front Porch
Number of idle LCDDOTCK cycles at the end of the line.
Idle period is (HFP+2) LCDDOTCK cycles.It is only a minor issue. I also changed all boards using
atmel_lcdfbI found to respect the new calculation.
Applied both patches of this series.
Thanks,
Florian Tobias Schandinat
Quoted 121 lines
Signed-off-by Alexander Stein <[email protected]>--- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 4 ++-- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- drivers/video/atmel_lcdfb.c | 4 ++-- 7 files changed, 9 insertions(+), 9 deletions(-)arch/arm/mach-at91/board-cap9adk.c +1
-1@@ -304,7 +304,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-neocore926.c +1
-1@@ -235,7 +235,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(5000), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9261ek.c +2
-2@@ -370,7 +370,7 @@ static struct fb_videomode at91_stn_modes[] = { .xres = 320, .yres = 240, .pixclock = KHZ2PICOS(1440), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 0, .lower_margin = 0, .hsync_len = 1, .vsync_len = 1,@@ -431,7 +431,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9263ek.c +1
-1@@ -258,7 +258,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9m10g45ek.c +1
-1@@ -197,7 +197,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 480, .yres = 272, .pixclock = KHZ2PICOS(9000), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 40, .lower_margin = 1, .hsync_len = 45, .vsync_len = 1,arch/arm/mach-at91/board-sam9rlek.c +1
-1@@ -154,7 +154,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,drivers/video/atmel_lcdfb.c +2
-2@@ -393,7 +393,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, var->lower_margin =min_t (u32, var->lower_margin,ATMEL_LCDC_VFP ); var->right_margin =min_t (u32, var->right_margin, - (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +1 ); + (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +2 ); var->hsync_len =min_t (u32, var->hsync_len, (ATMEL_LCDC_HPW >>ATMEL_LCDC_HPW_OFFSET ) +1 ); var->left_margin = min_t(u32, var->left_margin,@@ -578,7 +578,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)lcdc_writel (sinfo,ATMEL_LCDC_TIM1 , value);/* Horizontal timing */ - value = (info->var.right_margin -1 ) <<ATMEL_LCDC_HFP_OFFSET ; + value = (info->var.right_margin -2 ) <<ATMEL_LCDC_HFP_OFFSET ; value |= (info->var.hsync_len -1 ) <<ATMEL_LCDC_HPW_OFFSET ; value |= (info->var.left_margin -1 );dev_dbg (info->device," * LCDTIM2 = %08lx\n" , value);
PATCH 1/2 atmel_lcdfb: Adjust HFP calculation so it matches the manual.
In reply to Alexander SteinOn 10/05/2011 09:59 AM, Alexander Stein :
Quoted 4 lines
In the AT91SAM9263 Manual the HFP part in LCDTIM2 is described as follows:
* HFP: Horizontal Front Porch
Number of idle LCDDOTCK cycles at the end of the line.
Idle period is (HFP+2) LCDDOTCK cycles.
Hi Alexander,
Unfortunately this is not true for all the SoC that embed the atmel_lcdfb... So I may need to rework this patch but it is certainly not applicable in the current form.
Florian, can you please remove it from your git tree?
Thanks,
Best regards,
Quoted 123 lines
It is only a minor issue. I also changed all boards using
atmel_lcdfbI found to respect the new calculation.Signed-off-by Alexander Stein <[email protected]>--- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 4 ++- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- drivers/video/atmel_lcdfb.c | 4 ++-- 7 files changed, 9 insertions(+), 9 deletions(-)arch/arm/mach-at91/board-cap9adk.c +1
-1@@ -304,7 +304,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-neocore926.c +1
-1@@ -235,7 +235,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(5000), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9261ek.c +2
-2@@ -370,7 +370,7 @@ static struct fb_videomode at91_stn_modes[] = { .xres = 320, .yres = 240, .pixclock = KHZ2PICOS(1440), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 0, .lower_margin = 0, .hsync_len = 1, .vsync_len = 1,@@ -431,7 +431,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9263ek.c +1
-1@@ -258,7 +258,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9m10g45ek.c +1
-1@@ -197,7 +197,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 480, .yres = 272, .pixclock = KHZ2PICOS(9000), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 40, .lower_margin = 1, .hsync_len = 45, .vsync_len = 1,arch/arm/mach-at91/board-sam9rlek.c +1
-1@@ -154,7 +154,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,drivers/video/atmel_lcdfb.c +2
-2@@ -393,7 +393,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, var->lower_margin =min_t (u32, var->lower_margin,ATMEL_LCDC_VFP ); var->right_margin =min_t (u32, var->right_margin, - (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +1 ); + (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +2 ); var->hsync_len =min_t (u32, var->hsync_len, (ATMEL_LCDC_HPW >>ATMEL_LCDC_HPW_OFFSET ) +1 ); var->left_margin = min_t(u32, var->left_margin,@@ -578,7 +578,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)lcdc_writel (sinfo,ATMEL_LCDC_TIM1 , value);/* Horizontal timing */ - value = (info->var.right_margin -1 ) <<ATMEL_LCDC_HFP_OFFSET ; + value = (info->var.right_margin -2 ) <<ATMEL_LCDC_HFP_OFFSET ; value |= (info->var.hsync_len -1 ) <<ATMEL_LCDC_HPW_OFFSET ; value |= (info->var.left_margin -1 );dev_dbg (info->device," * LCDTIM2 = %08lx\n" , value);
Signature · 1 line
Nicolas Ferre
PATCH 1/2 atmel_lcdfb: Adjust HFP calculation so it matches the manual.
Hi Nicolas, Alexander,
Quoted 6 lines · Nicolas Ferre
On 10/05/2011 09:59 AM, Alexander Stein :
Quoted 4 lines
In the AT91SAM9263 Manual the HFP part in LCDTIM2 is described as follows:
* HFP: Horizontal Front Porch
Number of idle LCDDOTCK cycles at the end of the line.
Idle period is (HFP+2) LCDDOTCK cycles.
Quoted 7 lines
Hi Alexander,
Unfortunately this is not true for all the SoC that embed the
atmel_lcdfb... So I may need to rework this patch but it is certainly not applicable in the current form.Florian, can you please remove it from your git tree?
Done, I reverted this patch for now.
For the other patches, those that are currently in my tree, I will ask Linus to pull them really soon. For the others I'll take care of them after the merge window is closed.
Best regards,
Florian Tobias Schandinat
Quoted 130 lines
Thanks,
Best regards,
Quoted 123 lines
It is only a minor issue. I also changed all boards using
atmel_lcdfbI found to respect the new calculation.Signed-off-by Alexander Stein <[email protected]>--- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 4 ++- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- drivers/video/atmel_lcdfb.c | 4 ++-- 7 files changed, 9 insertions(+), 9 deletions(-)arch/arm/mach-at91/board-cap9adk.c +1
-1@@ -304,7 +304,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-neocore926.c +1
-1@@ -235,7 +235,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(5000), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9261ek.c +2
-2@@ -370,7 +370,7 @@ static struct fb_videomode at91_stn_modes[] = { .xres = 320, .yres = 240, .pixclock = KHZ2PICOS(1440), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 0, .lower_margin = 0, .hsync_len = 1, .vsync_len = 1,@@ -431,7 +431,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9263ek.c +1
-1@@ -258,7 +258,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,arch/arm/mach-at91/board-sam9m10g45ek.c +1
-1@@ -197,7 +197,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 480, .yres = 272, .pixclock = KHZ2PICOS(9000), - .left_margin = 1, .right_margin = 1, + .left_margin = 1, .right_margin = 2, .upper_margin = 40, .lower_margin = 1, .hsync_len = 45, .vsync_len = 1,arch/arm/mach-at91/board-sam9rlek.c +1
-1@@ -154,7 +154,7 @@ static struct fb_videomode at91_tft_vga_modes[] = { .xres = 240, .yres = 320, .pixclock = KHZ2PICOS(4965), - .left_margin = 1, .right_margin = 33, + .left_margin = 1, .right_margin = 34, .upper_margin = 1, .lower_margin = 0, .hsync_len = 5, .vsync_len = 1,drivers/video/atmel_lcdfb.c +2
-2@@ -393,7 +393,7 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var, var->lower_margin =min_t (u32, var->lower_margin,ATMEL_LCDC_VFP ); var->right_margin =min_t (u32, var->right_margin, - (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +1 ); + (ATMEL_LCDC_HFP >>ATMEL_LCDC_HFP_OFFSET ) +2 ); var->hsync_len =min_t (u32, var->hsync_len, (ATMEL_LCDC_HPW >>ATMEL_LCDC_HPW_OFFSET ) +1 ); var->left_margin = min_t(u32, var->left_margin,@@ -578,7 +578,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info)lcdc_writel (sinfo,ATMEL_LCDC_TIM1 , value);/* Horizontal timing */ - value = (info->var.right_margin -1 ) <<ATMEL_LCDC_HFP_OFFSET ; + value = (info->var.right_margin -2 ) <<ATMEL_LCDC_HFP_OFFSET ; value |= (info->var.hsync_len -1 ) <<ATMEL_LCDC_HPW_OFFSET ; value |= (info->var.left_margin -1 );dev_dbg (info->device," * LCDTIM2 = %08lx\n" , value);