Added SPL support

index ad9156e..d18750a 100644
@@ -51,7 +51,7 @@
 					| BIT(3) | BIT(4))
 
 /* Reset control */
-#ifdef CONFIG_AM335X
+#ifdef CONFIG_AM33XX
 #define PRM_RSTCTRL			0x44E00F00
 #endif
 #define PRM_RSTCTRL_RESET		0x01

index 26a3c96..f737094 100644
@@ -16,7 +16,7 @@
 #ifndef __CONFIG_AM335X_EVM_H
 #define __CONFIG_AM335X_EVM_H
 
-#define CONFIG_AM335X
+#define CONFIG_AM33XX
 #define CONFIG_CMD_MEMORY	/* for mtest */
 #undef CONFIG_GZIP
 #undef CONFIG_ZLIB

index 2d6d359..78db3a5 100644
@@ -26,7 +26,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
 
 /*
  * early system init of muxing and clocks.

@@ -55,12 +55,12 @@ void s_init(u32 in_ddr)
 void init_timer(void)
 {
 	/* Reset the Timer */
-	writel(0x2, (&timerreg->tsicrreg));
+	writel(0x2, (&timer_base->tscir));
 
 	/* Wait until the reset is done */
-	while (readl(&timerreg->tiocpcfgreg) & 1)
+	while (readl(&timer_base->tiocp_cfg) & 1)
 		;
 
 	/* Start the Timer */
-	writel(0x1, (&timerreg->tclrreg));
+	writel(0x1, (&timer_base->tclr));
 }

index 4ca6c45..7070e7d 100644
@@ -101,6 +101,9 @@ static void enable_per_clocks(void)
 	while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 		;
 
+	/* Select the Master osc 24 MHZ as Timer2 clock source */
+	writel(0x1, &cmdpll->clktimer2clk);
+
 	/* UART0 */
 	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)

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index 9638b4c..ba6b59b 100644
@@ -76,7 +76,7 @@ struct emif_regs {
 	unsigned int sdrmcsr;		/* offset 0x3C */
 	unsigned int res2[8];
 	unsigned int sdritr;		/* offset 0x60 */
-	unsigned int res3[20];
+	unsigned int res3[32];
 	unsigned int ddrphycr;		/* offset 0xE4 */
 	unsigned int ddrphycsr;		/* offset 0xE8 */
 	unsigned int ddrphycr2;		/* offset 0xEC */

@@ -161,10 +161,10 @@ struct ddr_regs {
 	unsigned int dt0wiratio1;	/* offset 0x0F4 */
 	unsigned int dt0giratio0;	/* offset 0x0FC */
 	unsigned int dt0giratio1;	/* offset 0x100 */
-	unsigned int resv6[2];
+	unsigned int resv6[1];
 	unsigned int dt0fwsratio0;	/* offset 0x108 */
 	unsigned int dt0fwsratio1;	/* offset 0x10C */
-	unsigned int resv7[5];
+	unsigned int resv7[4];
 	unsigned int dt0wrsratio0;	/* offset 0x120 */
 	unsigned int dt0wrsratio1;	/* offset 0x124 */
 	unsigned int resv8[3];

index f737094..c189031 100644
@@ -30,7 +30,7 @@
 #define CONFIG_AM335X_CONFIG_DDR
 #define CONFIG_ENV_SIZE			0x400
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (8 * 1024))
-#define CONFIG_SYS_PROMPT		"AM335X# "
+#define CONFIG_SYS_PROMPT		"U-Boot# "
 #define CONFIG_SYS_NO_FLASH
 #define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
 #define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM

@@ -48,14 +48,12 @@
 
 /* Clock Defines */
 #define V_OSCK				24000000  /* Clock output from T2 */
-#define V_SCLK				(V_OSCK >> 1)
+#define V_SCLK				(V_OSCK)
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for
-						   initial data */
 #define CONFIG_CMD_ECHO
 
 /* max number of command args */
-#define CONFIG_SYS_MAXARGS		32
+#define CONFIG_SYS_MAXARGS		16
 
 /* Console I/O Buffer Size */
 #define CONFIG_SYS_CBSIZE		512

@@ -75,7 +73,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START \
 					+ (8 * 1024 * 1024))
 
-#undef  CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
 #define CONFIG_SYS_HZ			1000 /* 1ms clock */
 

@@ -89,7 +86,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
 						GENERATED_GBL_DATA_SIZE)
  /* Platform/Board specific defs */
-#define CONFIG_SYS_CLK_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
 #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
 #define CONFIG_SYS_HZ			1000

@@ -100,7 +96,6 @@
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		(48000000)
 #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* Base EVM has UART0 */
-#define CONFIG_SYS_NS16550_COM4		0x481A6000	/* UART3 on IA BOard */
 
 #define CONFIG_BAUDRATE		115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 110, 300, 600, 1200, 2400, \

index 78db3a5..312643c 100644
@@ -64,3 +64,10 @@ void init_timer(void)
 	/* Start the Timer */
 	writel(0x1, (&timer_base->tclr));
 }
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif

index 7070e7d..98cfd93 100644
@@ -108,6 +108,11 @@ static void enable_per_clocks(void)
 	writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 	while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 		;
+
+	/* MMC0*/
+	writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
+	while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
+		;
 }
 
 static void mpu_pll_config(void)

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index 8f27409..27f5f30 100644
@@ -258,6 +258,20 @@ static struct module_pin_mux uart0_pin_mux[] = {
 	{-1},
 };
 
+#ifdef CONFIG_MMC
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT3 */
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* MMC0_CMD */
+	{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)},		/* MMC0_WP */
+	{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)},	/* MMC0_CD */
+	{-1},
+};
+#endif
+
 /*
  * Configure the pin mux for the module
  */

@@ -276,3 +290,10 @@ void enable_uart0_pin_mux(void)
 {
 	configure_module_pin_mux(uart0_pin_mux);
 }
+
+#ifdef CONFIG_MMC
+void enable_mmc0_pin_mux(void)
+{
+	configure_module_pin_mux(mmc0_pin_mux);
+}
+#endif

index c189031..1a25eb3 100644
@@ -76,6 +76,14 @@
 #define CONFIG_SYS_LOAD_ADDR		0x81000000 /* Default load address */
 #define CONFIG_SYS_HZ			1000 /* 1ms clock */
 
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_CMD_MMC
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
  /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1		/*  1 bank of DRAM */
 #define PHYS_DRAM_1			0x80000000	/* DRAM Bank #1 */

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index 1318365..2f4164d 100644
@@ -46,7 +46,7 @@ void dram_init_banksize(void)
 }
 
 
-#ifdef CONFIG_AM335X_CONFIG_DDR
+#ifdef CONFIG_SPL_BUILD
 static void data_macro_config(int dataMacroNum)
 {
 	struct ddr_data data;

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index f65705d..da22f73 100644
@@ -35,34 +35,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * This is used to verify if the configuration header
- * was executed by rom code prior to control of transfer
- * to the bootloader. SPL is responsible for saving and
- * passing the boot_params pointer to the u-boot.
- */
-struct omap_boot_parameters boot_params __attribute__ ((section(".data")));
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * We use static variables because global data is not ready yet.
- * Initialized data is available in SPL right from the beginning.
- * We would not typically need to save these parameters in regular
- * U-Boot. This is needed only in SPL at the moment.
- */
-u32 omap_bootmode = MMCSD_MODE_FAT;
-
-u32 omap_boot_device(void)
-{
-	return (u32) (boot_params.omap_bootdevice);
-}
-
-u32 omap_boot_mode(void)
-{
-	return omap_bootmode;
-}
-#endif
-
 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
 {
 	int i;

new file mode 100644
index 0000000..767932d
@@ -0,0 +1,22 @@
+/*
+ * common_def.h
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __COMMON_DEF_H__
+#define __COMMON_DEF_H__
+
+extern void enable_uart0_pin_mux(void);
+extern void enable_mmc0_pin_mux(void);
+
+#endif/*__COMMON_DEF_H__ */

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index 09ed650..6c58f1b 100644
@@ -29,4 +29,5 @@ int print_cpuinfo(void);
 #endif
 
 u32 get_device_type(void);
+void setup_clocks_for_console(void);
 #endif

index 1ec651b..efbf646 100644
@@ -62,6 +62,11 @@ void preloader_console_init(void);
 #define BOOT_DEVICE_MMC2	5 /*emmc*/
 #define BOOT_DEVICE_MMC1	6
 #define BOOT_DEVICE_XIPWAIT	7
+#elif defined(CONFIG_AM33XX)	/* AM33XX */
+#define BOOT_DEVICE_NAND	5
+#define BOOT_DEVICE_MMC1	8
+#define BOOT_DEVICE_MMC2	0
+#define BOOT_DEVICE_UART	65
 #endif
 
 /* Boot type */

deleted file mode 100644
index 1696d60..0000000
@@ -1,24 +0,0 @@
-/*
- * common_def.h
- *
- * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __COMMON_DEF_H__
-#define __COMMON_DEF_H__
-
-extern void enable_uart0_pin_mux(void);
-extern void configure_evm_pin_mux(unsigned char daughter_board_id,
-					unsigned short daughter_board_profile,
-					unsigned char daughter_board_flag);
-
-#endif/*__COMMON_DEF_H__ */

index b4eddd8..6a9f788 100644
@@ -16,7 +16,7 @@
 #include <common.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
-#include "common_def.h"
+#include <asm/arch/common_def.h>
 #include <serial.h>
 
 DECLARE_GLOBAL_DATA_PTR;

index 27f5f30..4cb0cdf 100644
@@ -14,7 +14,7 @@
  */
 
 #include <config.h>
-#include "common_def.h"
+#include <asm/arch/common_def.h>
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 

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