Skip to contentSkip to conversation

imx: mx6q: add aipstz init for off platform periph

PATCH New Jason Liu 2 participants 2 messages Jan 10, 2012 – Jan 11, 2012

Subsystems (2)
Arm (32-bit) Arm i.MX and Layerscape
lore
Share & tools
lore

Jason Liu

author
#0 lore raw

PATCH 1/1 imx: mx6q: add aipstz init for off platform periph

Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW):      0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP):      0 -> allows write accesses.
Trusted Protect(TP):    0 -> allows unstrusted master
Signed-off-by Jason Liu <[email protected]>
Cc Stefano Babic <[email protected]>
---
 arch/arm/cpu/armv7/mx6/soc.c             |   29 +++++++++++++++++++++++------
 arch/arm/include/asm/arch-mx6/imx-regs.h |   11 +++++++++++
 2 files changed, 34 insertions(+), 6 deletions(-)
arch/arm/cpu/armv7/mx6/soc.c +23 -6
index bd59cf5..bec53cd 100644
@@ -40,18 +40,35 @@ u32 get_cpu_rev(void)
 #ifdef CONFIG_ARCH_CPU_INIT
 void init_aips(void)
 {
-	u32 reg = AIPS1_BASE_ADDR;
+	struct aipstz_regs *aips1, *aips2;
+
+	aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
+	aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
 
 	/*
 	 * Set all MPROTx to be non-bufferable, trusted for R/W,
 	 * not forced to user-mode.
 	 */
-	writel(0x77777777, reg + 0x00);
-	writel(0x77777777, reg + 0x04);
+	writel(0x77777777, &aips1->mprot0);
+	writel(0x77777777, &aips1->mprot1);
+	writel(0x77777777, &aips2->mprot0);
+	writel(0x77777777, &aips2->mprot1);
 
-	reg = AIPS2_BASE_ADDR;
-	writel(0x77777777, reg + 0x00);
-	writel(0x77777777, reg + 0x04);
+	/*
+	 * Set all OPACRx to be non-bufferable, not require
+	 * supervisor privilege level for access,allow for
+	 * write access and untrusted master access.
+	 */
+	writel(0x00000000, &aips1->opacr0);
+	writel(0x00000000, &aips1->opacr1);
+	writel(0x00000000, &aips1->opacr2);
+	writel(0x00000000, &aips1->opacr3);
+	writel(0x00000000, &aips1->opacr4);
+	writel(0x00000000, &aips2->opacr0);
+	writel(0x00000000, &aips2->opacr1);
+	writel(0x00000000, &aips2->opacr2);
+	writel(0x00000000, &aips2->opacr3);
+	writel(0x00000000, &aips2->opacr4);
 }
 
 int arch_cpu_init(void)
arch/arm/include/asm/arch-mx6/imx-regs.h +11 -0
index 5fe9748..7650cb9 100644
@@ -232,5 +232,16 @@ struct fuse_bank4_regs {
 	u32	rsvd3[0x13];
 };
 
+struct aipstz_regs {
+	u32	mprot0;
+	u32	mprot1;
+	u32	rsvd[0xe];
+	u32	opacr0;
+	u32	opacr1;
+	u32	opacr2;
+	u32	opacr3;
+	u32	opacr4;
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
Signature · 1 line
1.7.4.1
#1 lore raw

PATCH 1/1 imx: mx6q: add aipstz init for off platform periph

Quoted 10 lines · Jason Liu

Init peripheral access control register of AIPSTZ OPACRx:

Buffer Writes(BW):      0 -> not bufferable,
Supervisor Protect(SP): 0 -> not require supervisor privilege level for accesses.
Write Protect(WP):      0 -> allows write accesses.
Trusted Protect(TP):    0 -> allows unstrusted master
Signed-off-by Jason Liu <[email protected]>
Cc Stefano Babic <[email protected]>

---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================