ARM: OMAP2+: Interrupt controllers adaptation to DT

PATCH Superseded Benoit Cousson 4 participants 22 messages Dec 20, 2011 – Jan 13, 2012

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Device tree bindings Arm (32-bit) Arm sub-architectures OMAP2+ support

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Benoit Cousson

author

2011-12-20 13:39 UTC #0 lore raw

v2 cover ARM: OMAP2+: Interrupt controllers adaptation to DT

Hi Tony and Rob,

Here is the series to take advantage of the new DT interrupt init mechanism. Thanks to Marc's CONFIG_MULTI_IRQ_HANDLER series, OMAP4 just has to use the default GIC binding and does not need some OMAP specific hacks anymore. OMAP2 and 3 are using a simple interrupt controller that can thus expose a simpler binding.

This update, compared to v1 [1], is introducing the IRQ domain for the OMAP2&3 INTC by default for both DT and none-DT build.
Please note that in the near future that code can even be simplier with the introduction of the domain support inside generic irq chip.

This series is based on lo/dt branch to get the needed cleanup and fixes for OMAP.

The series is available here for reference:
git://gitorious.org/omap-pm/linux.git for_3.3/2_dt_irq

Regards,
Benoit

[1] http://www.spinics.net/lists/linux-omap/msg61152.html

Benoit Cousson (5):
arm/dts: OMAP4: Update DTS file with new GIC bindings
ARM: OMAP2/3: intc: Add irqdomain support
ARM: OMAP2/3: intc: Add DT support for TI interrupt controller arm/dts: OMAP3: Add interrupt-controller bindings for INTC
ARM: OMAP2+: board-generic: Use of_irq_init API

 .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++++
 arch/arm/boot/dts/omap3.dtsi                       |    6 ++-
 arch/arm/boot/dts/omap4.dtsi                       |    3 +-
 arch/arm/mach-omap2/board-generic.c                |   30 +++++++------
 arch/arm/mach-omap2/common.h                       |   10 ++++
 arch/arm/mach-omap2/irq.c                          |   48 ++++++++++++++++++--
 6 files changed, 103 insertions(+), 21 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

Benoit Cousson

author

2011-12-20 13:39 UTC #1 lore raw

PATCH v2 1/5 arm/dts: OMAP4: Update DTS file with new GIC bindings

The GIC binding was updated in 3.2 and expect 3 interrupt-cells.
- Update the #interrupt-cells
- interrupt-parent seems to be needed as well for the top level GIC

Signed-off-by Benoit Cousson <[email protected]>

Cc Rob Herring <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

arch/arm/boot/dts/omap4.dtsi +2 -1

index 4c61c82..bede009 100644
@@ -95,7 +95,8 @@
 		gic: interrupt-controller at 48241000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
-			#interrupt-cells = <1>;
+			interrupt-parent;
+			#interrupt-cells = <3>;
 			reg = <0x48241000 0x1000>,
 			      <0x48240100 0x0100>;
 		};

Signature · 1 line

1.7.0.4

Grant Likely

2012-01-06 21:15 UTC #2 lore raw

PATCH v2 1/5 arm/dts: OMAP4: Update DTS file with new GIC bindings

Quoted 3 lines · Benoit Cousson

The GIC binding was updated in 3.2 and expect 3 interrupt-cells.
- Update the #interrupt-cells
- interrupt-parent seems to be needed as well for the top level GIC

Hmmm... it shouldn't be. If it is then it is a bug.

Quoted 29 lines

Signed-off-by Benoit Cousson <[email protected]>

Cc Rob Herring <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

arch/arm/boot/dts/omap4.dtsi +2 -1

index 4c61c82..bede009 100644
@@ -95,7 +95,8 @@
 		gic: interrupt-controller at 48241000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
-			#interrupt-cells = <1>;
+			interrupt-parent;
+			#interrupt-cells = <3>;
 			reg = <0x48241000 0x1000>,
 			      <0x48240100 0x0100>;
 		};

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Rob Herring

2012-01-06 21:30 UTC #3 lore raw

PATCH v2 1/5 arm/dts: OMAP4: Update DTS file with new GIC bindings

Quoted 7 lines · Grant Likely

Quoted 3 lines · Benoit Cousson
The GIC binding was updated in 3.2 and expect 3 interrupt-cells.
- Update the #interrupt-cells
- interrupt-parent seems to be needed as well for the top level GIC
Hmmm... it shouldn't be. If it is then it is a bug.

I think this is an old comment which I fixed in 3.2, so interrupt-parent can be removed.

Rob

Quoted 31 lines

Quoted 29 lines

Signed-off-by Benoit Cousson <[email protected]>

Cc Rob Herring <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

arch/arm/boot/dts/omap4.dtsi +2 -1

index 4c61c82..bede009 100644
@@ -95,7 +95,8 @@
 		gic: interrupt-controller at 48241000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
-			#interrupt-cells = <1>;
+			interrupt-parent;
+			#interrupt-cells = <3>;
 			reg = <0x48241000 0x1000>,
 			      <0x48240100 0x0100>;
 		};

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Cousson, Benoit

author

2012-01-09 13:31 UTC #4 lore raw

PATCH v2 1/5 arm/dts: OMAP4: Update DTS file with new GIC bindings

Quoted 10 lines · Rob Herring

Quoted 6 lines · Grant Likely
Quoted 3 lines · Benoit Cousson
The GIC binding was updated in 3.2 and expect 3 interrupt-cells.
- Update the #interrupt-cells
- interrupt-parent seems to be needed as well for the top level GIC
Hmmm... it shouldn't be. If it is then it is a bug.
I think this is an old comment which I fixed in 3.2, so interrupt-parent can be removed.

I've just tried, and indeed, it works now.

Please find below the patch updated accordingly.

Thanks,
Benoit

---

Quoted 1 line

From f9ebe0ff11e7cbbba0d7499420ff2f358e44a297 Mon Sep 17 00:00:00 2001

From: Benoit Cousson <[email protected]>
Date: Fri, 25 Nov 2011 12:11:52 +0100
Subject: [PATCH v3 1/5] arm/dts: OMAP4: Update DTS file with new GIC bindings

The GIC binding was updated in 3.2 and expects 3 interrupt-cells.
- Update the #interrupt-cells

Signed-off-by Benoit Cousson <[email protected]>

Acked-by Rob Herring <[email protected]>

---
 arch/arm/boot/dts/omap4.dtsi |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/boot/dts/omap4.dtsi +1 -1

index 4c61c82..4b2bff1 100644
@@ -95,7 +95,7 @@
 		gic: interrupt-controller at 48241000 {
 			compatible = "arm,cortex-a9-gic";
 			interrupt-controller;
-			#interrupt-cells = <1>;
+			#interrupt-cells = <3>;
 			reg = <0x48241000 0x1000>,
 			      <0x48240100 0x0100>;
 		};

Signature · 1 line

1.7.0.4

Benoit Cousson

author

2011-12-20 13:39 UTC #5 lore raw

PATCH v2 2/5 ARM: OMAP2/3: intc: Add irqdomain support

In reply to Benoit Cousson

Introduce the usage of the irqdomain to prepare the DT support. The irq_base is still hard coded to 0 to allow non-DT drivers to work with the previous assumption that was hwirq = irq.

Signed-off-by Benoit Cousson <[email protected]>

Cc Tony Lindgren <[email protected]>

Cc Rob Herring <[email protected]>

---
 arch/arm/mach-omap2/irq.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

arch/arm/mach-omap2/irq.c +17 -1

index 42b1d65..2f65dfd 100644
@@ -17,6 +17,7 @@
 #include <mach/hardware.h>
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
+#include <linux/irqdomain.h>
 
 
 /* selected INTC register offsets */

@@ -57,6 +58,8 @@ static struct omap_irq_bank {
 	},
 };
 
+static struct irq_domain domain;
+
 /* Structure to save interrupt controller context */
 struct omap3_intc_regs {
 	u32 sysconfig;

@@ -158,6 +161,17 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 	if (WARN_ON(!omap_irq_base))
 		return;
 
+	/*
+	 * XXX: Use a 0 irq_base for the moment since the legacy devices
+	 * created statically are expected a hwirq = irq mapping.
+	 * A proper offset will be added later, when IRQ resource creation
+	 * will be handled by DT.
+	 */
+	domain.irq_base = 0;
+	domain.nr_irq = nr_irqs;
+	domain.ops = &irq_domain_simple_ops;
+	irq_domain_add(&domain);
+
 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 		struct omap_irq_bank *bank = irq_banks + i;

@@ -225,8 +239,10 @@ out:
 		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
 		irqnr &= ACTIVEIRQ_MASK;
 
-		if (irqnr)
+		if (irqnr) {
+			irqnr = irq_domain_to_irq(&domain, irqnr);
 			handle_IRQ(irqnr, regs);
+		}
 	} while (irqnr);
 }

Signature · 1 line

1.7.0.4

Grant Likely

2012-01-06 21:22 UTC #6 lore raw

PATCH v2 2/5 ARM: OMAP2/3: intc: Add irqdomain support

Quoted 36 lines · Benoit Cousson

Introduce the usage of the irqdomain to prepare the DT support. The irq_base is still hard coded to 0 to allow non-DT drivers to work with the previous assumption that was hwirq = irq.
Signed-off-by Benoit Cousson <[email protected]>
Cc Tony Lindgren <[email protected]>
Cc Rob Herring <[email protected]>
---
 arch/arm/mach-omap2/irq.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)
arch/arm/mach-omap2/irq.c +3 -0
index 42b1d65..2f65dfd 100644
@@ -17,6 +17,7 @@
 #include <mach/hardware.h>
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
+#include <linux/irqdomain.h>
 
 
 /* selected INTC register offsets */
@@ -57,6 +58,8 @@ static struct omap_irq_bank {
 	},
 };
 
+static struct irq_domain domain;
+
 /* Structure to save interrupt controller context */
 struct omap3_intc_regs {
 	u32 sysconfig;
@@ -158,6 +161,17 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 	if (WARN_ON(!omap_irq_base))
 		return;
 

arch/arm/mach-omap2/irq.c static void __init omap_init_irq(u32 base, int nr_irqs) · line 173

Quoted 10 lines

arch/arm/mach-omap2/irq.c +10 -0

+	/*
+	 * XXX: Use a 0 irq_base for the moment since the legacy devices
+	 * created statically are expected a hwirq = irq mapping.
+	 * A proper offset will be added later, when IRQ resource creation
+	 * will be handled by DT.
+	 */
+	domain.irq_base = 0;
+	domain.nr_irq = nr_irqs;
+	domain.ops = &irq_domain_simple_ops;
+	irq_domain_add(&domain);

The omap doesn't need anything special from irq_domain. You can use irq_domain_add_simple(). A recent patch was posted that makes irq_domain_add_simple() accepts a nr_irqs parameter and returns the allocated irq domain.

However, that isn't enough reason for me to reject this patch if there is any opportunity to get it into v3.3 provided you promise to fix it up later.

Acked-by Grant Likely <[email protected]>

Quoted 24 lines

arch/arm/mach-omap2/irq.c +4 -1

+
 	for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
 		struct omap_irq_bank *bank = irq_banks + i;

@@ -225,8 +239,10 @@ out:
 		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
 		irqnr &= ACTIVEIRQ_MASK;
 
-		if (irqnr)
+		if (irqnr) {
+			irqnr = irq_domain_to_irq(&domain, irqnr);
 			handle_IRQ(irqnr, regs);
+		}
 	} while (irqnr);
 }

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Cousson, Benoit

author

2012-01-09 09:56 UTC #7 lore raw

PATCH v2 2/5 ARM: OMAP2/3: intc: Add irqdomain support

Hi Grant,

Quoted 1 line · Grant Likely

On Tue, Dec 20, 2011 at 02:39:55PM +0100, Benoit Cousson wrote:

[...]

Quoted 7 lines

arch/arm/mach-omap2/irq.c +7 -0

+	/*
+	 * XXX: Use a 0 irq_base for the moment since the legacy devices
+	 * created statically are expected a hwirq = irq mapping.
+	 * A proper offset will be added later, when IRQ resource creation
+	 * will be handled by DT.
+	 */
+	domain.irq_base = 0;

Quoted 8 lines

arch/arm/mach-omap2/irq.c static void __init omap_init_irq(u32 base, int nr_irqs) · line 173
Quoted 3 lines
arch/arm/mach-omap2/irq.c +3 -0
+	domain.nr_irq = nr_irqs;
+	domain.ops =&irq_domain_simple_ops;
+	irq_domain_add(&domain);
The omap doesn't need anything special from irq_domain. You can use irq_domain_add_simple(). A recent patch was posted that makes irq_domain_add_simple() accepts a nr_irqs parameter and returns the allocated irq domain.

Yes, I saw that, but in fact as discussed previously with Rob, even the irq_domain_add_simple should become useless when Rob's series to convert generic-chip to use irq_domain will be merged.

I have a patch ready for that, but like Nico for AT91, I decided to avoid that dependency for 3.3, since that series was not yet stable.

Quoted 3 lines

However, that isn't enough reason for me to reject this patch if there is any opportunity to get it into v3.3 provided you promise to fix it up later.

Yes, I do :-)

Quoted 1 line

Acked-by Grant Likely<[email protected]>

Thanks,
Benoit

Benoit Cousson

author

2011-12-20 13:39 UTC #8 lore raw

PATCH v2 3/5 ARM: OMAP2/3: intc: Add DT support for TI interrupt controller

In reply to Benoit Cousson

Add a function to initialize the OMAP2/3 interrupt controller (INTC) using a device tree node.

Replace some printk() with the proper pr_ macro.

Signed-off-by Benoit Cousson <[email protected]>

Cc Tony Lindgren <[email protected]>

Cc Rob Herring <[email protected]>

---
 .../devicetree/bindings/arm/omap/intc.txt          |   27 ++++++++++++++++++
 arch/arm/mach-omap2/common.h                       |   10 ++++++
 arch/arm/mach-omap2/irq.c                          |   30 ++++++++++++++++++--
 3 files changed, 64 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

Documentation/devicetree/bindings/arm/omap/intc.txt new file +27 -0

new file mode 100644
index 0000000..f2583e6
@@ -0,0 +1,27 @@
+* OMAP Interrupt Controller
+
+OMAP2/3 are using a TI interrupt controller that can support several
+configurable number of interrupts.
+
+Main node required properties:
+
+- compatible : should be:
+	"ti,omap2-intc"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 1.
+
+  The cell contains the interrupt number in the range [0-128].
+- ti,intc-size: Number of interrupts handled by the interrupt controller.
+- reg: physical base address and size of the intc registers map.
+
+Example:
+
+	intc: interrupt-controller at 1 {
+		compatible = "ti,omap2-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		ti,intc-size = <96>;
+		reg = <0x48200000 0x1000>;
+	};
+

arch/arm/mach-omap2/common.h +10 -0

index 012bac7..bcfccc2 100644
@@ -156,6 +156,16 @@ void omap3_intc_resume_idle(void);
 void omap2_intc_handle_irq(struct pt_regs *regs);
 void omap3_intc_handle_irq(struct pt_regs *regs);
 
+struct device_node;
+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node *parent);
+#else
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	return 0;
+}
+#endif
+
 /*
  * wfi used in low power code. Directly opcode is used instead
  * of instruction to avoid mulit-omap build break

arch/arm/mach-omap2/irq.c +27 -3

index 2f65dfd..f3722b1 100644
@@ -18,6 +18,8 @@
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 
 /* selected INTC register offsets */

@@ -180,7 +182,7 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 		/* Static mapping, never released */
 		bank->base_reg = ioremap(base, SZ_4K);
 		if (!bank->base_reg) {
-			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+			pr_err("Could not ioremap irq bank%i\n", i);
 			continue;
 		}

@@ -193,8 +195,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 		nr_banks++;
 	}
 
-	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+	pr_info("Total of %ld interrupts on %d active controller%s\n",
+		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 }
 
 void __init omap2_init_irq(void)

@@ -252,6 +254,28 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
 	omap_intc_handle_irq(base_addr, regs);
 }
 
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+	u32 nr_irqs = 96;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	if (of_address_to_resource(node, 0, &res)) {
+		WARN(1, "unable to get intc registers\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
+		pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
+
+	omap_init_irq(res.start, nr_irqs);
+	domain.of_node = of_node_get(node);
+
+	return 0;
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

Signature · 1 line

1.7.0.4

Grant Likely

2012-01-06 21:24 UTC #9 lore raw

PATCH v2 3/5 ARM: OMAP2/3: intc: Add DT support for TI interrupt controller

Quoted 8 lines · Benoit Cousson

Add a function to initialize the OMAP2/3 interrupt controller (INTC) using a device tree node.
Replace some printk() with the proper pr_ macro.
Signed-off-by Benoit Cousson <[email protected]>
Cc Tony Lindgren <[email protected]>
Cc Rob Herring <[email protected]>

Acked-by Grant Likely <[email protected]>

Quoted 131 lines

---
 .../devicetree/bindings/arm/omap/intc.txt          |   27 ++++++++++++++++++
 arch/arm/mach-omap2/common.h                       |   10 ++++++
 arch/arm/mach-omap2/irq.c                          |   30 ++++++++++++++++++--
 3 files changed, 64 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

Documentation/devicetree/bindings/arm/omap/intc.txt new file +27 -0

new file mode 100644
index 0000000..f2583e6
@@ -0,0 +1,27 @@
+* OMAP Interrupt Controller
+
+OMAP2/3 are using a TI interrupt controller that can support several
+configurable number of interrupts.
+
+Main node required properties:
+
+- compatible : should be:
+	"ti,omap2-intc"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 1.
+
+  The cell contains the interrupt number in the range [0-128].
+- ti,intc-size: Number of interrupts handled by the interrupt controller.
+- reg: physical base address and size of the intc registers map.
+
+Example:
+
+	intc: interrupt-controller at 1 {
+		compatible = "ti,omap2-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		ti,intc-size = <96>;
+		reg = <0x48200000 0x1000>;
+	};
+

arch/arm/mach-omap2/common.h +10 -0

index 012bac7..bcfccc2 100644
@@ -156,6 +156,16 @@ void omap3_intc_resume_idle(void);
 void omap2_intc_handle_irq(struct pt_regs *regs);
 void omap3_intc_handle_irq(struct pt_regs *regs);
 
+struct device_node;
+#ifdef CONFIG_OF
+int __init intc_of_init(struct device_node *node, struct device_node *parent);
+#else
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	return 0;
+}
+#endif
+
 /*
  * wfi used in low power code. Directly opcode is used instead
  * of instruction to avoid mulit-omap build break

arch/arm/mach-omap2/irq.c +27 -3

index 2f65dfd..f3722b1 100644
@@ -18,6 +18,8 @@
 #include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
 
 
 /* selected INTC register offsets */

@@ -180,7 +182,7 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 		/* Static mapping, never released */
 		bank->base_reg = ioremap(base, SZ_4K);
 		if (!bank->base_reg) {
-			printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
+			pr_err("Could not ioremap irq bank%i\n", i);
 			continue;
 		}

@@ -193,8 +195,8 @@ static void __init omap_init_irq(u32 base, int nr_irqs)
 		nr_banks++;
 	}
 
-	printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
-	       nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
+	pr_info("Total of %ld interrupts on %d active controller%s\n",
+		nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 }
 
 void __init omap2_init_irq(void)

@@ -252,6 +254,28 @@ asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs
 	omap_intc_handle_irq(base_addr, regs);
 }
 
+int __init intc_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+	u32 nr_irqs = 96;
+
+	if (WARN_ON(!node))
+		return -ENODEV;
+
+	if (of_address_to_resource(node, 0, &res)) {
+		WARN(1, "unable to get intc registers\n");
+		return -EINVAL;
+	}
+
+	if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
+		pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
+
+	omap_init_irq(res.start, nr_irqs);
+	domain.of_node = of_node_get(node);
+
+	return 0;
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];

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Benoit Cousson

author

2011-12-20 13:39 UTC #10 lore raw

PATCH v2 4/5 arm/dts: OMAP3: Add interrupt-controller bindings for INTC

In reply to Benoit Cousson

Update the DTS with the proper information required by the INTC bindings.

- Add the number of interrupt lines
- Add the reg and the compatible entries.

Signed-off-by Benoit Cousson <[email protected]>

Cc Rob Herring <[email protected]>

---
 arch/arm/boot/dts/omap3.dtsi |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

arch/arm/boot/dts/omap3.dtsi +4 -2

index d202bb5..6866dc7 100644
@@ -54,10 +54,12 @@
 		ranges;
 		ti,hwmods = "l3_main";
 
-		intc: interrupt-controller at 1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller at 48200000 {
+			compatible = "ti,omap2-intc";
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			ti,intc-size = <96>;
+			reg = <0x48200000 0x1000>;
 		};
 	};
 };

Signature · 1 line

1.7.0.4

Grant Likely

2012-01-06 21:24 UTC #11 lore raw

PATCH v2 4/5 arm/dts: OMAP3: Add interrupt-controller bindings for INTC

Quoted 8 lines · Benoit Cousson

Update the DTS with the proper information required by the INTC bindings.
- Add the number of interrupt lines
- Add the reg and the compatible entries.
Signed-off-by Benoit Cousson <[email protected]>
Cc Rob Herring <[email protected]>

Acked-by Grant Likely <[email protected]>

Quoted 31 lines

---
 arch/arm/boot/dts/omap3.dtsi |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

arch/arm/boot/dts/omap3.dtsi +4 -2

index d202bb5..6866dc7 100644
@@ -54,10 +54,12 @@
 		ranges;
 		ti,hwmods = "l3_main";
 
-		intc: interrupt-controller at 1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller at 48200000 {
+			compatible = "ti,omap2-intc";
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			ti,intc-size = <96>;
+			reg = <0x48200000 0x1000>;
 		};
 	};
 };

Signature · 7 lines

1.7.0.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Hiremath, Vaibhav

2012-01-13 06:14 UTC #12 lore raw

PATCH v2 4/5 arm/dts: OMAP3: Add interrupt-controller bindings for INTC

In reply to Benoit Cousson

Quoted 17 lines · Benoit

Update the DTS with the proper information required by the INTC bindings.
- Add the number of interrupt lines
- Add the reg and the compatible entries.
Signed-off-by Benoit Cousson <[email protected]>
Cc Rob Herring <[email protected]>
---
 arch/arm/boot/dts/omap3.dtsi |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)
arch/arm/boot/dts/omap3.dtsi +0 -0
index d202bb5..6866dc7 100644

arch/arm/boot/dts/omap3.dtsi line 61

Quoted 10 lines

arch/arm/boot/dts/omap3.dtsi +3 -2

@@ -54,10 +54,12 @@
 		ranges;
 		ti,hwmods = "l3_main";
 
-		intc: interrupt-controller at 1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller at 48200000 {
+			compatible = "ti,omap2-intc";
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			ti,intc-size = <96>;

Can we configure/change this field in platform specific .dts file? OR
Is there condition based configuration possible in DT?

To be specific,

I am adding support for AM335x EVM (using all your DT support patches), The device is considered as OMAP3 variant and when it comes to INTC support, I need to configure it to value "128", rest everything is same (including base add).

Can I do something like

File - am335x-evm.dts

/include/ "omap3.dtsi"

....
Again change the specific fields of " intc: interrupt-controller"?
....

How can this be handled?

Thanks,
Vaibhav

Quoted 12 lines

arch/arm/boot/dts/omap3.dtsi +1 -0

+			reg = <0x48200000 0x1000>;
 		};
 	};
 };

Signature · 6 lines

1.7.0.4

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Cousson, Benoit

author

2012-01-13 11:03 UTC #13 lore raw

PATCH v2 4/5 arm/dts: OMAP3: Add interrupt-controller bindings for INTC

Hi Vaibhav,

Quoted 1 line · Vaibhav

On Tue, Dec 20, 2011 at 19:09:57, Cousson, Benoit wrote:

[...]

Quoted 5 lines

Quoted 5 lines
+++ b/arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap3.dtsi +0 -0
@@ -54,10 +54,12 @@
  		ranges;
  		ti,hwmods = "l3_main";
 

Quoted 10 lines

arch/arm/boot/dts/omap3.dtsi
Quoted 7 lines
arch/arm/boot/dts/omap3.dtsi +3 -2
-		intc: interrupt-controller at 1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller at 48200000 {
+			compatible = "ti,omap2-intc";
  			interrupt-controller;
  			#interrupt-cells =<1>;
+			ti,intc-size =<96>;
Can we configure/change this field in platform specific .dts file? OR
Is there condition based configuration possible in DT?

I'm not sure to fully understand how your two options differ. Otherwise, yes the DT it can be configured, that why I exposed this attribute.
The intc code was already supporting the ti81xx with 128 lines as well, hence the need to make it configurable.
The other option was two handle that in the driver with 2 different compatible strings.

Quoted 7 lines

To be specific,
I am adding support for AM335x EVM (using all your DT support patches), The device is considered as OMAP3 variant and when it comes to INTC support, I need to configure it to value "128", rest everything is same (including base add).

Quoted 8 lines

Can I do something like
File - am335x-evm.dts
/include/ "omap3.dtsi"
....
Again change the specific fields of " intc: interrupt-controller"?

Yes.

Quoted 3 lines

....
How can this be handled?

After the include, you can redefine the node and the hierarchy:

+ ocp {
+ intc: interrupt-controller at 48200000 {
+ ti,intc-size = <128>;
+ };
...

or use the label directly:

+&intc: {
+ ti,intc-size =<128>;
+}

You can have a look at the way i2c or twl are using the include so far.

Regards,
Benoit

Hiremath, Vaibhav

2012-01-13 12:31 UTC #14 lore raw

PATCH v2 4/5 arm/dts: OMAP3: Add interrupt-controller bindings for INTC

Quoted 23 lines · Benoit

Hi Vaibhav,
Quoted 1 line · Vaibhav
On Tue, Dec 20, 2011 at 19:09:57, Cousson, Benoit wrote:
[...]
Quoted 5 lines
Quoted 5 lines
+++ b/arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap3.dtsi +0 -0
@@ -54,10 +54,12 @@
  		ranges;
  		ti,hwmods = "l3_main";
 
Quoted 10 lines
arch/arm/boot/dts/omap3.dtsi
Quoted 7 lines
arch/arm/boot/dts/omap3.dtsi +3 -2
-		intc: interrupt-controller at 1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller at 48200000 {
+			compatible = "ti,omap2-intc";
  			interrupt-controller;
  			#interrupt-cells =<1>;
+			ti,intc-size =<96>;
Can we configure/change this field in platform specific .dts file? OR
Is there condition based configuration possible in DT?

Quoted 5 lines

I'm not sure to fully understand how your two options differ. Otherwise, yes the DT it can be configured, that why I exposed this attribute.
The intc code was already supporting the ti81xx with 128 lines as well, hence the need to make it configurable.

I wanted to use DT configuration completely here, using existing omap_init_irq.
And I personally think, lets not use different implementation only because number of interrupts are different.

Quoted 39 lines

The other option was two handle that in the driver with 2 different compatible strings.
Quoted 7 lines
To be specific,
I am adding support for AM335x EVM (using all your DT support patches), The device is considered as OMAP3 variant and when it comes to INTC support, I need to configure it to value "128", rest everything is same (including base add).
Quoted 8 lines
Can I do something like
File - am335x-evm.dts
/include/ "omap3.dtsi"
....
Again change the specific fields of " intc: interrupt-controller"?
Yes.
Quoted 3 lines
....
How can this be handled?
After the include, you can redefine the node and the hierarchy:
(quoted diff) +4 -0
+	ocp {
+		intc: interrupt-controller at 48200000 {
+			ti,intc-size = <128>;
+		};
...
or use the label directly:
+&intc: {
(quoted diff) +2 -0
+	ti,intc-size =<128>;
+}

Quoted 2 lines

You can have a look at the way i2c or twl are using the include so far.

Thanks, I will trying this now...
And if it works, then I can submit the patches...

Thanks,
Vaibhav

Quoted 3 lines

Regards,
Benoit

Cousson, Benoit

author

2012-01-13 13:01 UTC #15 lore raw

PATCH v2 4/5 arm/dts: OMAP3: Add interrupt-controller bindings for INTC

Quoted 30 lines · Vaibhav

Quoted 23 lines · Benoit
Hi Vaibhav,
Quoted 1 line · Vaibhav
On Tue, Dec 20, 2011 at 19:09:57, Cousson, Benoit wrote:
[...]
Quoted 5 lines
Quoted 5 lines
+++ b/arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap3.dtsi +0 -0
@@ -54,10 +54,12 @@
   		ranges;
   		ti,hwmods = "l3_main";
 
Quoted 10 lines
arch/arm/boot/dts/omap3.dtsi
Quoted 7 lines
arch/arm/boot/dts/omap3.dtsi +3 -2
-		intc: interrupt-controller at 1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller at 48200000 {
+			compatible = "ti,omap2-intc";
   			interrupt-controller;
   			#interrupt-cells =<1>;
+			ti,intc-size =<96>;
Can we configure/change this field in platform specific .dts file? OR
Is there condition based configuration possible in DT?
Quoted 5 lines
I'm not sure to fully understand how your two options differ. Otherwise, yes the DT it can be configured, that why I exposed this attribute.
The intc code was already supporting the ti81xx with 128 lines as well, hence the need to make it configurable.

Quoted 4 lines

I wanted to use DT configuration completely here, using existing omap_init_irq.
And I personally think, lets not use different implementation only because number of interrupts are different.

Sure, that was the goal of that binding. Anyway, my point was that the driver was already generic enough to handle OMAP2, OMAP3 and TI81xx.

Quoted 35 lines

Quoted 35 lines
The other option was two handle that in the driver with 2 different compatible strings.
Quoted 7 lines
To be specific,
I am adding support for AM335x EVM (using all your DT support patches), The device is considered as OMAP3 variant and when it comes to INTC support, I need to configure it to value "128", rest everything is same (including base add).
Quoted 8 lines
Can I do something like
File - am335x-evm.dts
/include/ "omap3.dtsi"
....
Again change the specific fields of " intc: interrupt-controller"?
Yes.
Quoted 3 lines
....
How can this be handled?
After the include, you can redefine the node and the hierarchy:
(quoted diff) +4 -0
+	ocp {
+		intc: interrupt-controller at 48200000 {
+			ti,intc-size =<128>;
+		};
...
or use the label directly:

Quoted 8 lines

Quoted 6 lines
+&intc: {
(quoted diff) +2 -0
+	ti,intc-size =<128>;
+}
You can have a look at the way i2c or twl are using the include so far.
Thanks, I will trying this now...
And if it works, then I can submit the patches...

Well, it should in theory :-)

Regards,
Benoit

Hiremath, Vaibhav

2012-01-13 14:27 UTC #16 lore raw

PATCH v2 4/5 arm/dts: OMAP3: Add interrupt-controller bindings for INTC

Quoted 78 lines · Benoit

Quoted 30 lines · Vaibhav
Quoted 23 lines · Benoit
Hi Vaibhav,
Quoted 1 line · Vaibhav
On Tue, Dec 20, 2011 at 19:09:57, Cousson, Benoit wrote:
[...]
Quoted 5 lines
Quoted 5 lines
+++ b/arch/arm/boot/dts/omap3.dtsi
arch/arm/boot/dts/omap3.dtsi +0 -0
@@ -54,10 +54,12 @@
   		ranges;
   		ti,hwmods = "l3_main";
 
Quoted 10 lines
arch/arm/boot/dts/omap3.dtsi
Quoted 7 lines
arch/arm/boot/dts/omap3.dtsi +3 -2
-		intc: interrupt-controller at 1 {
-			compatible = "ti,omap3-intc";
+		intc: interrupt-controller at 48200000 {
+			compatible = "ti,omap2-intc";
   			interrupt-controller;
   			#interrupt-cells =<1>;
+			ti,intc-size =<96>;
Can we configure/change this field in platform specific .dts file? OR
Is there condition based configuration possible in DT?
Quoted 5 lines
I'm not sure to fully understand how your two options differ. Otherwise, yes the DT it can be configured, that why I exposed this attribute.
The intc code was already supporting the ti81xx with 128 lines as well, hence the need to make it configurable.
Quoted 4 lines
I wanted to use DT configuration completely here, using existing omap_init_irq.
And I personally think, lets not use different implementation only because number of interrupts are different.
Sure, that was the goal of that binding. Anyway, my point was that the driver was already generic enough to handle OMAP2, OMAP3 and TI81xx.
Quoted 39 lines
Quoted 39 lines
The other option was two handle that in the driver with 2 different compatible strings.
Quoted 7 lines
To be specific,
I am adding support for AM335x EVM (using all your DT support patches), The device is considered as OMAP3 variant and when it comes to INTC support, I need to configure it to value "128", rest everything is same (including base add).
Quoted 8 lines
Can I do something like
File - am335x-evm.dts
/include/ "omap3.dtsi"
....
Again change the specific fields of " intc: interrupt-controller"?
Yes.
Quoted 3 lines
....
How can this be handled?
After the include, you can redefine the node and the hierarchy:
(quoted diff) +4 -0
+	ocp {
+		intc: interrupt-controller at 48200000 {
+			ti,intc-size =<128>;
+		};
...
or use the label directly:
+&intc: {
(quoted diff) +2 -0
+	ti,intc-size =<128>;
+}

Quoted 7 lines

Quoted 4 lines
Quoted 2 lines
You can have a look at the way i2c or twl are using the include so far.
Thanks, I will trying this now...
And if it works, then I can submit the patches...
Well, it should in theory :-)

Thanks Benoit, it is working. Submitting patches now...

Thanks,
Vaibhav

Quoted 3 lines

Regards,
Benoit

Benoit Cousson

author

2011-12-20 13:39 UTC #17 lore raw

PATCH v2 5/5 ARM: OMAP2+: board-generic: Use of_irq_init API

In reply to Benoit Cousson

Use the of_irq_init API introduced in 3.2 to handle interrupt-controller with DT.
Update the irq_match table to map the proper XXX_of_init functions for INTC and GIC drivers.

Signed-off-by Benoit Cousson <[email protected]>

Cc Tony Lindgren <[email protected]>

Cc Rob Herring <[email protected]>

---
 arch/arm/mach-omap2/board-generic.c |   30 ++++++++++++++++--------------
 1 files changed, 16 insertions(+), 14 deletions(-)

arch/arm/mach-omap2/board-generic.c +16 ~~-14~~

index e493877..2529017 100644
@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/io.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>

@@ -24,6 +25,17 @@
 #include "common.h"
 #include "common-board-devices.h"
 
+static struct of_device_id irq_match[] __initdata = {
+	{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ }
+};
+
+static void __init omap_init_irq(void)
+{
+	of_irq_init(irq_match);
+}
+
 /*
  * XXX: Still needed to boot until the i2c & twl driver is adapted to
  * device-tree

@@ -58,18 +70,8 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
 	{ }
 };
 
-static struct of_device_id intc_match[] __initdata = {
-	{ .compatible = "ti,omap3-intc", },
-	{ .compatible = "arm,cortex-a9-gic", },
-	{ }
-};
-
 static void __init omap_generic_init(void)
 {
-	struct device_node *node = of_find_matching_node(NULL, intc_match);
-	if (node)
-		irq_domain_add_simple(node, 0);
-
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);

@@ -103,7 +105,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
-	.init_irq	= omap2_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,

@@ -122,7 +124,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap243x_map_io,
 	.init_early	= omap2430_init_early,
-	.init_irq	= omap2_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,

@@ -141,7 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
-	.init_irq	= omap3_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_init,
 	.timer		= &omap3_timer,

@@ -160,7 +162,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap4_map_io,
 	.init_early	= omap4430_init_early,
-	.init_irq	= gic_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap4_init,
 	.timer		= &omap4_timer,

Signature · 1 line

1.7.0.4

Grant Likely

2012-01-06 21:25 UTC #18 lore raw

PATCH v2 5/5 ARM: OMAP2+: board-generic: Use of_irq_init API

Quoted 8 lines · Benoit Cousson

Use the of_irq_init API introduced in 3.2 to handle interrupt-controller with DT.
Update the irq_match table to map the proper XXX_of_init functions for INTC and GIC drivers.
Signed-off-by Benoit Cousson <[email protected]>
Cc Tony Lindgren <[email protected]>
Cc Rob Herring <[email protected]>

Acked-by Grant Likely <[email protected]>

Quoted 97 lines

---
 arch/arm/mach-omap2/board-generic.c |   30 ++++++++++++++++--------------
 1 files changed, 16 insertions(+), 14 deletions(-)

arch/arm/mach-omap2/board-generic.c +16 ~~-14~~

index e493877..2529017 100644
@@ -12,6 +12,7 @@
  * published by the Free Software Foundation.
  */
 #include <linux/io.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/irqdomain.h>
 #include <linux/i2c/twl.h>

@@ -24,6 +25,17 @@
 #include "common.h"
 #include "common-board-devices.h"
 
+static struct of_device_id irq_match[] __initdata = {
+	{ .compatible = "ti,omap2-intc", .data = intc_of_init, },
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ }
+};
+
+static void __init omap_init_irq(void)
+{
+	of_irq_init(irq_match);
+}
+
 /*
  * XXX: Still needed to boot until the i2c & twl driver is adapted to
  * device-tree

@@ -58,18 +70,8 @@ static struct of_device_id omap_dt_match_table[] __initdata = {
 	{ }
 };
 
-static struct of_device_id intc_match[] __initdata = {
-	{ .compatible = "ti,omap3-intc", },
-	{ .compatible = "arm,cortex-a9-gic", },
-	{ }
-};
-
 static void __init omap_generic_init(void)
 {
-	struct device_node *node = of_find_matching_node(NULL, intc_match);
-	if (node)
-		irq_domain_add_simple(node, 0);
-
 	omap_serial_init();
 	omap_sdrc_init(NULL, NULL);

@@ -103,7 +105,7 @@ DT_MACHINE_START(OMAP242X_DT, "Generic OMAP2420 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
-	.init_irq	= omap2_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,

@@ -122,7 +124,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap243x_map_io,
 	.init_early	= omap2430_init_early,
-	.init_irq	= omap2_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,

@@ -141,7 +143,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
-	.init_irq	= omap3_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_init,
 	.timer		= &omap3_timer,

@@ -160,7 +162,7 @@ DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)")
 	.reserve	= omap_reserve,
 	.map_io		= omap4_map_io,
 	.init_early	= omap4430_init_early,
-	.init_irq	= gic_init_irq,
+	.init_irq	= omap_init_irq,
 	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap4_init,
 	.timer		= &omap4_timer,

Signature · 7 lines

1.7.0.4


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Cousson, Benoit

author

2011-12-23 09:46 UTC #19 lore raw

v2 cover ARM: OMAP2+: Interrupt controllers adaptation to DT

In reply to Benoit Cousson

Hi Rob,

Are you OK with that update?

Thanks,
Benoit

Quoted 41 lines · Benoit Cousson

Hi Tony and Rob,
Here is the series to take advantage of the new DT interrupt init mechanism. Thanks to Marc's CONFIG_MULTI_IRQ_HANDLER series, OMAP4 just has to use the default GIC binding and does not need some OMAP specific hacks anymore. OMAP2 and 3 are using a simple interrupt controller that can thus expose a simpler binding.
This update, compared to v1 [1], is introducing the IRQ domain for the OMAP2&3 INTC by default for both DT and none-DT build.
Please note that in the near future that code can even be simplier with the introduction of the domain support inside generic irq chip.
This series is based on lo/dt branch to get the needed cleanup and fixes for OMAP.
The series is available here for reference:
git://gitorious.org/omap-pm/linux.git for_3.3/2_dt_irq
Regards,
Benoit
[1] http://www.spinics.net/lists/linux-omap/msg61152.html
Benoit Cousson (5):
arm/dts: OMAP4: Update DTS file with new GIC bindings
ARM: OMAP2/3: intc: Add irqdomain support
ARM: OMAP2/3: intc: Add DT support for TI interrupt controller arm/dts: OMAP3: Add interrupt-controller bindings for INTC
ARM: OMAP2+: board-generic: Use of_irq_init API
  .../devicetree/bindings/arm/omap/intc.txt          |   27 +++++++++++
  arch/arm/boot/dts/omap3.dtsi                       |    6 ++-
  arch/arm/boot/dts/omap4.dtsi                       |    3 +-
  arch/arm/mach-omap2/board-generic.c                |   30 +++++++------
  arch/arm/mach-omap2/common.h                       |   10 ++++
  arch/arm/mach-omap2/irq.c                          |   48 ++++++++++++++++++--
  6 files changed, 103 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

Cousson, Benoit

author

2012-01-06 16:38 UTC #20 lore raw

v2 cover ARM: OMAP2+: Interrupt controllers adaptation to DT

Hi Rob/Grant,

Gentle ping on that series too. This should the last one:-)

Thanks,
Benoit

Quoted 54 lines · Benoit

Hi Rob,
Are you OK with that update?
Thanks,
Benoit
Quoted 45 lines · Benoit Cousson
Hi Tony and Rob,
Here is the series to take advantage of the new DT interrupt init mechanism.
Thanks to Marc's CONFIG_MULTI_IRQ_HANDLER series, OMAP4 just has to use the
default GIC binding and does not need some OMAP specific hacks anymore. OMAP2 and 3 are using a simple interrupt controller that can thus expose a simpler binding.
This update, compared to v1 [1], is introducing the IRQ domain for the OMAP2&3 INTC by default for both DT and none-DT build. Please note that in the near future that code can even be simplier with the
introduction of the domain support inside generic irq chip.
This series is based on lo/dt branch to get the needed cleanup and fixes for
OMAP.
The series is available here for reference:
git://gitorious.org/omap-pm/linux.git for_3.3/2_dt_irq
Regards,
Benoit
[1] http://www.spinics.net/lists/linux-omap/msg61152.html
Benoit Cousson (5):
arm/dts: OMAP4: Update DTS file with new GIC bindings
ARM: OMAP2/3: intc: Add irqdomain support
ARM: OMAP2/3: intc: Add DT support for TI interrupt controller arm/dts: OMAP3: Add interrupt-controller bindings for INTC
ARM: OMAP2+: board-generic: Use of_irq_init API
.../devicetree/bindings/arm/omap/intc.txt | 27 +++++++++++ arch/arm/boot/dts/omap3.dtsi | 6 ++- arch/arm/boot/dts/omap4.dtsi | 3 +- arch/arm/mach-omap2/board-generic.c | 30 +++++++------ arch/arm/mach-omap2/common.h | 10 ++++ arch/arm/mach-omap2/irq.c | 48 ++++++++++++++++++--
6 files changed, 103 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt

Rob Herring

2012-01-06 18:56 UTC #21 lore raw

v2 cover ARM: OMAP2+: Interrupt controllers adaptation to DT

Quoted 4 lines · Benoit

Hi Rob/Grant,
Gentle ping on that series too. This should the last one:-)

Sorry about that. For the series:

Acked-by Rob Herring <[email protected]>

Rob

Quoted 63 lines

Thanks,
Benoit
Quoted 54 lines · Benoit
Hi Rob,
Are you OK with that update?
Thanks,
Benoit
Quoted 45 lines · Benoit Cousson
Hi Tony and Rob,
Here is the series to take advantage of the new DT interrupt init mechanism.
Thanks to Marc's CONFIG_MULTI_IRQ_HANDLER series, OMAP4 just has to use the
default GIC binding and does not need some OMAP specific hacks anymore. OMAP2 and 3 are using a simple interrupt controller that can thus expose a simpler binding.
This update, compared to v1 [1], is introducing the IRQ domain for the OMAP2&3 INTC by default for both DT and none-DT build. Please note that in the near future that code can even be simplier with the
introduction of the domain support inside generic irq chip.
This series is based on lo/dt branch to get the needed cleanup and fixes for
OMAP.
The series is available here for reference:
git://gitorious.org/omap-pm/linux.git for_3.3/2_dt_irq
Regards,
Benoit
[1] http://www.spinics.net/lists/linux-omap/msg61152.html
Benoit Cousson (5):
arm/dts: OMAP4: Update DTS file with new GIC bindings
ARM: OMAP2/3: intc: Add irqdomain support
ARM: OMAP2/3: intc: Add DT support for TI interrupt controller arm/dts: OMAP3: Add interrupt-controller bindings for INTC
ARM: OMAP2+: board-generic: Use of_irq_init API
.../devicetree/bindings/arm/omap/intc.txt | 27 +++++++++++ arch/arm/boot/dts/omap3.dtsi | 6 ++- arch/arm/boot/dts/omap4.dtsi | 3 +- arch/arm/mach-omap2/board-generic.c | 30 +++++++------ arch/arm/mach-omap2/common.h | 10 ++++ arch/arm/mach-omap2/irq.c | 48 ++++++++++++++++++--
6 files changed, 103 insertions(+), 21 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/omap/intc.txt
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