i.mx6: mx6x_pins: Fix uart txd definitions

PATCH New Dirk Behme 3 participants 8 messages Jan 13, 2012 – Jan 17, 2012 Arm (32-bit)

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Dirk Behme

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2012-01-13 09:49 UTC #0 lore raw

PATCH 1/1 i.mx6: mx6x_pins: Fix uart txd definitions

From: Troy Kisky <[email protected]>

The uart txd pad can also provide the rxd function. But it does not stop its tx role. This could be used for a half duplex serial port.

Change names to reduce confusion.

Signed-off-by Troy Kisky <[email protected]>

CC Troy Kisky <[email protected]>

CC Jason Liu <[email protected]>

CC Stefano Babic <[email protected]>

---
Note: tools/checkpatch.pl reports various 'WARNING: line over 80 characters'
on this patch. But keep this to be consistent with the other pinmux definitions.

 arch/arm/include/asm/arch-mx6/mx6x_pins.h |   36 +++++++++-------------------
 1 files changed, 12 insertions(+), 24 deletions(-)

arch/arm/include/asm/arch-mx6/mx6x_pins.h +12 ~~-24~~

index b3f613c..afaa068 100644
@@ -220,7 +220,7 @@ enum {
 	MX6Q_PAD_EIM_D24__WEIM_WEIM_D_24	= IOMUX_PAD(0x03C8, 0x00B4, 0, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D24__ECSPI4_SS2		= IOMUX_PAD(0x03C8, 0x00B4, 1, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D24__UART3_TXD		= IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0000, 0, 0),
-	MX6Q_PAD_EIM_D24__UART3_RXD		= IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
+	MX6Q_PAD_EIM_D24__UART3_TXD_RXD		= IOMUX_PAD(0x03C8, 0x00B4, 2, 0x0930, 0, 0),
 	MX6Q_PAD_EIM_D24__ECSPI1_SS2		= IOMUX_PAD(0x03C8, 0x00B4, 3, 0x0808, 0, 0),
 	MX6Q_PAD_EIM_D24__ECSPI2_SS2		= IOMUX_PAD(0x03C8, 0x00B4, 4, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D24__GPIO_3_24		= IOMUX_PAD(0x03C8, 0x00B4, 5, 0x0000, 0, 0),

@@ -228,7 +228,6 @@ enum {
 	MX6Q_PAD_EIM_D24__UART1_DTR		= IOMUX_PAD(0x03C8, 0x00B4, 7, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D25__WEIM_WEIM_D_25	= IOMUX_PAD(0x03CC, 0x00B8, 0, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D25__ECSPI4_SS3		= IOMUX_PAD(0x03CC, 0x00B8, 1, 0x0000, 0, 0),
-	MX6Q_PAD_EIM_D25__UART3_TXD		= IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D25__UART3_RXD		= IOMUX_PAD(0x03CC, 0x00B8, 2, 0x0930, 1, 0),
 	MX6Q_PAD_EIM_D25__ECSPI1_SS3		= IOMUX_PAD(0x03CC, 0x00B8, 3, 0x080C, 0, 0),
 	MX6Q_PAD_EIM_D25__ECSPI2_SS3		= IOMUX_PAD(0x03CC, 0x00B8, 4, 0x0000, 0, 0),

@@ -240,7 +239,7 @@ enum {
 	MX6Q_PAD_EIM_D26__IPU1_CSI0_D_1		= IOMUX_PAD(0x03D0, 0x00BC, 2, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D26__IPU2_CSI1_D_14	= IOMUX_PAD(0x03D0, 0x00BC, 3, 0x08C0, 0, 0),
 	MX6Q_PAD_EIM_D26__UART2_TXD		= IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0000, 0, 0),
-	MX6Q_PAD_EIM_D26__UART2_RXD		= IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
+	MX6Q_PAD_EIM_D26__UART2_TXD_RXD		= IOMUX_PAD(0x03D0, 0x00BC, 4, 0x0928, 0, 0),
 	MX6Q_PAD_EIM_D26__GPIO_3_26		= IOMUX_PAD(0x03D0, 0x00BC, 5, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D26__IPU1_SISG_2		= IOMUX_PAD(0x03D0, 0x00BC, 6, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D26__IPU1_DISP1_DAT_22	= IOMUX_PAD(0x03D0, 0x00BC, 7, 0x0000, 0, 0),

@@ -248,7 +247,6 @@ enum {
 	MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13	= IOMUX_PAD(0x03D4, 0x00C0, 1, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D27__IPU1_CSI0_D_0		= IOMUX_PAD(0x03D4, 0x00C0, 2, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D27__IPU2_CSI1_D_13	= IOMUX_PAD(0x03D4, 0x00C0, 3, 0x08BC, 0, 0),
-	MX6Q_PAD_EIM_D27__UART2_TXD		= IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D27__UART2_RXD		= IOMUX_PAD(0x03D4, 0x00C0, 4, 0x0928, 1, 0),
 	MX6Q_PAD_EIM_D27__GPIO_3_27		= IOMUX_PAD(0x03D4, 0x00C0, 5, 0x0000, 0, 0),
 	MX6Q_PAD_EIM_D27__IPU1_SISG_3		= IOMUX_PAD(0x03D4, 0x00C0, 6, 0x0000, 0, 0),

@@ -938,7 +936,7 @@ enum {
 	MX6Q_PAD_KEY_COL0__AUDMUX_AUD5_TXC	= IOMUX_PAD(0x05C8, 0x01F8, 2, 0x07DC, 1, 0),
 	MX6Q_PAD_KEY_COL0__KPP_COL_0		= IOMUX_PAD(0x05C8, 0x01F8, 3, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_COL0__UART4_TXD		= IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0000, 0, 0),
-	MX6Q_PAD_KEY_COL0__UART4_RXD		= IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
+	MX6Q_PAD_KEY_COL0__UART4_TXD_RXD	= IOMUX_PAD(0x05C8, 0x01F8, 4, 0x0938, 0, 0),
 	MX6Q_PAD_KEY_COL0__GPIO_4_6		= IOMUX_PAD(0x05C8, 0x01F8, 5, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_COL0__DCIC1_DCIC_OUT	= IOMUX_PAD(0x05C8, 0x01F8, 6, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_COL0__SRC_ANY_PU_RST	= IOMUX_PAD(0x05C8, 0x01F8, 7, 0x0000, 0, 0),

@@ -946,7 +944,6 @@ enum {
 	MX6Q_PAD_KEY_ROW0__ENET_TDATA_3		= IOMUX_PAD(0x05CC, 0x01FC, 1, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_ROW0__AUDMUX_AUD5_TXD	= IOMUX_PAD(0x05CC, 0x01FC, 2, 0x07D0, 1, 0),
 	MX6Q_PAD_KEY_ROW0__KPP_ROW_0		= IOMUX_PAD(0x05CC, 0x01FC, 3, 0x0000, 0, 0),
-	MX6Q_PAD_KEY_ROW0__UART4_TXD		= IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_ROW0__UART4_RXD		= IOMUX_PAD(0x05CC, 0x01FC, 4, 0x0938, 1, 0),
 	MX6Q_PAD_KEY_ROW0__GPIO_4_7		= IOMUX_PAD(0x05CC, 0x01FC, 5, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_ROW0__DCIC2_DCIC_OUT	= IOMUX_PAD(0x05CC, 0x01FC, 6, 0x0000, 0, 0),

@@ -956,7 +953,7 @@ enum {
 	MX6Q_PAD_KEY_COL1__AUDMUX_AUD5_TXFS	= IOMUX_PAD(0x05D0, 0x0200, 2, 0x07E0, 1, 0),
 	MX6Q_PAD_KEY_COL1__KPP_COL_1		= IOMUX_PAD(0x05D0, 0x0200, 3, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_COL1__UART5_TXD		= IOMUX_PAD(0x05D0, 0x0200, 4, 0x0000, 0, 0),
-	MX6Q_PAD_KEY_COL1__UART5_RXD		= IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
+	MX6Q_PAD_KEY_COL1__UART5_TXD_RXD	= IOMUX_PAD(0x05D0, 0x0200, 4, 0x0940, 0, 0),
 	MX6Q_PAD_KEY_COL1__GPIO_4_8		= IOMUX_PAD(0x05D0, 0x0200, 5, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_COL1__USDHC1_VSELECT	= IOMUX_PAD(0x05D0, 0x0200, 6, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_COL1__PL301MX_PER1_HADR_1	= IOMUX_PAD(0x05D0, 0x0200, 7, 0x0000, 0, 0),

@@ -964,7 +961,6 @@ enum {
 	MX6Q_PAD_KEY_ROW1__ENET_COL		= IOMUX_PAD(0x05D4, 0x0204, 1, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_ROW1__AUDMUX_AUD5_RXD	= IOMUX_PAD(0x05D4, 0x0204, 2, 0x07CC, 1, 0),
 	MX6Q_PAD_KEY_ROW1__KPP_ROW_1		= IOMUX_PAD(0x05D4, 0x0204, 3, 0x0000, 0, 0),
-	MX6Q_PAD_KEY_ROW1__UART5_TXD		= IOMUX_PAD(0x05D4, 0x0204, 4, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_ROW1__UART5_RXD		= IOMUX_PAD(0x05D4, 0x0204, 4, 0x0940, 1, 0),
 	MX6Q_PAD_KEY_ROW1__GPIO_4_9		= IOMUX_PAD(0x05D4, 0x0204, 5, 0x0000, 0, 0),
 	MX6Q_PAD_KEY_ROW1__USDHC2_VSELECT	= IOMUX_PAD(0x05D4, 0x0204, 6, 0x0000, 0, 0),

@@ -1085,7 +1081,7 @@ enum {
 	MX6Q_PAD_GPIO_7__EPIT1_EPITO		= IOMUX_PAD(0x0610, 0x0240, 2, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_7__CAN1_TXCAN		= IOMUX_PAD(0x0610, 0x0240, 3, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_7__UART2_TXD		= IOMUX_PAD(0x0610, 0x0240, 4, 0x0000, 0, 0),
-	MX6Q_PAD_GPIO_7__UART2_RXD		= IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
+	MX6Q_PAD_GPIO_7__UART2_TXD_RXD		= IOMUX_PAD(0x0610, 0x0240, 4, 0x0928, 2, 0),
 	MX6Q_PAD_GPIO_7__GPIO_1_7		= IOMUX_PAD(0x0610, 0x0240, 5, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_7__SPDIF_PLOCK		= IOMUX_PAD(0x0610, 0x0240, 6, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_7__USBOH3_OTGUSB_HST_MODE	= IOMUX_PAD(0x0610, 0x0240, 7, 0x0000, 0, 0),

@@ -1093,7 +1089,6 @@ enum {
 	MX6Q_PAD_GPIO_8__ANATOP_ANATOP_32K_OUT	= IOMUX_PAD(0x0614, 0x0244, 1, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_8__EPIT2_EPITO		= IOMUX_PAD(0x0614, 0x0244, 2, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_8__CAN1_RXCAN		= IOMUX_PAD(0x0614, 0x0244, 3, 0x07E4, 1, 0),
-	MX6Q_PAD_GPIO_8__UART2_TXD		= IOMUX_PAD(0x0614, 0x0244, 4, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_8__UART2_RXD		= IOMUX_PAD(0x0614, 0x0244, 4, 0x0928, 3, 0),
 	MX6Q_PAD_GPIO_8__GPIO_1_8		= IOMUX_PAD(0x0614, 0x0244, 5, 0x0000, 0, 0),
 	MX6Q_PAD_GPIO_8__SPDIF_SRCLK		= IOMUX_PAD(0x0614, 0x0244, 6, 0x0000, 0, 0),

@@ -1208,7 +1203,7 @@ enum {
 	MX6Q_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC	= IOMUX_PAD(0x0650, 0x0280, 1, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO	= IOMUX_PAD(0x0650, 0x0280, 2, 0x0814, 2, 0),
 	MX6Q_PAD_CSI0_DAT10__UART1_TXD		= IOMUX_PAD(0x0650, 0x0280, 3, 0x0000, 0, 0),
-	MX6Q_PAD_CSI0_DAT10__UART1_RXD		= IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
+	MX6Q_PAD_CSI0_DAT10__UART1_TXD_RXD	= IOMUX_PAD(0x0650, 0x0280, 3, 0x0920, 0, 0),
 	MX6Q_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4	= IOMUX_PAD(0x0650, 0x0280, 4, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT10__GPIO_5_28		= IOMUX_PAD(0x0650, 0x0280, 5, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT10__MMDC_MMDC_DEBUG_33	= IOMUX_PAD(0x0650, 0x0280, 6, 0x0000, 0, 0),

@@ -1216,7 +1211,6 @@ enum {
 	MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11	= IOMUX_PAD(0x0654, 0x0284, 0, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT11__AUDMUX_AUD3_RXFS	= IOMUX_PAD(0x0654, 0x0284, 1, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0		= IOMUX_PAD(0x0654, 0x0284, 2, 0x081C, 2, 0),
-	MX6Q_PAD_CSI0_DAT11__UART1_TXD		= IOMUX_PAD(0x0654, 0x0284, 3, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT11__UART1_RXD		= IOMUX_PAD(0x0654, 0x0284, 3, 0x0920, 1, 0),
 	MX6Q_PAD_CSI0_DAT11__SDMA_DEBUG_PC_5	= IOMUX_PAD(0x0654, 0x0284, 4, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT11__GPIO_5_29		= IOMUX_PAD(0x0654, 0x0284, 5, 0x0000, 0, 0),

@@ -1226,7 +1220,7 @@ enum {
 	MX6Q_PAD_CSI0_DAT12__WEIM_WEIM_D_8	= IOMUX_PAD(0x0658, 0x0288, 1, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT12__PCIE_CTRL_MUX_16	= IOMUX_PAD(0x0658, 0x0288, 2, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT12__UART4_TXD		= IOMUX_PAD(0x0658, 0x0288, 3, 0x0000, 0, 0),
-	MX6Q_PAD_CSI0_DAT12__UART4_RXD		= IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
+	MX6Q_PAD_CSI0_DAT12__UART4_TXD_RXD	= IOMUX_PAD(0x0658, 0x0288, 3, 0x0938, 2, 0),
 	MX6Q_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6	= IOMUX_PAD(0x0658, 0x0288, 4, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT12__GPIO_5_30		= IOMUX_PAD(0x0658, 0x0288, 5, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT12__MMDC_MMDC_DEBUG_35	= IOMUX_PAD(0x0658, 0x0288, 6, 0x0000, 0, 0),

@@ -1234,7 +1228,6 @@ enum {
 	MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13	= IOMUX_PAD(0x065C, 0x028C, 0, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT13__WEIM_WEIM_D_9	= IOMUX_PAD(0x065C, 0x028C, 1, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT13__PCIE_CTRL_MUX_17	= IOMUX_PAD(0x065C, 0x028C, 2, 0x0000, 0, 0),
-	MX6Q_PAD_CSI0_DAT13__UART4_TXD		= IOMUX_PAD(0x065C, 0x028C, 3, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT13__UART4_RXD		= IOMUX_PAD(0x065C, 0x028C, 3, 0x0938, 3, 0),
 	MX6Q_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7	= IOMUX_PAD(0x065C, 0x028C, 4, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT13__GPIO_5_31		= IOMUX_PAD(0x065C, 0x028C, 5, 0x0000, 0, 0),

@@ -1244,7 +1237,7 @@ enum {
 	MX6Q_PAD_CSI0_DAT14__WEIM_WEIM_D_10	= IOMUX_PAD(0x0660, 0x0290, 1, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT14__PCIE_CTRL_MUX_18	= IOMUX_PAD(0x0660, 0x0290, 2, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT14__UART5_TXD		= IOMUX_PAD(0x0660, 0x0290, 3, 0x0000, 0, 0),
-	MX6Q_PAD_CSI0_DAT14__UART5_RXD		= IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
+	MX6Q_PAD_CSI0_DAT14__UART5_TXD_RXD	= IOMUX_PAD(0x0660, 0x0290, 3, 0x0940, 2, 0),
 	MX6Q_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8	= IOMUX_PAD(0x0660, 0x0290, 4, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT14__GPIO_6_0		= IOMUX_PAD(0x0660, 0x0290, 5, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT14__MMDC_MMDC_DEBUG_37	= IOMUX_PAD(0x0660, 0x0290, 6, 0x0000, 0, 0),

@@ -1252,7 +1245,6 @@ enum {
 	MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15	= IOMUX_PAD(0x0664, 0x0294, 0, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT15__WEIM_WEIM_D_11	= IOMUX_PAD(0x0664, 0x0294, 1, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT15__PCIE_CTRL_MUX_19	= IOMUX_PAD(0x0664, 0x0294, 2, 0x0000, 0, 0),
-	MX6Q_PAD_CSI0_DAT15__UART5_TXD		= IOMUX_PAD(0x0664, 0x0294, 3, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT15__UART5_RXD		= IOMUX_PAD(0x0664, 0x0294, 3, 0x0940, 3, 0),
 	MX6Q_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9	= IOMUX_PAD(0x0664, 0x0294, 4, 0x0000, 0, 0),
 	MX6Q_PAD_CSI0_DAT15__GPIO_6_1		= IOMUX_PAD(0x0664, 0x0294, 5, 0x0000, 0, 0),

@@ -1318,7 +1310,7 @@ enum {
 	MX6Q_PAD_TEST_MODE__TCU_TEST_MODE	= IOMUX_PAD(NO_PAD_I, NO_MUX_I, 0, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT7__USDHC3_DAT7		= IOMUX_PAD(0x0690, 0x02A8, 0, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT7__UART1_TXD		= IOMUX_PAD(0x0690, 0x02A8, 1, 0x0000, 0, 0),
-	MX6Q_PAD_SD3_DAT7__UART1_RXD		= IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
+	MX6Q_PAD_SD3_DAT7__UART1_TXD_RXD	= IOMUX_PAD(0x0690, 0x02A8, 1, 0x0920, 2, 0),
 	MX6Q_PAD_SD3_DAT7__PCIE_CTRL_MUX_24	= IOMUX_PAD(0x0690, 0x02A8, 2, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT7__USBOH3_UH3_DFD_OUT_0	= IOMUX_PAD(0x0690, 0x02A8, 3, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT7__USBOH3_UH2_DFD_OUT_0	= IOMUX_PAD(0x0690, 0x02A8, 4, 0x0000, 0, 0),

@@ -1326,7 +1318,6 @@ enum {
 	MX6Q_PAD_SD3_DAT7__MIPI_CORE_DPHY_IN_12	= IOMUX_PAD(0x0690, 0x02A8, 6, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT7__USBPHY2_CLK20DIV	= IOMUX_PAD(0x0690, 0x02A8, 7, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT6__USDHC3_DAT6		= IOMUX_PAD(0x0694, 0x02AC, 0, 0x0000, 0, 0),
-	MX6Q_PAD_SD3_DAT6__UART1_TXD		= IOMUX_PAD(0x0694, 0x02AC, 1, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT6__UART1_RXD		= IOMUX_PAD(0x0694, 0x02AC, 1, 0x0920, 3, 0),
 	MX6Q_PAD_SD3_DAT6__PCIE_CTRL_MUX_25	= IOMUX_PAD(0x0694, 0x02AC, 2, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT6__USBOH3_UH3_DFD_OUT_1 = IOMUX_PAD(0x0694, 0x02AC, 3, 0x0000, 0, 0),

@@ -1336,7 +1327,7 @@ enum {
 	MX6Q_PAD_SD3_DAT6__ANATOP_TESTO_10	= IOMUX_PAD(0x0694, 0x02AC, 7, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT5__USDHC3_DAT5		= IOMUX_PAD(0x0698, 0x02B0, 0, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT5__UART2_TXD		= IOMUX_PAD(0x0698, 0x02B0, 1, 0x0000, 0, 0),
-	MX6Q_PAD_SD3_DAT5__UART2_RXD		= IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
+	MX6Q_PAD_SD3_DAT5__UART2_TXD_RXD	= IOMUX_PAD(0x0698, 0x02B0, 1, 0x0928, 4, 0),
 	MX6Q_PAD_SD3_DAT5__PCIE_CTRL_MUX_26	= IOMUX_PAD(0x0698, 0x02B0, 2, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT5__USBOH3_UH3_DFD_OUT_2	= IOMUX_PAD(0x0698, 0x02B0, 3, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT5__USBOH3_UH2_DFD_OUT_2	= IOMUX_PAD(0x0698, 0x02B0, 4, 0x0000, 0, 0),

@@ -1344,7 +1335,6 @@ enum {
 	MX6Q_PAD_SD3_DAT5__MIPI_CORE_DPHY_IN_14	= IOMUX_PAD(0x0698, 0x02B0, 6, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT5__ANATOP_TESTO_11	= IOMUX_PAD(0x0698, 0x02B0, 7, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT4__USDHC3_DAT4		= IOMUX_PAD(0x069C, 0x02B4, 0, 0x0000, 0, 0),
-	MX6Q_PAD_SD3_DAT4__UART2_TXD		= IOMUX_PAD(0x069C, 0x02B4, 1, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT4__UART2_RXD		= IOMUX_PAD(0x069C, 0x02B4, 1, 0x0928, 5, 0),
 	MX6Q_PAD_SD3_DAT4__PCIE_CTRL_MUX_27	= IOMUX_PAD(0x069C, 0x02B4, 2, 0x0000, 0, 0),
 	MX6Q_PAD_SD3_DAT4__USBOH3_UH3_DFD_OUT_3	= IOMUX_PAD(0x069C, 0x02B4, 3, 0x0000, 0, 0),

@@ -1471,13 +1461,12 @@ enum {
 	MX6Q_PAD_SD4_CMD__USDHC4_CMD		= IOMUX_PAD(0x06DC, 0x02F4, 16, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CMD__RAWNAND_RDN		= IOMUX_PAD(0x06DC, 0x02F4, 1, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CMD__UART3_TXD		= IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0000, 0, 0),
-	MX6Q_PAD_SD4_CMD__UART3_RXD		= IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
+	MX6Q_PAD_SD4_CMD__UART3_TXD_RXD		= IOMUX_PAD(0x06DC, 0x02F4, 2, 0x0930, 2, 0),
 	MX6Q_PAD_SD4_CMD__PCIE_CTRL_MUX_5	= IOMUX_PAD(0x06DC, 0x02F4, 4, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CMD__GPIO_7_9		= IOMUX_PAD(0x06DC, 0x02F4, 5, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CMD__TPSMP_HDATA_DIR	= IOMUX_PAD(0x06DC, 0x02F4, 7, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CLK__USDHC4_CLK		= IOMUX_PAD(0x06E0, 0x02F8, 0, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CLK__RAWNAND_WRN		= IOMUX_PAD(0x06E0, 0x02F8, 1, 0x0000, 0, 0),
-	MX6Q_PAD_SD4_CLK__UART3_TXD		= IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CLK__UART3_RXD		= IOMUX_PAD(0x06E0, 0x02F8, 2, 0x0930, 3, 0),
 	MX6Q_PAD_SD4_CLK__PCIE_CTRL_MUX_6	= IOMUX_PAD(0x06E0, 0x02F8, 4, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_CLK__GPIO_7_10		= IOMUX_PAD(0x06E0, 0x02F8, 5, 0x0000, 0, 0),

@@ -1578,7 +1567,6 @@ enum {
 	MX6Q_PAD_SD4_DAT3__IPU2_IPU_DIAG_BUS_11	= IOMUX_PAD(0x0710, 0x0328, 7, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT4__RAWNAND_D12		= IOMUX_PAD(0x0714, 0x032C, 0, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT4__USDHC4_DAT4		= IOMUX_PAD(0x0714, 0x032C, 1, 0x0000, 0, 0),
-	MX6Q_PAD_SD4_DAT4__UART2_TXD		= IOMUX_PAD(0x0714, 0x032C, 2, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT4__UART2_RXD		= IOMUX_PAD(0x0714, 0x032C, 2, 0x0928, 6, 0),
 	MX6Q_PAD_SD4_DAT4__USBOH3_UH2_DFD_OUT28	= IOMUX_PAD(0x0714, 0x032C, 3, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT4__USBOH3_UH3_DFD_OUT28	= IOMUX_PAD(0x0714, 0x032C, 4, 0x0000, 0, 0),

@@ -1605,7 +1593,7 @@ enum {
 	MX6Q_PAD_SD4_DAT7__RAWNAND_D15		= IOMUX_PAD(0x0720, 0x0338, 0, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT7__USDHC4_DAT7		= IOMUX_PAD(0x0720, 0x0338, 1, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT7__UART2_TXD		= IOMUX_PAD(0x0720, 0x0338, 2, 0x0000, 0, 0),
-	MX6Q_PAD_SD4_DAT7__UART2_RXD		= IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
+	MX6Q_PAD_SD4_DAT7__UART2_TXD_RXD	= IOMUX_PAD(0x0720, 0x0338, 2, 0x0928, 7, 0),
 	MX6Q_PAD_SD4_DAT7__USBOH3_UH2_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 3, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT7__USBOH3_UH3_DFD_OUT31 = IOMUX_PAD(0x0720, 0x0338, 4, 0x0000, 0, 0),
 	MX6Q_PAD_SD4_DAT7__GPIO_2_15		= IOMUX_PAD(0x0720, 0x0338, 5, 0x0000, 0, 0),

Signature · 1 line

1.7.0.4

Dirk Behme

author

2012-01-13 09:49 UTC #1 lore raw

PATCH 1/1 i.mx6q: configs: Add fdt_high and initrd_high variables

To be able to load the device tree and initrd correctly, set the fdt_high and initrd_high environment variables.

Using 0xffffffff implies that the device tree and the initrd are initially copied to working addresses. This will avoid an additional copy.

Loading the device tree to 0x30000000 and the initrd to 0x3c000000 should work for both boards, the ARM2 and SabreLite.

Example (SabreLite):

fatload mmc 0:2 0x10000000 uImage
fatload mmc 0:2 0x3c000000 uInitrd
fatload mmc 0:2 0x30000000 board.dtb
bootm 0x10000000 0x3c000000 0x30000000

Note: This requires that the kernel has CONFIG_HIGHMEM enabled.

Signed-off-by Dirk Behme <[email protected]>

CC Jason Liu <[email protected]>

CC Stefano Babic <[email protected]>

---
Note: This patch is against the recent head of u-boot-imx.git including
the SabreLite support:

5b894e4d00ff94a221f8cc23d54d08b889f54190
i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board

Note: tools/checkpatch.pl reports 0 errors, 0 warnings

 include/configs/mx6qarm2.h      |    2 ++
 include/configs/mx6qsabrelite.h |    2 ++
 2 files changed, 4 insertions(+), 0 deletions(-)

include/configs/mx6qarm2.h +2 -0

index 124a7a6..0962d3c 100644
@@ -86,6 +86,8 @@
 	"script=boot.scr\0" \
 	"uimage=uImage\0" \
 	"console=ttymxc3\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
 	"mmcdev=1\0" \
 	"mmcpart=2\0" \
 	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \

include/configs/mx6qsabrelite.h +2 -0

index 464f0ec..ba09f15 100644
@@ -78,6 +78,8 @@
        "script=boot.scr\0" \
        "uimage=uImage\0" \
        "console=ttymxc3\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
        "mmcdev=0\0" \
        "mmcpart=2\0" \
        "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \

Signature · 1 line

1.7.0.4

Jason Hui

2012-01-16 13:45 UTC #2 lore raw

PATCH 1/1 i.mx6q: configs: Add fdt_high and initrd_high variables

Quoted 22 lines · Dirk Behme

To be able to load the device tree and initrd correctly, set the fdt_high and initrd_high environment variables.
Using 0xffffffff implies that the device tree and the initrd are initially copied to working addresses. This will avoid an additional copy.
Loading the device tree to 0x30000000 and the initrd to 0x3c000000 should work for both boards, the ARM2 and SabreLite.
Example (SabreLite):
fatload mmc 0:2 0x10000000 uImage
fatload mmc 0:2 0x3c000000 uInitrd
fatload mmc 0:2 0x30000000 board.dtb
bootm 0x10000000 0x3c000000 0x30000000
Note: This requires that the kernel has CONFIG_HIGHMEM enabled.
Signed-off-by Dirk Behme <[email protected]>
CC Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>

Quoted 9 lines

---
Note: This patch is against the recent head of u-boot-imx.git including ? ? ?the SabreLite support:
? ? ?5b894e4d00ff94a221f8cc23d54d08b889f54190
? ? ?i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board
Note: tools/checkpatch.pl reports 0 errors, 0 warnings

Acked-by Jason Liu <[email protected]>

Quoted 2 lines

1.7.0.4

Stefano Babic

2012-01-17 09:45 UTC #3 lore raw

PATCH 1/1 i.mx6q: configs: Add fdt_high and initrd_high variables

In reply to Dirk Behme

Quoted 17 lines · Dirk Behme

To be able to load the device tree and initrd correctly, set the fdt_high and initrd_high environment variables.
Using 0xffffffff implies that the device tree and the initrd are initially copied to working addresses. This will avoid an additional copy.
Loading the device tree to 0x30000000 and the initrd to 0x3c000000 should work for both boards, the ARM2 and SabreLite.
Example (SabreLite):
fatload mmc 0:2 0x10000000 uImage
fatload mmc 0:2 0x3c000000 uInitrd
fatload mmc 0:2 0x30000000 board.dtb
bootm 0x10000000 0x3c000000 0x30000000

Quoted 6 lines

Note: This requires that the kernel has CONFIG_HIGHMEM enabled.
Signed-off-by Dirk Behme <[email protected]>
CC Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Dirk Behme

author

2012-01-13 09:49 UTC #4 lore raw

PATCH 1/1 i.mx6q: mx6qsabrelite: Setup uart1 pinmux

In reply to Dirk Behme

From: Troy Kisky <[email protected]>

This allows the Linux kernel to use UART1 before pinmux support is added for UART1

Signed-off-by Troy Kisky <[email protected]>

CC Troy Kisky <[email protected]>

CC Jason Liu <[email protected]>

CC Stefano Babic <[email protected]>

---
Note: This patch is against the recent head of u-boot-imx.git including
the SabreLite support:

5b894e4d00ff94a221f8cc23d54d08b889f54190
i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board

Note: tools/checkpatch.pl reports 0 errors, 0 warnings

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

board/freescale/mx6qsabrelite/mx6qsabrelite.c +6 -0

index 4028789..233e652 100644
@@ -47,6 +47,11 @@ int dram_init(void)
        return 0;
 }
 
+iomux_v3_cfg_t uart1_pads[] = {
+	MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
 iomux_v3_cfg_t uart2_pads[] = {
        MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),

@@ -74,6 +79,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
 
 static void setup_iomux_uart(void)
 {
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }

Signature · 1 line

1.7.0.4

Jason Hui

2012-01-16 13:45 UTC #5 lore raw

PATCH 1/1 i.mx6q: mx6qsabrelite: Setup uart1 pinmux

Quoted 9 lines · Dirk Behme

From: Troy Kisky <[email protected]>
This allows the Linux kernel to use UART1 before pinmux support is added for UART1
Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>

Quoted 9 lines

---
Note: This patch is against the recent head of u-boot-imx.git including ? ? ?the SabreLite support:
? ? ?5b894e4d00ff94a221f8cc23d54d08b889f54190
? ? ?i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board
Note: tools/checkpatch.pl reports 0 errors, 0 warnings

Acked-by Jason Liu <[email protected]>

Quoted 30 lines

?board/freescale/mx6qsabrelite/mx6qsabrelite.c | ? ?6 ++++++ ?1 files changed, 6 insertions(+), 0 deletions(-)

board/freescale/mx6qsabrelite/mx6qsabrelite.c +6 -1

index 4028789..233e652 100644
@@ -47,6 +47,11 @@ int dram_init(void)
 ? ? ? ?return 0;
 ?}
 
+iomux_v3_cfg_t uart1_pads[] = {
+ ? ? ? MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ ? ? ? MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
 ?iomux_v3_cfg_t uart2_pads[] = {
 ? ? ? ?MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
 ? ? ? ?MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),

@@ -74,6 +79,7 @@ iomux_v3_cfg_t usdhc4_pads[] = {
 
 ?static void setup_iomux_uart(void)
 ?{
+ ? ? ? imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 ? ? ? ?imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 ?}
 
--

1.7.0.4

Stefano Babic

2012-01-17 09:45 UTC #6 lore raw

PATCH 1/1 i.mx6q: mx6qsabrelite: Setup uart1 pinmux

In reply to Dirk Behme

Quoted 10 lines · Dirk Behme

From: Troy Kisky <[email protected]>
This allows the Linux kernel to use UART1 before pinmux support is added for UART1
Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Jason Hui

2012-01-16 13:44 UTC #7 lore raw

PATCH 1/1 i.mx6: mx6x_pins: Fix uart txd definitions

In reply to Dirk Behme

Quoted 5 lines · Dirk Behme

From: Troy Kisky <[email protected]>
The uart txd pad can also provide the rxd function. But it does not stop its tx role. This could be used for a half duplex serial port.

Quoted 7 lines

Change names to reduce confusion.
Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Jason Liu <[email protected]>
CC Stefano Babic <[email protected]>
---

Acked-by Jason Liu <[email protected]>

Quoted 2 lines

1.7.0.4