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net: fec_mxc: Add 1000 Mbps selection

PATCH New Dirk Behme 7 participants 19 messages Jan 13, 2012 – Jan 19, 2012 Network drivers

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Dirk Behme

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#0 lore raw

PATCH 1/5 net: fec_mxc: Add 1000 Mbps selection

From: Troy Kisky <[email protected]>

Add 1000 Mbps selection and print negotiated speed

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 drivers/net/fec_mxc.c |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletions(-)
drivers/net/fec_mxc.c +15 -1
index ed73353..9e8ef7a 100644
@@ -379,6 +379,7 @@ static int fec_set_hwaddr(struct eth_device *dev)
 static int fec_open(struct eth_device *edev)
 {
 	struct fec_priv *fec = (struct fec_priv *)edev->priv;
+	int speed;
 
 	debug("fec_open: fec_open(dev)\n");
 	/* full-duplex, heartbeat disabled */

@@ -428,8 +429,21 @@ static int fec_open(struct eth_device *edev)
 #endif
 
 	miiphy_wait_aneg(edev);
-	miiphy_speed(edev->name, fec->phy_id);
+	speed = miiphy_speed(edev->name, fec->phy_id);
 	miiphy_duplex(edev->name, fec->phy_id);
+#ifdef CONFIG_MX6Q
+	{
+		u32 ecr = readl(&fec->eth->ecntrl) & ~(0x1 << 5);
+		u32 rcr = (readl(&fec->eth->r_cntrl) & ~0x300) | 0x44;
+		if (speed == _1000BASET)
+			ecr |= (0x1 << 5);
+		else if (speed != _100BASET)
+			rcr |= (0x1 << 9);
+		writel(ecr, &fec->eth->ecntrl);
+		writel(rcr, &fec->eth->r_cntrl);
+	}
+#endif
+	printf("%s:Speed=%i\n", __func__, speed);
 
 	/*
 	 * Enable SmartDMA receive task
Signature · 1 line
1.7.0.4
author
#1 lore raw

PATCH 2/5 net: fec_mxc: Increase autonegotiation timeout

From: Troy Kisky <[email protected]>

Timeouts were happening to soon for some switches.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 drivers/net/fec_mxc.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/net/fec_mxc.c +1 -1
index 9e8ef7a..b50e01c 100644
@@ -226,7 +226,7 @@ static int miiphy_wait_aneg(struct eth_device *dev)
 	 */
 	start = get_timer(0);
 	do {
-		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
+		if (get_timer(start) > (CONFIG_SYS_HZ * 10)) {
 			printf("%s: Autonegotiation timeout\n", dev->name);
 			return -1;
 		}
Signature · 1 line
1.7.0.4
author
#2 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

In reply to Dirk Behme

From: Troy Kisky <[email protected]>

Previously, only GIGE phy was supported in this function.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 common/miiphyutil.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)
common/miiphyutil.c +17 -1
index 2cc23b4..8cb4748 100644
@@ -471,7 +471,23 @@ int miiphy_speed(const char *devname, unsigned char addr)
 			(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
 		return _1000BASET;
 #endif /* CONFIG_PHY_GIGE */
-
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+#define MII_PHY_CTL		0x1f
+#define MII_PHY_CTL_1000	(1 << 6)
+#define MII_PHY_CTL_100		(1 << 5)
+#define MII_PHY_CTL_10		(1 << 4)
+	u16 btsr;
+	if (miiphy_read(devname, addr, MII_PHY_CTL, &btsr)) {
+		printf("PHY 1000BT status");
+		goto miiphy_read_failed;
+	}
+	if (btsr & MII_PHY_CTL_1000)
+		return _1000BASET;
+	if (btsr & MII_PHY_CTL_100)
+		return _100BASET;
+	if (btsr & MII_PHY_CTL_10)
+		return _10BASET;
+#endif
 	/* Check Basic Management Control Register first. */
 	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
 		printf("PHY speed");
Signature · 1 line
1.7.0.4
#3 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

Quoted 19 lines

From: Troy Kisky <[email protected]>

Previously, only GIGE phy was supported in this function.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 common/miiphyutil.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)
common/miiphyutil.c +0 -0
index 2cc23b4..8cb4748 100644
@@ -471,7 +471,23 @@ int miiphy_speed(const char *devname, unsigned char
 addr) (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
 		return _1000BASET;

common/miiphyutil.c int miiphy_speed(const char *devname, unsigned char · line 481

Quoted 10 lines
common/miiphyutil.c +8 -1
 #endif /* CONFIG_PHY_GIGE */
-
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+#define MII_PHY_CTL		0x1f
+#define MII_PHY_CTL_1000	(1 << 6)
+#define MII_PHY_CTL_100		(1 << 5)
+#define MII_PHY_CTL_10		(1 << 4)
+	u16 btsr;
+	if (miiphy_read(devname, addr, MII_PHY_CTL, &btsr)) {
+		printf("PHY 1000BT status");

Very helpful message. Please, if you want to print some output, output something understandable.

Quoted 12 lines
common/miiphyutil.c +9 -0
+		goto miiphy_read_failed;
+	}
+	if (btsr & MII_PHY_CTL_1000)
+		return _1000BASET;
+	if (btsr & MII_PHY_CTL_100)
+		return _100BASET;
+	if (btsr & MII_PHY_CTL_10)
+		return _10BASET;
+#endif
 	/* Check Basic Management Control Register first. */
 	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
 		printf("PHY speed");
#4 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

In reply to Dirk Behme
Quoted 2 lines · On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
 common/miiphyutil.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.

common/miiphyutil.c int miiphy_speed(const char *devname, unsigned char addr) · line 478

Quoted 8 lines
common/miiphyutil.c +5 -0
 
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+#define MII_PHY_CTL		0x1f
+#define MII_PHY_CTL_1000	(1 << 6)
+#define MII_PHY_CTL_100		(1 << 5)
+#define MII_PHY_CTL_10		(1 << 4)

are you sure there aren't defines already in linux/mii.h for these ?
-mike
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author
#5 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

Quoted 6 lines · Mike Frysinger
Quoted 2 lines · On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
 common/miiphyutil.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.

Could you point us to an example how to "use the name phy framework"?

Many thanks and best regards

Dirk

#6 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

Quoted 9 lines · Dirk Behme
Quoted 6 lines · Mike Frysinger
Quoted 2 lines · On Friday 13 January 2012 07:10:02 Dirk Behme wrote:

common/miiphyutil.c | 18 +++++++++++++++++-

1 files changed, 17 insertions(+), 1 deletions(-)

this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.

Could you point us to an example how to "use the name phy framework"?

Hmm, is anything like

http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=5751aa2f248a72c3cec7048cec8dfad33dab0979

http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=fcc0c75dea90f2bb8394e7031fc33f72119be544

meant here?

Best regards

Dirk

#7 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

Quoted 13 lines · On Thursday 19 January 2012 11:19:52 Dirk Behme wrote:
Quoted 9 lines · Dirk Behme
Quoted 6 lines · Mike Frysinger
Quoted 2 lines · On Friday 13 January 2012 07:10:02 Dirk Behme wrote:

common/miiphyutil.c | 18 +++++++++++++++++-

1 files changed, 17 insertions(+), 1 deletions(-)

this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.

Could you point us to an example how to "use the name phy framework"?

Hmm, is anything like

Quoted 7 lines

http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=5751aa2f2
48a72c3cec7048cec8dfad33dab0979

http://git.denx.de/cgi-bin/gitweb.cgi?p=u-boot.git;a=commitdiff;h=fcc0c75de
a90f2bb8394e7031fc33f72119be544

meant here?

yep, that's the ticket
-mike
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#8 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

In reply to Dirk Behme
Quoted 9 lines · On Thursday 19 January 2012 07:38:44 Dirk Behme wrote:
Quoted 6 lines · Mike Frysinger
Quoted 2 lines · On Friday 13 January 2012 07:10:02 Dirk Behme wrote:
 common/miiphyutil.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)

this is dead code ... i think we're pushing people to use the name phy framework rather than fixing/extending the old one.

Could you point us to an example how to "use the name phy framework"?

sorry, typo. i meant "new phy framework". as in the phylib stuff.
-mike
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author
#9 lore raw

PATCH 3/5 miiphyutil: Add Micrel KSZ9021 support to miiphy_speed

In reply to Dirk Behme

Hi Troy,

Quoted 31 lines · Dirk Behme

From: Troy Kisky <[email protected]>

Previously, only GIGE phy was supported in this function.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 common/miiphyutil.c |   18 +++++++++++++++++-
 1 files changed, 17 insertions(+), 1 deletions(-)
common/miiphyutil.c +10 -1
index 2cc23b4..8cb4748 100644
@@ -471,7 +471,23 @@ int miiphy_speed(const char *devname, unsigned char addr)
 			(btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)))
 		return _1000BASET;
 #endif /* CONFIG_PHY_GIGE */
-
+#ifdef CONFIG_PHY_MICREL_KSZ9021
+#define MII_PHY_CTL		0x1f
+#define MII_PHY_CTL_1000	(1 << 6)
+#define MII_PHY_CTL_100		(1 << 5)
+#define MII_PHY_CTL_10		(1 << 4)
+	u16 btsr;
+	if (miiphy_read(devname, addr, MII_PHY_CTL, &btsr)) {
+		printf("PHY 1000BT status");
+		goto miiphy_read_failed;
+	}

common/miiphyutil.c int miiphy_speed(const char *devname, unsigned char addr) · line 493

Quoted 10 lines
common/miiphyutil.c +7 -0
+	if (btsr & MII_PHY_CTL_1000)
+		return _1000BASET;
+	if (btsr & MII_PHY_CTL_100)
+		return _100BASET;
+	if (btsr & MII_PHY_CTL_10)
+		return _10BASET;
+#endif
 	/* Check Basic Management Control Register first. */
 	if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) {
 		printf("PHY speed");

Thilo mentioned that on an ARM2 board he additionally needs

common/miiphyutil.c +0 -0
index 8cb4748..d3ff2af 100644
@@ -500,6 +500,8 @@ int miiphy_speed(const char *devname, unsigned char

addr)
printf("PHY AN speed");
goto miiphy_read_failed;
}
+ if (anlpar & LPA_1000XFULL )
+ return _1000BASET;
return (anlpar & LPA_100) ? _100BASET : _10BASET;
}
/* Get speed from basic control settings. */

to make GbE work on that board. What do you think?

Best regards

Dirk

author
#10 lore raw

PATCH 4/5 net: fec_mxc: Nove autonegoatiate restart after mii_postcall

In reply to Dirk Behme

From: Troy Kisky <[email protected]>

Allow boards to change what is advertised before an autoneg restart happens.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 drivers/net/fec_mxc.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)
drivers/net/fec_mxc.c +3 -3
index b50e01c..6271df5 100644
@@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
 			LPA_100FULL | LPA_100HALF | LPA_10FULL |
 			LPA_10HALF | PHY_ANLPAR_PSB_802_3);
-	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
 	if (fec->mii_postcall)
 		ret = fec->mii_postcall(fec->phy_id);
 
+	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+
 	return ret;
 }
Signature · 1 line
1.7.0.4
#11 lore raw

PATCH 4/5 net: fec_mxc: Nove autonegoatiate restart after mii_postcall

Quoted 22 lines

From: Troy Kisky <[email protected]>

Allow boards to change what is advertised before an autoneg restart happens.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 drivers/net/fec_mxc.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)
drivers/net/fec_mxc.c +0 -1
index b50e01c..6271df5 100644
@@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device
 *dev) miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
 			LPA_100FULL | LPA_100HALF | LPA_10FULL |
 			LPA_10HALF | PHY_ANLPAR_PSB_802_3);
-	miiphy_write(dev->name, fec->phy_id, MII_BMCR,

drivers/net/fec_mxc.c static int miiphy_restart_aneg(struct eth_device · line 216

Quoted 10 lines
drivers/net/fec_mxc.c +3 -2
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
 	if (fec->mii_postcall)
 		ret = fec->mii_postcall(fec->phy_id);
 
+	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+
 	return ret;
 }

I think this might break boards using the mii_postcall.

#12 lore raw

PATCH 4/5 net: fec_mxc: Nove autonegoatiate restart after mii_postcall

Quoted 27 lines · Marek Vasut
Quoted 27 lines

From: Troy Kisky<[email protected]>

Allow boards to change what is advertised before an autoneg restart happens.

Signed-off-by Troy Kisky<[email protected]>
CC Troy Kisky<[email protected]>
CC Stefano Babic<[email protected]>
CC Marek Vasut<[email protected]>
---
  drivers/net/fec_mxc.c |    6 +++---
  1 files changed, 3 insertions(+), 3 deletions(-)
drivers/net/fec_mxc.c +0 -3
index b50e01c..6271df5 100644
@@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device
 *dev) miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
  			LPA_100FULL | LPA_100HALF | LPA_10FULL |
  			LPA_10HALF | PHY_ANLPAR_PSB_802_3);
-	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
  	if (fec->mii_postcall)
  		ret = fec->mii_postcall(fec->phy_id);
Quoted 7 lines

drivers/net/fec_mxc.c static int miiphy_restart_aneg(struct eth_device *dev) · line 216

Quoted 5 lines
drivers/net/fec_mxc.c +3 -0
+	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+
  	return ret;
  }

I think this might break boards using the mii_postcall.

Since only 3 boards use this. Perhaps I should code as

if (fec->mii_start_aneg_call)

	ret = fec->mii_start_aneg_call(fec->phy_id);
else
	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
		BMCR_ANENABLE | BMCR_ANRESTART);

and copy the

	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
		BMCR_ANENABLE | BMCR_ANRESTART);

into all three callbacks?

Troy

#13 lore raw

PATCH 4/5 net: fec_mxc: Nove autonegoatiate restart after mii_postcall

In reply to Dirk Behme
Quoted 20 lines · Dirk Behme

From: Troy Kisky <[email protected]>

Allow boards to change what is advertised before an autoneg restart happens.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 drivers/net/fec_mxc.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)
drivers/net/fec_mxc.c +0 -0
index b50e01c..6271df5 100644
@@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
 			LPA_100FULL | LPA_100HALF | LPA_10FULL |

drivers/net/fec_mxc.c static int miiphy_restart_aneg(struct eth_device *dev) · line 214

Quoted 10 lines
drivers/net/fec_mxc.c +3 -3
 			LPA_10HALF | PHY_ANLPAR_PSB_802_3);
-	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
 	if (fec->mii_postcall)
 		ret = fec->mii_postcall(fec->phy_id);
 
+	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+

...but you change the postcall into a precall...

The current implementation is correct. Something is set / written , and after that a specific supplied function (if any) is called, then the name postcall.

Changing the order is not correct if the fec->mii_postcall thinks (as it should be) that the MII_BMCR register was already written.

But you missed to mention why you need such as change : which is the failure / bug you discovered ?

Best regards,
Stefano Babic

Signature · 5 lines
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Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================
#14 lore raw

PATCH 4/5 net: fec_mxc: Nove autonegoatiate restart after mii_postcall

Quoted 28 lines · Stefano Babic
Quoted 27 lines · Dirk Behme

From: Troy Kisky<[email protected]>

Allow boards to change what is advertised before an autoneg restart happens.

Signed-off-by Troy Kisky<[email protected]>
CC Troy Kisky<[email protected]>
CC Stefano Babic<[email protected]>
CC Marek Vasut<[email protected]>
---
  drivers/net/fec_mxc.c |    6 +++---
  1 files changed, 3 insertions(+), 3 deletions(-)
drivers/net/fec_mxc.c +0 -3
index b50e01c..6271df5 100644
@@ -206,12 +206,12 @@ static int miiphy_restart_aneg(struct eth_device *dev)
  	miiphy_write(dev->name, fec->phy_id, MII_ADVERTISE,
  			LPA_100FULL | LPA_100HALF | LPA_10FULL |
  			LPA_10HALF | PHY_ANLPAR_PSB_802_3);
-	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
-			BMCR_ANENABLE | BMCR_ANRESTART);
-
  	if (fec->mii_postcall)
  		ret = fec->mii_postcall(fec->phy_id);
Quoted 4 lines

drivers/net/fec_mxc.c static int miiphy_restart_aneg(struct eth_device *dev) · line 214

Quoted 3 lines
drivers/net/fec_mxc.c +3 -0
+	miiphy_write(dev->name, fec->phy_id, MII_BMCR,
+			BMCR_ANENABLE | BMCR_ANRESTART);
+

...but you change the postcall into a precall...

I assumed mii_postcall meant mii_post_init_call
not mii_post_aneg_call.

A rename of the function may be desired.

Perhaps we should let the mii_postcall function do the

miiphy_write(dev->name, fec->phy_id, MII_BMCR,

			BMCR_ANENABLE | BMCR_ANRESTART);

as well.

Quoted 10 lines

The current implementation is correct. Something is set / written , and after that a specific supplied function (if any) is called, then the name postcall.

Changing the order is not correct if the fec->mii_postcall thinks (as it should be) that the MII_BMCR register was already written.

But you missed to mention why you need such as change : which is the failure / bug you discovered ?

I wanted the sabrelite board to be able to remove 1000BaseT advertisement before aneg starts.

I think it works either way, but is clearer this way and doesn't rely on luck.

Quoted 4 lines

Best regards,
Stefano Babic

author
#15 lore raw

PATCH 5/5 i.mx6q: mx6qsabrelite: Update the network configuration

In reply to Dirk Behme

From: Troy Kisky <[email protected]>

Enable the usage of PHY_MICREL_KSZ9021, force the master mode and minimize the tx clock delay.

There is an issue with the gigabit ethernet mode at the SabreLite boards:
When operating on a Gb LAN, the FEC occasionally receives packets larger than the MTU that appear to be caused by concatenation of multiple received packets into one.
The problem was identified on the phy side. The current schematic has the center tap pin 9 of the MAG/JAC USB combo to 3.3 filtered supply. Letting this pin float solves the problem.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Jason Liu <[email protected]>

---
Note: This patch depends on the basic SabreLite ethernet patch

      http://patchwork.ozlabs.org/patch/135744/
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |    8 ++++++--
 include/configs/mx6qsabrelite.h               |    1 +
 2 files changed, 7 insertions(+), 2 deletions(-)
board/freescale/mx6qsabrelite/mx6qsabrelite.c +6 -2
index d80165e..7879049 100644
@@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis)
 
 int fecmxc_mii_postcall(int phy)
 {
-	/* prefer master mode */
-	miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
+	/* force master mode */
+	miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00);
 
 	/* min rx data delay */
 	miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105);
 	miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
 
+	/* min tx data delay */
+	miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106);
+	miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
+
 	/* max rx/tx clock delay, min rx/tx control delay */
 	miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104);
 	miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);
include/configs/mx6qsabrelite.h +1 -0
index 840e271..6a29142 100644
@@ -66,6 +66,7 @@
 #define	CONFIG_FEC_XCV_TYPE		RGMII
 #define CONFIG_ETHPRIME			"FEC"
 #define CONFIG_FEC_MXC_PHYADDR		6
+#define CONFIG_PHY_MICREL_KSZ9021
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
Signature · 1 line
1.7.0.4
#16 lore raw

PATCH 5/5 i.mx6q: mx6qsabrelite: Update the network configuration

Quoted 54 lines · Dirk Behme

From: Troy Kisky <[email protected]>

Enable the usage of PHY_MICREL_KSZ9021, force the master mode and minimize the tx clock delay.

There is an issue with the gigabit ethernet mode at the SabreLite boards:
When operating on a Gb LAN, the FEC occasionally receives packets larger than the MTU that appear to be caused by concatenation of multiple received packets into one.
The problem was identified on the phy side. The current schematic has the center tap pin 9 of the MAG/JAC USB combo to 3.3 filtered supply. Letting this pin float solves the problem.

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Jason Liu <[email protected]>

---
Note: This patch depends on the basic SabreLite ethernet patch ? ? ?http://patchwork.ozlabs.org/patch/135744/

?board/freescale/mx6qsabrelite/mx6qsabrelite.c | ? ?8 ++++++-- ?include/configs/mx6qsabrelite.h ? ? ? ? ? ? ? | ? ?1 + ?2 files changed, 7 insertions(+), 2 deletions(-)

board/freescale/mx6qsabrelite/mx6qsabrelite.c +2 -2
index d80165e..7879049 100644
@@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis)
 
 ?int fecmxc_mii_postcall(int phy)
 ?{
- ? ? ? /* prefer master mode */
- ? ? ? miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
+ ? ? ? /* force master mode */
+ ? ? ? miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00);

? ? ? ?/* min rx data delay */
? ? ? ?miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); ? ? ? ?miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);

+ ? ? ? /* min tx data delay */
+ ? ? ? miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106);
+ ? ? ? miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); +
? ? ? ?/* max rx/tx clock delay, min rx/tx control delay */ ? ? ? ?miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); ? ? ? ?miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);

include/configs/mx6qsabrelite.h +0 -0
index 840e271..6a29142 100644
@@ -66,6 +66,7 @@
Quoted 4 lines

?#define ? ? ? ?CONFIG_FEC_XCV_TYPE ? ? ? ? ? ? RGMII ?#define CONFIG_ETHPRIME ? ? ? ? ? ? ? ? ? ? ? ?"FEC" ?#define CONFIG_FEC_MXC_PHYADDR ? ? ? ? 6 +#define CONFIG_PHY_MICREL_KSZ9021

Acked-by Jason Liu <[email protected]>
Quoted 6 lines

?/* allow to overwrite serial and ethaddr */
?#define CONFIG_ENV_OVERWRITE
--
1.7.0.4

#17 lore raw

PATCH 5/5 i.mx6q: mx6qsabrelite: Update the network configuration

Quoted 10 lines · Jason Hui
Quoted 9 lines · Dirk Behme

From: Troy Kisky<[email protected]>

Enable the usage of PHY_MICREL_KSZ9021, force the master mode and minimize the tx clock delay.

There is an issue with the gigabit ethernet mode at the SabreLite boards:
When operating on a Gb LAN, the FEC occasionally receives packets larger than the MTU that appear to be caused by concatenation of multiple received packets into one.

No, the extra length are usually zero bytes.

Quoted 8 lines
Quoted 8 lines

The problem was identified on the phy side. The current schematic has the center tap pin 9 of the MAG/JAC USB combo to 3.3 filtered supply. Letting this pin float solves the problem.

Signed-off-by Troy Kisky<[email protected]>
CC Troy Kisky<[email protected]>
CC Stefano Babic<[email protected]>
CC Jason Liu<[email protected]>

Dirk should either signoff or ack

Quoted 48 lines
Quoted 37 lines

---
Note: This patch depends on the basic SabreLite ethernet patch

      http://patchwork.ozlabs.org/patch/135744/
  board/freescale/mx6qsabrelite/mx6qsabrelite.c |    8 ++++++--
  include/configs/mx6qsabrelite.h               |    1 +
  2 files changed, 7 insertions(+), 2 deletions(-)
board/freescale/mx6qsabrelite/mx6qsabrelite.c +6 -2
index d80165e..7879049 100644
@@ -193,13 +193,17 @@ int board_mmc_init(bd_t *bis)
 
  int fecmxc_mii_postcall(int phy)
  {
-       /* prefer master mode */
-       miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00);
+       /* force master mode */
+       miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x1f00);
 
        /* min rx data delay */
        miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105);
        miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
 
+       /* min tx data delay */
+       miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8106);
+       miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000);
+
        /* max rx/tx clock delay, min rx/tx control delay */
        miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104);
        miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0);
include/configs/mx6qsabrelite.h +0 -0
index 840e271..6a29142 100644

include/configs/mx6qsabrelite.h line 69

Quoted 4 lines
include/configs/mx6qsabrelite.h +1 -0
@@ -66,6 +66,7 @@
  #define        CONFIG_FEC_XCV_TYPE             RGMII
  #define CONFIG_ETHPRIME                        "FEC"
  #define CONFIG_FEC_MXC_PHYADDR         6
+#define CONFIG_PHY_MICREL_KSZ9021
Acked-by Jason Liu<[email protected]>
Quoted 5 lines
include/configs/mx6qsabrelite.h +0 -1
  /* allow to overwrite serial and ethaddr */
  #define CONFIG_ENV_OVERWRITE
--

1.7.0.4

#18 lore raw

PATCH 1/5 net: fec_mxc: Add 1000 Mbps selection

In reply to Dirk Behme
Quoted 25 lines

From: Troy Kisky <[email protected]>

Add 1000 Mbps selection and print negotiated speed

Signed-off-by Troy Kisky <[email protected]>
CC Troy Kisky <[email protected]>
CC Stefano Babic <[email protected]>
CC Marek Vasut <[email protected]>
---
 drivers/net/fec_mxc.c |   16 +++++++++++++++-
 1 files changed, 15 insertions(+), 1 deletions(-)
drivers/net/fec_mxc.c +1 -0
index ed73353..9e8ef7a 100644
@@ -379,6 +379,7 @@ static int fec_set_hwaddr(struct eth_device *dev)
 static int fec_open(struct eth_device *edev)
 {
 	struct fec_priv *fec = (struct fec_priv *)edev->priv;
+	int speed;
 
 	debug("fec_open: fec_open(dev)\n");
 	/* full-duplex, heartbeat disabled */

drivers/net/fec_mxc.c static int fec_open(struct eth_device *edev) · line 437

Quoted 10 lines
drivers/net/fec_mxc.c +5 -1
@@ -428,8 +429,21 @@ static int fec_open(struct eth_device *edev)
 #endif
 
 	miiphy_wait_aneg(edev);
-	miiphy_speed(edev->name, fec->phy_id);
+	speed = miiphy_speed(edev->name, fec->phy_id);
 	miiphy_duplex(edev->name, fec->phy_id);
+#ifdef CONFIG_MX6Q
+	{
+		u32 ecr = readl(&fec->eth->ecntrl) & ~(0x1 << 5);
+		u32 rcr = (readl(&fec->eth->r_cntrl) & ~0x300) | 0x44;

Why the magic?

drivers/net/fec_mxc.c static int fec_open(struct eth_device *edev) · line 446

Quoted 9 lines
drivers/net/fec_mxc.c +9 -0
+		if (speed == _1000BASET)
+			ecr |= (0x1 << 5);
+		else if (speed != _100BASET)
+			rcr |= (0x1 << 9);
+		writel(ecr, &fec->eth->ecntrl);
+		writel(rcr, &fec->eth->r_cntrl);
+	}
+#endif
+	printf("%s:Speed=%i\n", __func__, speed);

debug()

Quoted 3 lines
drivers/net/fec_mxc.c +0 -0
 	/*
 	 * Enable SmartDMA receive task