mxc_spi refactoring (for mx6q and mx6qsabrelite)
Subsystems (3)
cover mxc_spi refactoring (for mx6q and mx6qsabrelite)
This patch set refactors mxc_spi as described in
http://lists.denx.de/pipermail/u-boot/2010-March/068791.html and requested in http://lists.denx.de/pipermail/u-boot/2012-January/116023.html
in order to add support for the MX6Q in general and the mx6qsabrelite specifically.
Patch 1 simply moves the conditional parts of mxc_spi.c into the respective CPU-specific imx-regs.h files.
Patch 2 adds general support for SPI to the i.MX6.
Patch 3 adds support to the mx6qsabrelite board
PATCH 1/3 mxc_spi: move machine specifics into CPU headers
Move (E)CSPI register declarations into the imx-regs.h files for each supported CPU
Introduce two new macros to control conditional setup
MXC_CSPI - Used for processors with the Configurable Serial Peripheral Interface (MX3x) MXC_ECSPI - For processors with Enhanced Configurable... (MX5x, MX6x)
--- arch/arm/include/asm/arch-mx31/imx-regs.h | 27 ++++++++ arch/arm/include/asm/arch-mx35/imx-regs.h | 25 ++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 30 +++++++++ drivers/spi/mxc_spi.c | 93 ++--------------------------- 4 files changed, 88 insertions(+), 87 deletions(-)
arch/arm/include/asm/arch-mx31/imx-regs.h +27 -0
@@ -901,4 +901,31 @@ struct esdc_regs {#define MXC_EHCI_IPPUE_DOWN (1 << 8)#define MXC_EHCI_IPPUE_UP (1 << 9) +/* +* CSPI register definitions +*/ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT (x) (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT (x) (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE (x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 8) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0x1f + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, \ + 0x53f84000, +#endif /* __ASM_ARCH_MX31_IMX_REGS_H */
arch/arm/include/asm/arch-mx35/imx-regs.h +25 -0
@@ -179,6 +179,31 @@#define IPU_CONF_IC_EN (1<<1)#define IPU_CONF_SCI_EN (1<<0) +/* +* CSPI register definitions +*/ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT (x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT (x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE (x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + 0x43fa4000, \ + 0x50010000, +#define GPIO_PORT_NUM 3#define GPIO_NUM_PIN 32
arch/arm/include/asm/arch-mx5/imx-regs.h +30 -0
@@ -223,6 +223,36 @@#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3/* +* CSPI register definitions +*/ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT (x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT (x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV (x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV (x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN (x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 +#define MXC_SPI_BASE_ADDRESSES \ + CSPI1_BASE_ADDR, \ + CSPI2_BASE_ADDR, \ + CSPI3_BASE_ADDR, + +/* * Number of GPIO pins per port */ #define GPIO_NUM_PIN 32
drivers/spi/mxc_spi.c +6 -87
127 lines not on this page · raw message
Signature · 1 line
1.7.1
PATCH 1/3 mxc_spi: move machine specifics into CPU headers
Eric
Quoted 9 lines · Eric Nelson
Move (E)CSPI register declarations into the
imx-regs.hfiles for each supported CPUIntroduce two new macros to control conditional setup
? ?MXC_CSPI- Used for processors with the Configurable Serial Peripheral Interface (MX3x) ? ?MXC_ECSPI- For processors with Enhanced Configurable... (MX5x, MX6x)Signed-off-by Eric Nelson <[email protected]>Acked-by Dirk Behme <[email protected]>Acked-by Stefano Babic <[email protected]>
Quoted 6 lines
---
?arch/arm/include/asm/arch-mx31/imx-regs.h | ? 27 ++++++++ ?arch/arm/include/asm/arch-mx35/imx-regs.h | ? 25 ++++++++ ?arch/arm/include/asm/arch-mx5/imx-regs.h ?| ? 30 +++++++++ ?drivers/spi/mxc_spi.c ? ? ? ? ? ? ? ? ? ? | ? 93 ++---------------------------?4 files changed, 88 insertions(+), 87 deletions(-)
Tested OK on the i.mx51evk board with SPI-PMIC
Quoted 253 lines
arch/arm/include/asm/arch-mx31/imx-regs.h +27
-0@@ -901,4 +901,31 @@ struct esdc_regs { ?#define MXC_EHCI_IPPUE_DOWN ? ? ? ? ? ?(1 << 8) ?#define MXC_EHCI_IPPUE_UP ? ? ? ? ? ? ?(1 << 9) +/* +* CSPI register definitions +*/ +#define MXC_CSPI +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) +#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) +#define MXC_CSPICTRL_POL ? ? ? (1 << 4) +#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) +#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) +#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT (x) ? ? (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT (x) ? ? ? (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE (x) ? ? ? (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 8) +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) +#define MXC_CSPICTRL_MAXBITS ? 0x1f + +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) +#define MAX_SPI_BYTES ?4 + +#define MXC_SPI_BASE_ADDRESSES \ + ? ? ? 0x43fa4000, \ + ? ? ? 0x50010000, \ + ? ? ? 0x53f84000, +?#endif /*
__ASM_ARCH_MX31_IMX_REGS_H*/arch/arm/include/asm/arch-mx35/imx-regs.h +25
-0@@ -179,6 +179,31 @@ ?#define IPU_CONF_IC_EN ? ? ? ? (1<<1) ?#define IPU_CONF_SCI_EN ? ? ? ? ? ? ? ?(1<<0) +/* +* CSPI register definitions +*/ +#define MXC_CSPI +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) +#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) +#define MXC_CSPICTRL_POL ? ? ? (1 << 4) +#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) +#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) +#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT (x) ? ? (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT (x) ? ? ? (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE (x) ? ? ? (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) +#define MXC_CSPICTRL_MAXBITS ? 0xfff +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) +#define MAX_SPI_BYTES ?4 + +#define MXC_SPI_BASE_ADDRESSES \ + ? ? ? 0x43fa4000, \ + ? ? ? 0x50010000, +?#define
GPIO_PORT_NUM? ? ? ? ?3
?#defineGPIO_NUM_PIN? ? ? ? ? 32arch/arm/include/asm/arch-mx5/imx-regs.h +0
-0@@ -223,6 +223,36 @@?#define
CS0_32M_CS1_32M_CS2_32M_CS3_32M? ? ? ? ? ? ? ?3?/*
+ * CSPI register definitions
+ */arch/arm/include/asm/arch-mx5/imx-regs.h +28
-0+#define MXC_ECSPI +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT (x) ? ? (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT (x) ? ? ? (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV (x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV (x) ? ? ? ?(((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN (x) ? ? ? ?(((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS ? 0xfff +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) +#define MAX_SPI_BYTES ?32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN ? ? ?18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4 +#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0 +#define MXC_CSPICON_SSPOL ? ? ?12 +#define MXC_SPI_BASE_ADDRESSES \ + ? ? ? CSPI1_BASE_ADDR, \ + ? ? ? CSPI2_BASE_ADDR, \ + ? ? ? CSPI3_BASE_ADDR, + +/* ?* Number of GPIO pins per port
?*/
?#defineGPIO_NUM_PIN? ? ? ? ? ?32drivers/spi/mxc_spi.c +0
-0@@ -33,93 +33,12 @@ ?#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \?"See linux
mxc_spidriver from Freescale for details."drivers/spi/mxc_spi.c +1
-77- -#elif defined(CONFIG_MX31 ) - -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) -#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) -#define MXC_CSPICTRL_POL ? ? ? (1 << 4) -#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) -#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) -#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT (x) ? ? (((x) & 0x3) << 24) -#define MXC_CSPICTRL_BITCOUNT (x) ? ? ? (((x) & 0x1f) << 8) -#define MXC_CSPICTRL_DATARATE (x) ? ? ? (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 8) -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) -#define MXC_CSPICTRL_MAXBITS ? 0x1f - -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) -#define MAX_SPI_BYTES ?4 - -static unsigned long spi_bases[] = { - ? ? ? 0x43fa4000, - ? ? ? 0x50010000, - ? ? ? 0x53f84000, -}; - -#elif defined(CONFIG_MX51 ) - -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) -#define MXC_CSPICTRL_CHIPSELECT (x) ? ? (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT (x) ? ? ? (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_PREDIV (x) (((x) & 0xF) << 12) -#define MXC_CSPICTRL_POSTDIV (x) ? ? ? ?(((x) & 0xF) << 8) -#define MXC_CSPICTRL_SELCHAN (x) ? ? ? ?(((x) & 0x3) << 18) -#define MXC_CSPICTRL_MAXBITS ? 0xfff -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) - -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) -#define MAX_SPI_BYTES ?32 - -/* Bit position inside CTRL register to be associated with SS */ -#define MXC_CSPICTRL_CHAN ? ? ?18 - -/* Bit position inside CON register to be associated with SS */ -#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4 -#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0 -#define MXC_CSPICON_SSPOL ? ? ?12 - -static unsigned long spi_bases[] = { - ? ? ? CSPI1_BASE_ADDR, - ? ? ? CSPI2_BASE_ADDR, - ? ? ? CSPI3_BASE_ADDR, -}; - -#elif defined(CONFIG_MX35 ) - -#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) -#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) -#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) -#define MXC_CSPICTRL_SMC ? ? ? (1 << 3) -#define MXC_CSPICTRL_POL ? ? ? (1 << 4) -#define MXC_CSPICTRL_PHA ? ? ? (1 << 5) -#define MXC_CSPICTRL_SSCTL ? ? (1 << 6) -#define MXC_CSPICTRL_SSPOL ? ? (1 << 7) -#define MXC_CSPICTRL_CHIPSELECT (x) ? ? (((x) & 0x3) << 12) -#define MXC_CSPICTRL_BITCOUNT (x) ? ? ? (((x) & 0xfff) << 20) -#define MXC_CSPICTRL_DATARATE (x) ? ? ? (((x) & 0x7) << 16) -#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) -#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) -#define MXC_CSPICTRL_MAXBITS ? 0xfff - -#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) -#define MAX_SPI_BYTES ?4 +#endif ?static unsigned long spi_bases[] = {
- ? ? ?0x43fa4000,
- ? ? ?0x50010000,
+ ? ? ?MXC_SPI_BASE_ADDRESSES
?};drivers/spi/mxc_spi.c +0
-4-#else -#error "Unsupported architecture" -#endif -?#define OUT ? ?MXC_GPIO_DIRECTION_OUT
?#define
reg_readreadldrivers/spi/mxc_spi.c +1
-1@@ -129,7 +48,7 @@ struct mxc_spi_slave { ? ? ? ?struct spi_slave slave; ? ? ? ?unsigned long ? base; ? ? ? ?u32 ? ? ? ? ? ? ctrl_reg; -#if defined(CONFIG_MX51 ) +#if defined(MXC_ECSPI ) ? ? ? ?u32 ? ? ? ? ? ? cfg_reg;?#endif
? ? ? ?int ? ? ? ? ? ? gpio;drivers/spi/mxc_spi.c +1
-1@@ -167,7 +86,7 @@ u32 get_cspi_div(u32 div) ? ? ? ?return i; ?} -#if defined(CONFIG_MX31 ) || defined(CONFIG_MX35 ) +#ifdef MXC_CSPI ?static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, ? ? ? ? ? ? ? ?unsigned int max_hz, unsigned int mode) ?{@@ -204,7 +123,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, ?}?#endif
drivers/spi/mxc_spi.c +1
-1-#if defined(CONFIG_MX51 ) +#ifdef MXC_ECSPI ?static s32
spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, ? ? ? ? ? ? ? ?unsigned int max_hz, unsigned int mode)
?{drivers/spi/mxc_spi.c +1
-1@@ -316,7 +235,7 @@ int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen, ? ? ? ? ? ? ? ?MXC_CSPICTRL_BITCOUNT(bitlen - 1); ? ? ? ?reg_write(®s->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN); -#ifdef CONFIG_MX51 +#ifdef MXC_ECSPI ? ? ? ?reg_write(®s->cfg, mxcs->cfg_reg);?#endif
--
1.7.1
PATCH 2/3 mx6q: Add support for ECSPI through mxc_spi driver
In reply to Eric Nelson--- arch/arm/include/asm/arch-mx6/imx-regs.h | 44 ++++++++++++++++++++++++++++++ 1 files changed, 44 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx6/imx-regs.h +44 -0
@@ -190,6 +190,50 @@ struct src {u32 gpr10; }; +/* ECSPI registers */ +struct cspi_regs { +u32 rxdata; +u32 txdata; +u32 ctrl; +u32 cfg; +u32 intr; +u32 dma; +u32 stat; +u32 period; +}; + +/* +* CSPI register definitions +*/ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT (x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT (x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV (x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV (x) (((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN (x) (((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN 18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL 4 +#define MXC_CSPICON_PHA 0 +#define MXC_CSPICON_SSPOL 12 +#define MXC_SPI_BASE_ADDRESSES \ + ECSPI1_BASE_ADDR, \ + ECSPI2_BASE_ADDR, \ + ECSPI3_BASE_ADDR, \ + ECSPI4_BASE_ADDR, \ + ECSPI5_BASE_ADDR +struct iim_regs {u32 ctrl;u32 ctrl_set;
Signature · 1 line
1.7.1
PATCH 2/3 mx6q: Add support for ECSPI through mxc_spi driver
Quoted 6 lines · Eric Nelson
Signed-off-by Eric Nelson <[email protected]>Acked-by Dirk Behme <[email protected]>Acked-by Stefano Babic <[email protected]>---
?arch/arm/include/asm/arch-mx6/imx-regs.h | ? 44 ++++++++++++++++++++++++++++++ ?1 files changed, 44 insertions(+), 0 deletions(-)
Quoted 59 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +44
-1@@ -190,6 +190,50 @@ struct src { ? ? ? ?u32 ? ? gpr10; ?}; +/* ECSPI registers */ +struct cspi_regs { + ? ? ? u32 rxdata; + ? ? ? u32 txdata; + ? ? ? u32 ctrl; + ? ? ? u32 cfg; + ? ? ? u32 intr; + ? ? ? u32 dma; + ? ? ? u32 stat; + ? ? ? u32 period; +}; + +/* +* CSPI register definitions +*/ +#define MXC_ECSPI +#define MXC_CSPICTRL_EN ? ? ? ? ? ? ? ?(1 << 0) +#define MXC_CSPICTRL_MODE ? ? ?(1 << 1) +#define MXC_CSPICTRL_XCH ? ? ? (1 << 2) +#define MXC_CSPICTRL_CHIPSELECT (x) ? ? (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT (x) ? ? ? (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_PREDIV (x) (((x) & 0xF) << 12) +#define MXC_CSPICTRL_POSTDIV (x) ? ? ? ?(((x) & 0xF) << 8) +#define MXC_CSPICTRL_SELCHAN (x) ? ? ? ?(((x) & 0x3) << 18) +#define MXC_CSPICTRL_MAXBITS ? 0xfff +#define MXC_CSPICTRL_TC ? ? ? ? ? ? ? ?(1 << 7) +#define MXC_CSPICTRL_RXOVF ? ? (1 << 6) +#define MXC_CSPIPERIOD_32KHZ ? (1 << 15) +#define MAX_SPI_BYTES ?32 + +/* Bit position inside CTRL register to be associated with SS */ +#define MXC_CSPICTRL_CHAN ? ? ?18 + +/* Bit position inside CON register to be associated with SS */ +#define MXC_CSPICON_POL ? ? ? ? ? ? ? ?4 +#define MXC_CSPICON_PHA ? ? ? ? ? ? ? ?0 +#define MXC_CSPICON_SSPOL ? ? ?12 +#define MXC_SPI_BASE_ADDRESSES \ + ? ? ? ECSPI1_BASE_ADDR, \ + ? ? ? ECSPI2_BASE_ADDR, \ + ? ? ? ECSPI3_BASE_ADDR, \ + ? ? ? ECSPI4_BASE_ADDR, \ + ? ? ? ECSPI5_BASE_ADDR + ?struct iim_regs { ? ? ? ?u32 ? ? ctrl; ? ? ? ?u32 ? ? ctrl_set; --1.7.1
PATCH 3/3 mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform
In reply to Eric Nelson--- board/freescale/mx6qsabrelite/imximage.cfg | 2 +- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 25 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 9 +++++++++ 3 files changed, 35 insertions(+), 1 deletions(-)
board/freescale/mx6qsabrelite/imximage.cfg +1 -1
@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006 # set the default clock gate to save power DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03 DATA 4 0x020c4070 0x0FFFC000 DATA 4 0x020c4074 0x3FF00000 DATA 4 0x020c4078 0x00FFF300
board/freescale/mx6qsabrelite/mx6qsabrelite.c +25 -0
@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +int dram_init (void ) { gd->ram_size =get_ram_size ((void *)PHYS_SDRAM ,PHYS_SDRAM_SIZE );
@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis) }#endif +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t ecspi1_pads[] = { +/* SS1 */ +MX6Q_PAD_EIM_D19__GPIO_3_19 |MUX_PAD_CTRL (SPI_PAD_CTRL ), +MX6Q_PAD_EIM_D17__ECSPI1_MISO |MUX_PAD_CTRL (SPI_PAD_CTRL ), +MX6Q_PAD_EIM_D18__ECSPI1_MOSI |MUX_PAD_CTRL (SPI_PAD_CTRL ), +MX6Q_PAD_EIM_D16__ECSPI1_SCLK |MUX_PAD_CTRL (SPI_PAD_CTRL ), +}; + +void setup_spi (void ) +{ +gpio_direction_output (IMX_GPIO_NR (3 ,19 ),1 ); +imx_iomux_v3_setup_multiple_pads (ecspi1_pads, +ARRAY_SIZE (ecspi1_pads)); +} +#endif +#define MII_1000BASET_CTRL 0x9#define MII_EXTENDED_CTRL 0xb#define MII_EXTENDED_DATAW 0xc
@@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis)return ret; } +#ifdef CONFIG_MXC_SPI +setup_spi (); +#endif +return 0 ; }
include/configs/mx6qsabrelite.h +9 -0
@@ -44,6 +44,15 @@#define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif +/* MMC Configs */ #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC
Signature · 1 line
1.7.1
PATCH 3/3 mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform
Eric,
Quoted 8 lines · Eric Nelson
Signed-off-by Eric Nelson <[email protected]>Acked-by Dirk Behme <[email protected]>Acked-by Stefano Babic <[email protected]>---
?board/freescale/mx6qsabrelite/imximage.cfg ? ?| ? ?2 +- ?board/freescale/mx6qsabrelite/mx6qsabrelite.c | ? 25 +++++++++++++++++++++++++ ?include/configs/mx6qsabrelite.h ? ? ? ? ? ? ? | ? ?9 +++++++++?3 files changed, 35 insertions(+), 1 deletions(-)
After apply the patch, I have the build errors:../mx6qsabrelite/mx6qsabrelite.c:211: undefined reference to `IMX_GPIO_NR'
So, the patch should depends on others. If one patch set is depend on others, it's better to tell it
in the cover letter of your patch set. Thanks.
Quoted 87 lines
board/freescale/mx6qsabrelite/imximage.cfg +0
-0@@ -156,7 +156,7 @@ DATA 4 0x021b0404 0x00011006?# set the default clock gate to save power
?DATA 40x020c40680x00C03F3Fboard/freescale/mx6qsabrelite/imximage.cfg +1
-1-DATA 4 0x020c406c 0x0030FC00 +DATA 4 0x020c406c 0x0030FC03?DATA 4
0x020c40700x0FFFC000
?DATA 40x020c40740x3FF00000
?DATA 40x020c40780x00FFF300board/freescale/mx6qsabrelite/mx6qsabrelite.c +4
-0@@ -46,6 +46,10 @@ DECLARE_GLOBAL_DATA_PTR; ? ? ? ?PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED ? | ? ? ? ? ? ? \ ? ? ? ?PAD_CTL_DSE_40ohm ? | PAD_CTL_HYS) +#define SPI_PAD_CTRL (PAD_CTL_HYS | ? ? ? ? ? ? ? ? ? ? ? ? ? ?\ + ? ? ? PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | ? ? ? ? ? ? \ + ? ? ? PAD_CTL_DSE_40ohm ? ? | PAD_CTL_SRE_FAST) + ?int dram_init(void) ?{ ? ? ? ?gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);@@ -193,6 +197,23 @@ int board_mmc_init(bd_t *bis) ?}?#endif
board/freescale/mx6qsabrelite/mx6qsabrelite.c +17
-0+#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t ecspi1_pads[] = { + ? ? ? /* SS1 */ + ? ? ? MX6Q_PAD_EIM_D19__GPIO_3_19 ? | MUX_PAD_CTRL(SPI_PAD_CTRL), + ? ? ? MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + ? ? ? MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + ? ? ? MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; + +void setup_spi (void ) +{ + ? ? ? gpio_direction_output(IMX_GPIO_NR(3, 19), 1); + ? ? ? imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARRAY_SIZE(ecspi1_pads)); +} +#endif +?#define
MII_1000BASET_CTRL? ? ? ? ? ?0x9
?#defineMII_EXTENDED_CTRL? ? ? ? ? ? ?0xb
?#defineMII_EXTENDED_DATAW? ? ? ? ? ?0xcboard/freescale/mx6qsabrelite/mx6qsabrelite.c +4
-0@@ -239,6 +260,10 @@ int board_eth_init(bd_t *bis) ? ? ? ? ? ? ? ?return ret; ? ? ? ?} +#ifdef CONFIG_MXC_SPI + ? ? ? setup_spi(); +#endif + ? ? ? ?return 0; ?}include/configs/mx6qsabrelite.h +0
-0@@ -44,6 +44,15 @@?#define
CONFIG_MXC_UART
?#defineCONFIG_MXC_UART_BASE? ? ? ? ?UART2_BASEinclude/configs/mx6qsabrelite.h +9
-0+#define CONFIG_CMD_SF +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_SPEED 25000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#endif +?/* MMC Configs */
?#defineCONFIG_FSL_ESDHC
?#defineCONFIG_FSL_USDHC
--
1.7.1
PATCH 3/3 mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform
Quoted 13 lines · Jason Hui
Eric,
Quoted 8 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>Acked-by Dirk Behme<[email protected]>Acked-by Stefano Babic<[email protected]>--- board/freescale/mx6qsabrelite/imximage.cfg | 2 +- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 25 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 9 +++++++++ 3 files changed, 35 insertions(+), 1 deletions(-)
Quoted 7 lines
After apply the patch, I have the build errors:
../mx6qsabrelite/mx6qsabrelite.c:211: undefined reference to `IMX_GPIO_NR'So, the patch should depends on others. If one patch set is depend on others, it's better to tell it
in the cover letter of your patch set. Thanks.
Ouch! It's all about the GPIO numbers...
This occurred when I re-based to Stefano's tree and will require another patch to keep the BANK:OFFSET numbering scheme. There's a patch lingering in Dirk's tree that defines IMX_GPIO_NR() in gpio.h.
See http://lists.denx.de/pipermail/u-boot/2012-January/116866.html
for details.
I was hoping to get some feedback before generating a patch and revising this patch (and removing GPIO_3_19 macro):
http://lists.denx.de/pipermail/u-boot/2012-January/116874.html
That said, I'll revise and re-send along with a patch adding support for:
GPIO_NUMBER(port,index)
GPIO_PORT(number)
GPIO_INDEX(number)
PATCH 3/3 mx6q: mx6qsabrelite: Add ECSPI support to the Sabrelite platform
Quoted 3 lines · Eric Nelson
Quoted 2 lines · Jason Hui
Eric,
Hi Eric,
Quoted 8 lines
Ouch! It's all about the GPIO numbers...
This occurred when I re-based to Stefano's tree and will require another patch to keep the BANK:OFFSET numbering scheme. There's a patch lingering in Dirk's tree that defines
IMX_GPIO_NR()ingpio.h.See http://lists.denx.de/pipermail/u-boot/2012-January/116866.html
for details.
Extending the thread you report: the only macro defined in MX I can find is for MX27:
#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f))
but we do not need to stick with it ;-). Using a more general GPIO_ as you proposed is better because we could extend the same macros to other family.
Quoted 11 lines
I was hoping to get some feedback before generating a patch and revising this patch (and removing
GPIO_3_19macro):http://lists.denx.de/pipermail/u-boot/2012-January/116874.html
That said, I'll revise and re-send along with a patch adding support for:
GPIO_NUMBER(port,index)
GPIO_PORT(number)
GPIO_INDEX(number)
Agree with your proposal, good idea !
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================
[U-Boot] MX6q SPI refactoring and related patches
In reply to Eric NelsonI'm about to send an updated set of patches for mxc_spi re-factoring and the related cleanup stemming from the discussions in
http://lists.denx.de/pipermail/u-boot/2012-January/116816.html
These are split into multiple patch sets as suggested by Dirk:
http://lists.denx.de/pipermail/u-boot/2012-January/116865.html
Because these are all re-sends, I'm tagging them as "V6" as requested by Jason:
http://lists.denx.de/pipermail/u-boot/2012-January/116894.html
I'm also including a "PART #" to make it clear which patches are grouped together.
-- Part 1 will contain basic support for translating between
ordinal GPIO numbers and port:index forms.
It is required for parts 2, 4, and 5
-- Part 2 (3 patches) re-factors mxc_spi by moving register
declarations into their arch-specific headers. This changed from the previous submission by using GPIO_NUMBER() instead of the undefined IMX_GPIO_NR().
http://lists.denx.de/pipermail/u-boot/2012-January/116901.html
-- Part 3 (2 patches) allows a board to define default values
for SPI ROM bus and chip-selects and add some documentation for the same. I believe these have already been approved by Mike Frysinger.
-- Part 4 defines defaults for the mx6qsabrelite board. Note
that this is slightly different from previous submission by also changing a reference to GPIO_NUMBER(3,19) to use the new default value (CONFIG_SF_DEFAULT_CS).
-- Part 5 conditionally defines a configuration for use in
booting and saving environment to SPI flash instead of SD card to make it easier to switch between them.
cover mxc_spi refactoring (for mx6q and mx6qsabrelite)
In reply to Eric NelsonEric,
2012/1/31 Eric Nelson <[email protected]>:
Quoted 6 lines
This patch set refactors
mxc_spias described in
? ?http://lists.denx.de/pipermail/u-boot/2010-March/068791.html and requested in
? ?http://lists.denx.de/pipermail/u-boot/2012-January/116023.html in order to add support for the MX6Q in general and the mx6qsabrelite specifically.
If this patch-set is re-send, please specify version Vx and change-log. Thanks,
Quoted 5 lines
Patch 1 simply moves the conditional parts of
mxc_spi.cinto the respective CPU-specificimx-regs.hfiles.Patch 2 adds general support for SPI to the i.MX6.
I can't find the patch 2/3 in my email system, miss it?
Quoted 7 lines
Patch 3 adds support to the mx6qsabrelite board
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
cover mxc_spi refactoring (for mx6q and mx6qsabrelite)
Quoted 13 lines · Jason Liu
Eric,
2012/1/31 Eric Nelson <[email protected]>:
Quoted 6 lines
This patch set refactors
mxc_spias described in
? ?http://lists.denx.de/pipermail/u-boot/2010-March/068791.html and requested in
? ?http://lists.denx.de/pipermail/u-boot/2012-January/116023.html in order to add support for the MX6Q in general and the mx6qsabrelite specifically.If this patch-set is re-send, please specify version Vx and change-log. Thanks,
Quoted 1 line
Quoted 6 lines
Quoted 4 lines
Patch 1 simply moves the conditional parts of
mxc_spi.cinto the respective CPU-specificimx-regs.hfiles.Patch 2 adds general support for SPI to the i.MX6.
I can't find the patch 2/3 in my email system, miss it?
sorry, Ignore it. The email system get messed.
Quoted 8 lines
Quoted 8 lines
Patch 3 adds support to the mx6qsabrelite board
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
cover mxc_spi refactoring (for mx6q and mx6qsabrelite)
In reply to Jason LiuQuoted 12 lines · Jason Liu
Eric,
2012/1/31 Eric Nelson<[email protected]>:
Quoted 6 lines
This patch set refactors
mxc_spias described inhttp://lists.denx.de/pipermail/u-boot/2010-March/068791.html and requested in http://lists.denx.de/pipermail/u-boot/2012-January/116023.htmlin order to add support for the MX6Q in general and the mx6qsabrelite specifically.
If this patch-set is re-send, please specify version Vx and change-log. Thanks,
Hi Jason,
I wasn't quite sure how to handle that, since I split up a 7-patch series into independent parts.
Any guidance?
cover mxc_spi refactoring (for mx6q and mx6qsabrelite)
Eric,
Quoted 17 lines · Eric Nelson
Quoted 13 lines · Jason Liu
Eric,
2012/1/31 Eric Nelson<[email protected]>:
Quoted 7 lines
This patch set refactors
mxc_spias described in
? ?http://lists.denx.de/pipermail/u-boot/2010-March/068791.html and requested in
? ?http://lists.denx.de/pipermail/u-boot/2012-January/116023.html in order to add support for the MX6Q in general and the mx6qsabrelite specifically.Quoted 3 lines
If this patch-set is re-send, please specify version Vx and change-log. Thanks,
Quoted 6 lines
Hi Jason,
I wasn't quite sure how to handle that, since I split up a 7-patch series into independent parts.
Any guidance?
IMHO,
if the patches is resent with changes you need specify Vx and change-log. if the patches is resent with no changes you need have the keywords resend and add some comments blow --- to tell the reader why resend.
Jason