ARM: smp: allow get the core count from L2 control on A15
Subsystems (2)
PATCH 1/1 ARM: smp: allow get the core count from L2 control on A15
Actually, the number of A15 CPU core gets from L2 control register not SCU configuration.
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Hi Russell,
As you know, the method of A15 core counting is different with A9. So the function will be required on that but I'm not sure where the function should be added at.
arch/arm/include/asm/smp.h | 5 +++++ arch/arm/kernel/smp.c | 16 ++++++++++++++++ 2 files changed, 21 insertions(+), 0 deletions(-)
arch/arm/include/asm/smp.h +5 -0
@@ -71,6 +71,11 @@ extern void platform_secondary_init(unsigned int cpu);extern void platform_smp_prepare_cpus (unsigned int );/* +* Get the number of CPU cores from the L2 control register on A15 +*/ +extern unsigned long a15_get_core_count (void ); + +/* * Logical CPU mapping. */ extern int __cpu_logical_map[NR_CPUS ];
arch/arm/kernel/smp.c +16 -0
@@ -233,6 +233,22 @@ void __ref cpu_die(void) }#endif /* CONFIG_HOTPLUG_CPU */ +/* +* Get the number of CPU cores from the L2 control register on A15 +*/ +unsigned long a15_get_core_count (void ) +{ +unsigned long val; + +/* Read L2 control register */ + asmvolatile ("mrc p15, 1, %0, c9, c0, 2" :"=r" (val)); + +/* [25:24] of L2 control register means core count - 1 */ + val = ((val >>24 ) &0x3 ) +1 ; + +return val; +} +int __cpu_logical_map[NR_CPUS ];void __init smp_setup_processor_id (void )
Signature · 1 line
1.7.1
Will Deacon
NAKPATCH 1/1 ARM: smp: allow get the core count from L2 control on A15
Hi Kukjin,
Quoted 8 lines · Kukjin Kim
Actually, the number of A15 CPU core gets from L2 control register not SCU configuration.
Suggested-by Changhwan Youn <[email protected]>Signed-off-by Kukjin Kim <[email protected]>Cc Russell King <[email protected]>---
NAK.
Quoted 29 lines
arch/arm/include/asm/smp.h +5
-0@@ -71,6 +71,11 @@ extern void platform_secondary_init(unsigned int cpu);extern void platform_smp_prepare_cpus (unsigned int );/* +* Get the number of CPU cores from the L2 control register on A15 +*/ +extern unsigned long a15_get_core_count (void ); + +/* * Logical CPU mapping. */ extern int __cpu_logical_map[NR_CPUS ];arch/arm/kernel/smp.c +5
-0@@ -233,6 +233,22 @@ void __ref cpu_die(void) }#endif /* CONFIG_HOTPLUG_CPU */ +/* +* Get the number of CPU cores from the L2 control register on A15 +*/ +unsigned long a15_get_core_count (void ) +{
arch/arm/kernel/smp.c void __ref cpu_die(void) · line 250
Quoted 10 lines
arch/arm/kernel/smp.c +10
-0+unsigned long val; + +/* Read L2 control register */ + asmvolatile ("mrc p15, 1, %0, c9, c0, 2" :"=r" (val)); + +/* [25:24] of L2 control register means core count - 1 */ + val = ((val >>24 ) &0x3 ) +1 ; + +return val; +}
This doesn't belong in smp.c but, more importantly, this doesn't work for multi-cluster configurations at all. Since all A15 implementations will be on new platforms, the code will be device-tree only and so we should use that to determine the CPU topology as, unfortunately, there is no architected way of doing this.
I believe Lorenzo posted some patches which you could look at.
Will
PATCH 1/1 ARM: smp: allow get the core count from L2 control on A15
Quoted 49 lines · Will Deacon
Hi Kukjin,
Quoted 8 lines · Kukjin Kim
Actually, the number of A15 CPU core gets from L2 control register not SCU configuration.
Suggested-by Changhwan Youn<[email protected]>Signed-off-by Kukjin Kim<[email protected]>Cc Russell King<[email protected]>---
NAK.
Quoted 35 lines
arch/arm/include/asm/smp.h +5
-0@@ -71,6 +71,11 @@ extern void platform_secondary_init(unsigned int cpu);extern void platform_smp_prepare_cpus (unsigned int );/* +* Get the number of CPU cores from the L2 control register on A15 +*/ +extern unsigned long a15_get_core_count (void ); + +/* * Logical CPU mapping. */ extern int __cpu_logical_map[NR_CPUS ];arch/arm/kernel/smp.c +11
-0@@ -233,6 +233,22 @@ void __ref cpu_die(void) }#endif /* CONFIG_HOTPLUG_CPU */ +/* +* Get the number of CPU cores from the L2 control register on A15 +*/ +unsigned long a15_get_core_count (void ) +{ +unsigned long val; + +/* Read L2 control register */ + asmvolatile ("mrc p15, 1, %0, c9, c0, 2" :"=r" (val)); + +/* [25:24] of L2 control register means core count - 1 */
Quoted 8 lines
arch/arm/kernel/smp.c void __ref cpu_die(void) · line 250
Quoted 4 lines
arch/arm/kernel/smp.c +4
-0+ val = ((val>>24 )&0x3 ) +1 ; + +return val; +}This doesn't belong in
smp.cbut, more importantly, this doesn't work for multi-cluster configurations at all. Since all A15 implementations will be on new platforms, the code will be device-tree only and so we should use
Why not? As I know, current arm kernel ARMv7 arch can support A15 without device-tree. And you know, the core number should be counted by L2 control register. no?
Quoted 5 lines
that to determine the CPU topology as, unfortunately, there is no architected way of doing this.
I believe Lorenzo posted some patches which you could look at.
OK, Would be better.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
PATCH 1/1 ARM: smp: allow get the core count from L2 control on A15
Quoted 9 lines · Kukjin Kim
Quoted 4 lines · Will Deacon
This doesn't belong in
smp.cbut, more importantly, this doesn't work for multi-cluster configurations at all. Since all A15 implementations will be on new platforms, the code will be device-tree only and so we should useWhy not? As I know, current arm kernel ARMv7 arch can support A15 without device-tree. And you know, the core number should be counted by L2 control register. no?
I'll answer these in order:
1.) The code doesn't belong in smp.c because it's specific to the A15 2.) The architecture code may well support A15, but since there are no
platforms in mainline that support A15 yet, then all new platforms will need to be DT-based. That means we can rely on the DT to provide this information.
3.) The L2 control register only tells you how many cores are hanging off
that particular L2. This will be wrong for multi-cluster systems since it will only identify a subset of the cores.
Quoted 3 lines
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I believe Lorenzo posted some patches which you could look at.
OK, Would be better.
Yes, I think it's the only way to solve this problem without adding an architected method for enumerating the CPU topology.
Will
PATCH 1/1 ARM: smp: allow get the core count from L2 control on A15
Quoted 7 lines · Will Deacon
Quoted 6 lines · Kukjin Kim
Quoted 4 lines · Will Deacon
This doesn't belong in
smp.cbut, more importantly, this doesn't work for multi-cluster configurations at all. Since all A15 implementations will be on new platforms, the code will be device-tree only and so we should use
Quoted 5 lines
Quoted 3 lines
Why not? As I know, current arm kernel ARMv7 arch can support A15 without device-tree. And you know, the core number should be counted by L2 control register. no?
I'll answer these in order:
Hmm, let
Quoted 2 lines
1.) The code doesn't belong in
smp.cbecause it's specific to the A15
Yes, agree. So I just commented in my patch, I'm not sure where it should be added at.
Quoted 4 lines
2.) The architecture code may well support A15, but since there are no
platforms in mainline that support A15 yet, then all new platforms will need to be DT-based. That means we can rely on the DT to provide this information.
Well, I will submit EXYNOS5 which has two A15 cores today and I don't know why it should be supported only with DT, EXYNOS5 DT supporting will be submitted though.
Quoted 3 lines
3.) The L2 control register only tells you how many cores are hanging off
that particular L2. This will be wrong for multi-cluster systems since it will only identify a subset of the cores.
OK, let me check it.
Quoted 8 lines
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Quoted 3 lines
I believe Lorenzo posted some patches which you could look at.
OK, Would be better.
Yes, I think it's the only way to solve this problem without adding an architected method for enumerating the CPU topology.
I'm not sure it is the only way...
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
PATCH 1/1 ARM: smp: allow get the core count from L2 control on A15
Quoted 12 lines · Kukjin Kim
Quoted 11 lines · Will Deacon
Quoted 9 lines · Kukjin Kim
Quoted 4 lines · Will Deacon
This doesn't belong in
smp.cbut, more importantly, this doesn't work for multi-cluster configurations at all. Since all A15 implementations will be on new platforms, the code will be device-tree only and so we should useWhy not? As I know, current arm kernel ARMv7 arch can support A15 without device-tree. And you know, the core number should be counted by L2 control register. no?
Quoted 8 lines
Quoted 1 line
I'll answer these in order:
Hmm, let
Quoted 2 lines
1.) The code doesn't belong in
smp.cbecause it's specific to the A15Yes, agree. So I just commented in my patch, I'm not sure where it should be added at.
I do not think it should be added at all. And if you add it at least add it to your BSP code (not in smp.c), because it works for a single cluster A15 configuration, it does not for other A15 based systems.
I think Will's comment was pretty clear about this.
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2.) The architecture code may well support A15, but since there are no
platforms in mainline that support A15 yet, then all new platforms will need to be DT-based. That means we can rely on the DT to provide this information.Well, I will submit EXYNOS5 which has two A15 cores today and I don't know why it should be supported only with DT, EXYNOS5 DT supporting will be submitted though.
See above.
Quoted 5 lines
Quoted 3 lines
3.) The L2 control register only tells you how many cores are hanging off
that particular L2. This will be wrong for multi-cluster systems since it will only identify a subset of the cores.OK, let me check it.
Check it and you will notice that it does not work for multi-cluster SMP systems.
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I believe Lorenzo posted some patches which you could look at.
OK, Would be better.
Yes, I think it's the only way to solve this problem without adding an architected method for enumerating the CPU topology.
I'm not sure it is the only way...
We are not stating that it is the only way to do it. We are saying it is the only way to do it in a generic way without relying on a per platform hook (if it exists).
If it does not and we rely on this patch, we end up booting only one cluster out of the possible ones, which is awesome.
I am against adding this code for the aforementioned reasons.
Lorenzo
PATCH 1/1 ARM: smp: allow get the core count from L2 control on A15
In reply to Kukjin KimQuoted 14 lines · Kukjin Kim
arch/arm/kernel/smp.c +6
-0@@ -233,6 +233,22 @@ void __ref cpu_die(void) }#endif /* CONFIG_HOTPLUG_CPU */ +/* +* Get the number of CPU cores from the L2 control register on A15 +*/ +unsigned long a15_get_core_count (void ) +{ +unsigned long val;
arch/arm/kernel/smp.c void __ref cpu_die(void) · line 251
Quoted 10 lines
arch/arm/kernel/smp.c +10
-0+ +/* Read L2 control register */ + asmvolatile ("mrc p15, 1, %0, c9, c0, 2" :"=r" (val)); + +/* [25:24] of L2 control register means core count - 1 */ + val = ((val >>24 ) &0x3 ) +1 ; + +return val; +} +
This is *definitely* the wrong place for this. Do we have the reading of the number of cores from the SCU in smp.c ? No. Do we want to litter smp.c with each architecture revisions own way of reading this information? No.
Keep this kind of crap out of the main smp.c file please. It contains zero CPU and platform specifics and should stay that way.