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ARM: EXYNOS: adds dma mdma and for new EXYNOS SoCs

PATCH Superseded Kukjin Kim 2 participants 6 messages Jan 31, 2012 – Feb 9, 2012

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

v1 of 2 Superseded Latest is v2 →

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Kukjin Kim

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#0 lore raw

cover ARM: EXYNOS: adds dma mdma and for new EXYNOS SoCs

This patches are including various suppporting DMA on EXYNOS SoCs like following.

[PATCH 1/3] ARM: EXYNOS: Enable MDMA driver [PATCH 2/3] ARM: EXYNOS: Support DMA for EXYNOS4X12 SoC [PATCH 3/3] ARM: EXYNOS: Support DMA for EXYNOS5250 SoC

author
#1 lore raw

PATCH 1/3 ARM: EXYNOS: Enable MDMA driver

From: Boojin Kim <[email protected]>

This patch adds MDMA platform data and enables
MDMA for DMA memcpy operation for EXYNOS SoCs.

Signed-off-by Boojin Kim <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/clock-exynos4.c           |    9 ++++++
 arch/arm/mach-exynos/dma.c                     |   35 ++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/irqs.h       |    2 +
 arch/arm/mach-exynos/include/mach/map.h        |    3 +-
 arch/arm/plat-samsung/include/plat/dma-pl330.h |    8 +++++
 5 files changed, 56 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/clock-exynos4.c +9 -0
index 411b366b..ffcc46b 100644
@@ -783,6 +783,13 @@ static struct clk exynos4_clk_pdma1 = {
 	.ctrlbit	= (1 << 1),
 };
 
+static struct clk exynos4_clk_mdma1 = {
+	.name		= "dma",
+	.devname	= "dma-pl330.2",
+	.enable		= exynos4_clk_ip_image_ctrl,
+	.ctrlbit	= ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
 struct clk *exynos4_clkset_group_list[] = {
 	[0] = &clk_ext_xtal_mux,
 	[1] = &clk_xusbxti,

@@ -1301,6 +1308,7 @@ static struct clksrc_clk *exynos4_sysclks[] = {
 static struct clk *exynos4_clk_cdev[] = {
 	&exynos4_clk_pdma0,
 	&exynos4_clk_pdma1,
+	&exynos4_clk_mdma,
 };
 
 static struct clksrc_clk *exynos4_clksrc_cdev[] = {

@@ -1329,6 +1337,7 @@ static struct clk_lookup exynos4_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
 	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
 	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma),
 	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
 	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
 	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
arch/arm/mach-exynos/dma.c +35 -0
index b10fcd2..e89329e 100644
@@ -139,6 +139,38 @@ struct amba_device exynos4_device_pdma1 = {
 	.periphid = 0x00041330,
 };
 
+u8 mdma_peri[] = {
+	DMACH_MTOM_0,
+	DMACH_MTOM_1,
+	DMACH_MTOM_2,
+	DMACH_MTOM_3,
+	DMACH_MTOM_4,
+	DMACH_MTOM_5,
+	DMACH_MTOM_6,
+	DMACH_MTOM_7,
+};
+
+struct dma_pl330_platdata exynos4_mdma_pdata = {
+	.nr_valid_peri = ARRAY_SIZE(mdma_peri),
+	.peri_id = mdma_peri,
+};
+
+struct amba_device exynos4_device_mdma = {
+	.dev = {
+		.init_name = "dma-pl330.2",
+		.dma_mask = &dma_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+		.platform_data = &exynos4_mdma_pdata,
+	},
+	.res = {
+		.start = EXYNOS4_PA_MDMA1,
+		.end = EXYNOS4_PA_MDMA1 + SZ_4K,
+		.flags = IORESOURCE_MEM,
+	},
+	.irq = {IRQ_MDMA1, NO_IRQ},
+	.periphid = 0x00041330,
+};
+
 static int __init exynos4_dma_init(void)
 {
 	if (of_have_populated_dt())

@@ -152,6 +184,9 @@ static int __init exynos4_dma_init(void)
 	dma_cap_set(DMA_CYCLIC, exynos4_pdma1_pdata.cap_mask);
 	amba_device_register(&exynos4_device_pdma1, &iomem_resource);
 
+	dma_cap_set(DMA_MEMCPY, exynos4_mdma_pdata.cap_mask);
+	amba_device_register(&exynos4_device_mdma, &iomem_resource);
+
 	return 0;
 }
 arch_initcall(exynos4_dma_init);
arch/arm/mach-exynos/include/mach/irqs.h +2 -0
index acf998f..874e224 100644
@@ -45,6 +45,8 @@
 #define IRQ_EINT15		IRQ_SPI(31)
 #define IRQ_EINT16_31		IRQ_SPI(32)
 
+#define IRQ_MDMA0		IRQ_SPI(33)
+#define IRQ_MDMA1		IRQ_SPI(34)
 #define IRQ_PDMA0		IRQ_SPI(35)
 #define IRQ_PDMA1		IRQ_SPI(36)
 #define IRQ_TIMER0_VIC		IRQ_SPI(37)
arch/arm/mach-exynos/include/mach/map.h +2 -1
index b157eb4..0691ca8 100644
@@ -80,7 +80,8 @@
 #define EXYNOS4_PA_TWD			0x10500600
 #define EXYNOS4_PA_L2CC			0x10502000
 
-#define EXYNOS4_PA_MDMA			0x10810000
+#define EXYNOS4_PA_MDMA0		0x10810000
+#define EXYNOS4_PA_MDMA1		0x12840000
 #define EXYNOS4_PA_PDMA0		0x12680000
 #define EXYNOS4_PA_PDMA1		0x12690000
arch/arm/plat-samsung/include/plat/dma-pl330.h +8 -0
index c5eaad5..ecf23a8 100644
@@ -82,6 +82,14 @@ enum dma_ch {
 	DMACH_SLIMBUS4_TX,
 	DMACH_SLIMBUS5_RX,
 	DMACH_SLIMBUS5_TX,
+	DMACH_MTOM_0,
+	DMACH_MTOM_1,
+	DMACH_MTOM_2,
+	DMACH_MTOM_3,
+	DMACH_MTOM_4,
+	DMACH_MTOM_5,
+	DMACH_MTOM_6,
+	DMACH_MTOM_7,
 	/* END Marker, also used to denote a reserved channel */
 	DMACH_MAX,
 };
Signature · 1 line
1.7.4.4
#2 lore raw

PATCH 1/3 ARM: EXYNOS: Enable MDMA driver

Quoted 20 lines · Kukjin Kim

From: Boojin Kim <[email protected]>

This patch adds MDMA platform data and enables
MDMA for DMA memcpy operation for EXYNOS SoCs.

Signed-off-by Boojin Kim <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/clock-exynos4.c           |    9 ++++++
 arch/arm/mach-exynos/dma.c                     |   35 ++++++++++++++++++++++++
 arch/arm/mach-exynos/include/mach/irqs.h       |    2 +
 arch/arm/mach-exynos/include/mach/map.h        |    3 +-
 arch/arm/plat-samsung/include/plat/dma-pl330.h |    8 +++++
 5 files changed, 56 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/clock-exynos4.c +0 -0
index 411b366b..ffcc46b 100644

arch/arm/mach-exynos/clock-exynos4.c static struct clk exynos4_clk_pdma1 = { · line 786

Quoted 4 lines
arch/arm/mach-exynos/clock-exynos4.c +1 -0
@@ -783,6 +783,13 @@ static struct clk exynos4_clk_pdma1 = {
 	.ctrlbit	= (1 << 1),
 };
 
+static struct clk exynos4_clk_mdma1 = {

exynos4_clk_mdma ?

Quoted 25 lines
arch/arm/mach-exynos/clock-exynos4.c +8 -0
+	.name		= "dma",
+	.devname	= "dma-pl330.2",
+	.enable		= exynos4_clk_ip_image_ctrl,
+	.ctrlbit	= ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
 struct clk *exynos4_clkset_group_list[] = {
 	[0] = &clk_ext_xtal_mux,
 	[1] = &clk_xusbxti,

@@ -1301,6 +1308,7 @@ static struct clksrc_clk *exynos4_sysclks[] = {
 static struct clk *exynos4_clk_cdev[] = {
 	&exynos4_clk_pdma0,
 	&exynos4_clk_pdma1,
+	&exynos4_clk_mdma,
 };
 
 static struct clksrc_clk *exynos4_clksrc_cdev[] = {

@@ -1329,6 +1337,7 @@ static struct clk_lookup exynos4_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
 	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
 	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma),
 	CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
 	CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
 	CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
Signature · 1 line
Tushar Behera
author
#3 lore raw

PATCH 1/3 ARM: EXYNOS: Enable MDMA driver

Quoted 6 lines · Tushar Behera
Quoted 4 lines · Kukjin Kim

From: Boojin Kim <[email protected]>

This patch adds MDMA platform data and enables
MDMA for DMA memcpy operation for EXYNOS SoCs.

[...]

Quoted 4 lines
Quoted 1 line

+static struct clk exynos4_clk_mdma1 = {

exynos4_clk_mdma ?

Boojin, could you please explain why you used 'exynos4_clk_mdma1' instead of just mdma here?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

author
#4 lore raw

PATCH 2/3 ARM: EXYNOS: Support DMA for EXYNOS4X12 SoC

In reply to Kukjin Kim

From: Boojin Kim <[email protected]>

Signed-off-by Boojin Kim <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/Kconfig                   |    4 +
 arch/arm/mach-exynos/clock-exynos4.c           |    2 +-
 arch/arm/mach-exynos/dma.c                     |   95 ++++++++++++++++++++++--
 arch/arm/plat-samsung/include/plat/dma-pl330.h |    8 ++
 4 files changed, 100 insertions(+), 9 deletions(-)
arch/arm/mach-exynos/Kconfig +4 -0
index 89b8e17..0d8677e 100644
@@ -47,6 +47,7 @@ config SOC_EXYNOS4212
 	bool "SAMSUNG EXYNOS4212"
 	default y
 	depends on ARCH_EXYNOS4
+	select SAMSUNG_DMADEV
 	select S5P_PM if PM
 	select S5P_SLEEP if PM
 	help

@@ -56,6 +57,7 @@ config SOC_EXYNOS4412
 	bool "SAMSUNG EXYNOS4412"
 	default y
 	depends on ARCH_EXYNOS4
+	select SAMSUNG_DMADEV
 	help
 	  Enable EXYNOS4412 SoC support
 

@@ -346,6 +348,7 @@ config MACH_SMDK4212
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_KEYPAD
 	select SAMSUNG_DEV_PWM
+	select EXYNOS4_DEV_DMA
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
 	select EXYNOS4_SETUP_I2C7

@@ -360,6 +363,7 @@ config MACH_SMDK4412
 	bool "SMDK4412"
 	select SOC_EXYNOS4412
 	select MACH_SMDK4212
+	select EXYNOS4_DEV_DMA
 	help
 	  Machine support for Samsung SMDK4412
 endif
arch/arm/mach-exynos/clock-exynos4.c +1 -1
index ffcc46b..a1f118e 100644
@@ -783,7 +783,7 @@ static struct clk exynos4_clk_pdma1 = {
 	.ctrlbit	= (1 << 1),
 };
 
-static struct clk exynos4_clk_mdma1 = {
+static struct clk exynos4_clk_mdma = {
 	.name		= "dma",
 	.devname	= "dma-pl330.2",
 	.enable		= exynos4_clk_ip_image_ctrl,
arch/arm/mach-exynos/dma.c +87 -8

135 lines not on this page · raw message

arch/arm/plat-samsung/include/plat/dma-pl330.h +8 -0
index ecf23a8..0670f37 100644
@@ -82,6 +82,14 @@ enum dma_ch {
 	DMACH_SLIMBUS4_TX,
 	DMACH_SLIMBUS5_RX,
 	DMACH_SLIMBUS5_TX,
+	DMACH_MIPI_HSI0,
+	DMACH_MIPI_HSI1,
+	DMACH_MIPI_HSI2,
+	DMACH_MIPI_HSI3,
+	DMACH_MIPI_HSI4,
+	DMACH_MIPI_HSI5,
+	DMACH_MIPI_HSI6,
+	DMACH_MIPI_HSI7,
 	DMACH_MTOM_0,
 	DMACH_MTOM_1,
 	DMACH_MTOM_2,
Signature · 1 line
1.7.4.4
author
#5 lore raw

PATCH 3/3 ARM: EXYNOS: Support DMA for EXYNOS5250 SoC

In reply to Kukjin Kim

From: Boojin Kim <[email protected]>

Signed-off-by Boojin Kim <[email protected]>
Signed-off-by Kukjin Kim <[email protected]>
---
 arch/arm/mach-exynos/Kconfig                   |   18 ++--
 arch/arm/mach-exynos/Makefile                  |    2 +-
 arch/arm/mach-exynos/clock-exynos5.c           |   14 +-
 arch/arm/mach-exynos/dma.c                     |  143 ++++++++++++++++++------
 arch/arm/mach-exynos/include/mach/map.h        |   10 ++
 arch/arm/plat-samsung/Kconfig                  |    2 +-
 arch/arm/plat-samsung/include/plat/dma-pl330.h |    1 +
 7 files changed, 140 insertions(+), 50 deletions(-)
arch/arm/mach-exynos/Kconfig +10 -8
index 0d8677e..745fdfd 100644
@@ -65,6 +65,7 @@ config SOC_EXYNOS5250
 	bool "SAMSUNG EXYNOS5250"
 	default y
 	depends on ARCH_EXYNOS5
+	select SAMSUNG_DMADEV
 	help
 	  Enable EXYNOS5250 SoC support
 

@@ -74,7 +75,7 @@ config EXYNOS4_MCT
 	help
 	  Use MCT (Multi Core Timer) as kernel timers
 
-config EXYNOS4_DEV_DMA
+config EXYNOS_DEV_DMA
 	bool
 	help
 	  Compile in amba device definitions for DMA controller

@@ -209,7 +210,7 @@ config MACH_SMDKV310
 	select SAMSUNG_DEV_BACKLIGHT
 	select EXYNOS4_DEV_AHCI
 	select SAMSUNG_DEV_KEYPAD
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_DEV_PD
 	select SAMSUNG_DEV_PWM
 	select EXYNOS4_DEV_USB_OHCI

@@ -231,7 +232,7 @@ config MACH_ARMLEX4210
 	select S3C_DEV_HSMMC2
 	select S3C_DEV_HSMMC3
 	select EXYNOS4_DEV_AHCI
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_DEV_SYSMMU
 	select EXYNOS4_SETUP_SDHCI
 	help

@@ -257,7 +258,7 @@ config MACH_UNIVERSAL_C210
 	select S5P_DEV_MFC
 	select S5P_DEV_ONENAND
 	select S5P_DEV_TV
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_DEV_PD
 	select EXYNOS4_SETUP_FIMD0
 	select EXYNOS4_SETUP_I2C1

@@ -291,7 +292,7 @@ config MACH_NURI
 	select S5P_DEV_MFC
 	select S5P_DEV_USB_EHCI
 	select S5P_SETUP_MIPIPHY
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_DEV_PD
 	select EXYNOS4_SETUP_FIMC
 	select EXYNOS4_SETUP_FIMD0

@@ -324,7 +325,7 @@ config MACH_ORIGEN
 	select S5P_DEV_USB_EHCI
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_PWM
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_DEV_PD
 	select EXYNOS4_DEV_USB_OHCI
 	select EXYNOS4_SETUP_FIMD0

@@ -348,7 +349,7 @@ config MACH_SMDK4212
 	select SAMSUNG_DEV_BACKLIGHT
 	select SAMSUNG_DEV_KEYPAD
 	select SAMSUNG_DEV_PWM
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	select EXYNOS4_SETUP_I2C1
 	select EXYNOS4_SETUP_I2C3
 	select EXYNOS4_SETUP_I2C7

@@ -363,7 +364,7 @@ config MACH_SMDK4412
 	bool "SMDK4412"
 	select SOC_EXYNOS4412
 	select MACH_SMDK4212
-	select EXYNOS4_DEV_DMA
+	select EXYNOS_DEV_DMA
 	help
 	  Machine support for Samsung SMDK4412
 endif

@@ -375,6 +376,7 @@ comment "EXYNOS5250 Boards"
 config MACH_SMDK5250
 	bool "SMDK5250"
 	select SOC_EXYNOS5250
+	select EXYNOS_DEV_DMA
 	help
 	  Machine support for Samsung SMDK4412
 endif
arch/arm/mach-exynos/Makefile +1 -1
index 1b12345..eccadc8 100644
@@ -52,7 +52,7 @@ obj-$(CONFIG_EXYNOS4_DEV_AHCI)		+= dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)		+= dev-pd.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)	+= dev-sysmmu.o
 obj-$(CONFIG_EXYNOS4_DEV_DWMCI)		+= dev-dwmci.o
-obj-$(CONFIG_EXYNOS4_DEV_DMA)		+= dma.o
+obj-$(CONFIG_EXYNOS_DEV_DMA)		+= dma.o
 obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI)	+= dev-ohci.o
 
 obj-$(CONFIG_ARCH_EXYNOS)		+= setup-i2c0.o
arch/arm/mach-exynos/clock-exynos5.c +7 -7
index b0c4478..b43161b 100644
@@ -681,8 +681,8 @@ static struct clk exynos5_init_clocks_on[] = {
 static struct clk exynos5_clk_pdma0 = {
 	.name		= "dma",
 	.devname	= "dma-pl330.0",
-	.enable		= exynos5_clk_ip_gen_ctrl,
-	.ctrlbit	= (1 << 4),
+	.enable		= exynos5_clk_ip_fsys_ctrl,
+	.ctrlbit	= (1 << 1),
 };
 
 static struct clk exynos5_clk_pdma1 = {

@@ -692,11 +692,11 @@ static struct clk exynos5_clk_pdma1 = {
 	.ctrlbit	= (1 << 1),
 };
 
-static struct clk exynos5_clk_pdma2 = {
+static struct clk exynos5_clk_mdma = {
 	.name		= "dma",
 	.devname	= "dma-pl330.2",
-	.enable		= exynos5_clk_ip_fsys_ctrl,
-	.ctrlbit	= (1 << 1),
+	.enable		= exynos5_clk_ip_gen_ctrl,
+	.ctrlbit	= (1 << 4),
 };
 
 struct clk *exynos5_clkset_group_list[] = {

@@ -982,7 +982,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 static struct clk *exynos5_clk_cdev[] = {
 	&exynos5_clk_pdma0,
 	&exynos5_clk_pdma1,
-	&exynos5_clk_pdma2,
+	&exynos5_clk_mdma,
 };
 
 static struct clksrc_clk *exynos5_clksrc_cdev[] = {

@@ -1007,7 +1007,7 @@ static struct clk_lookup exynos5_clk_lookup[] = {
 	CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
 	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
 	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
-	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_pdma2),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma),
 };
 
 static unsigned long exynos5_epll_get_rate(struct clk *clk)
arch/arm/mach-exynos/dma.c +110 -33

205 lines not on this page · raw message

arch/arm/mach-exynos/include/mach/map.h +10 -0
index 0691ca8..35a696d 100644
@@ -84,6 +84,10 @@
 #define EXYNOS4_PA_MDMA1		0x12840000
 #define EXYNOS4_PA_PDMA0		0x12680000
 #define EXYNOS4_PA_PDMA1		0x12690000
+#define EXYNOS5_PA_MDMA0		0x10800000
+#define EXYNOS5_PA_MDMA1		0x11c10000
+#define EXYNOS5_PA_PDMA0		0x121a0000
+#define EXYNOS5_PA_PDMA1		0x121b0000
 
 #define EXYNOS4_PA_SYSMMU_MDMA		0x10A40000
 #define EXYNOS4_PA_SYSMMU_SSS		0x10A50000

@@ -206,10 +210,16 @@
 
 #ifdef CONFIG_ARCH_EXYNOS4
 #define S3C_PA_UART			EXYNOS4_PA_UART
+#define EXYNOS_PA_PDMA0			EXYNOS4_PA_PDMA0
+#define EXYNOS_PA_PDMA1			EXYNOS4_PA_PDMA1
+#define EXYNOS_PA_MDMA1			EXYNOS4_PA_MDMA1
 #endif
 
 #ifdef CONFIG_ARCH_EXYNOS5
 #define S3C_PA_UART			EXYNOS5_PA_UART
+#define EXYNOS_PA_PDMA0			EXYNOS5_PA_PDMA0
+#define EXYNOS_PA_PDMA1			EXYNOS5_PA_PDMA1
+#define EXYNOS_PA_MDMA1			EXYNOS5_PA_MDMA1
 #endif
 
 #define S3C_VA_UARTx(x)			(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
arch/arm/plat-samsung/Kconfig +1 -1
index 0a23b52..88e6a4f 100644
@@ -298,7 +298,7 @@ config S3C_DMA
 config SAMSUNG_DMADEV
 	bool
 	select DMADEVICES
-	select PL330_DMA if (CPU_EXYNOS4210 || CPU_S5PV210 || CPU_S5PC100 || \
+	select PL330_DMA if (ARCH_EXYNOS5 || ARCH_EXYNOS4 || CPU_S5PV210 || CPU_S5PC100 || \
 					CPU_S5P6450 || CPU_S5P6440)
 	select ARM_AMBA
 	help
arch/arm/plat-samsung/include/plat/dma-pl330.h +1 -0
index 0670f37..d384a80 100644
@@ -90,6 +90,7 @@ enum dma_ch {
 	DMACH_MIPI_HSI5,
 	DMACH_MIPI_HSI6,
 	DMACH_MIPI_HSI7,
+	DMACH_DISP1,
 	DMACH_MTOM_0,
 	DMACH_MTOM_1,
 	DMACH_MTOM_2,
Signature · 1 line
1.7.4.4