tegra: Add fdt definitions and USB driver

This series brings in the Linux kernel fdt file and provides a working USB driver for Tegra2 Seaboard.

(I have done this in one series since otherwise most of the fdt additions will just look like dead code.)

The driver requires CONFIG_OF_CONTROL and a device tree to operate.

Some enhancements to fdtdec are required to make this easier, and these are included in the series also. I have had to bring in basic GPIO support due to the request to put the USB VBUS into the fdt.

Since the kernel recently got a very minimal USB binding, I have started with that and extended it where appropriate.

Tegra likes to have cache-aligned buffers. I have dropped the patch which implements this since we will solve this problem by making callers align their buffers (as we did with MMC).

Changes in v2:
- Add setting of pinmux for USB VBUS GPIO
- Decode USB VBUS GPIO from the fdt
- Decode phy type differently (to match new kernel fdt)
- Improve debug() printouts in case of failure to init USB
- Remove 0x from fdt aliases
- Remove non-fdt operation of USB, since it is not needed
- Remove unneeded CONFIG_TEGRA_USBx defines
- Rename params to timing
- Rename tegra20-usb to tegra20-ehcui (to match new kernel fdt)
- Store entire fdt config in port list, not just register pointer
- Use "okay" instead of "ok" for fdt node status

Changes in v3:
- Disable USB2 which is not used on Seaboard
- Drop Tegra USB alignment patch as we will deal with this another way
- Fix device tree indenting with tabs instead of spaces
- Remove "okay" from nodes since this is the default anyway
- Remove usbparams properties from fdt and moved them to C code

Changes in v4:
- Add clock bindings for Tegra2x
- Add fdtdec function to return peripheral ID
- Add staging area for device tree bindings used in U-Boot
- Use peripheral clock node to obtain peripheral ID
- Use updated fdtdec alias functiona to get USB aliases

Changes in v5:
- Add CONFIG_EHCI_DCACHE which is needed for dcache operation
- Add additional debugging to report active USB ports
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Allow any port to operate in otg mode
- Change device tree comment style from // to /* */
- Correct PTS_MASK value to be unsigned
- Drop unused CONFIG_USB_EHCI_DATA_ALIGN option
- Fixed endian bug in fdtdec_decode_gpios()
- Implement new device tree properties
- Make sure GPIO name is NULL if incorrectly decoded
- Put pinmux setting into a board-specific function
- Remove checking of peripheral ID and try to use only device tree
- Remove support-host-mode property
- Report error if phy clock does not start up
- Update README to indicate that we will commit fdt documentation to U-Boot

Simon Glass (18):
fdt: Add basic support for decoding GPIO definitions
arm: fdt: Ensure that an embedded fdt is word-aligned
arm: fdt: Add skeleton device tree file from kernel
tegra: fdt: Add Tegra2x device tree file from kernel
tegra: fdt: Add device tree file for Tegra2 Seaboard from kernel
fdt: Add staging area for device tree binding documentation
fdt: Add tegra-usb bindings file from linux
tegra: fdt: Add additional USB binding
tegra: fdt: Add clock bindings
tegra: usb: fdt: Add additional device tree definitions for USB ports
tegra: usb: fdt: Add USB definitions for Tegra2 Seaboard
usb: Add support for txfifo threshold
fdt: Add function to return peripheral/clock ID
tegra: usb: Add support for Tegra USB peripheral
tegra: usb: Add USB support to nvidia boards
tegra: usb: Add common USB defines for tegra2 boards
tegra: usb: Enable USB on Seaboard
tegra: fdt: Enable FDT support for Seaboard

 README                                         |    3 +
 arch/arm/cpu/armv7/tegra2/Makefile             |    4 +-
 arch/arm/cpu/armv7/tegra2/config.mk            |    2 +
 arch/arm/cpu/armv7/tegra2/usb.c                |  460 ++++++++++++++++++++++++
 arch/arm/cpu/armv7/u-boot.lds                  |    5 +
 arch/arm/dts/skeleton.dtsi                     |   13 +
 arch/arm/dts/tegra20.dtsi                      |  202 +++++++++++
 arch/arm/include/asm/arch-tegra2/tegra2.h      |    2 +
 arch/arm/include/asm/arch-tegra2/usb.h         |  252 +++++++++++++
 board/nvidia/common/board.c                    |   12 +
 board/nvidia/common/board.h                    |    6 +
 board/nvidia/dts/tegra2-seaboard.dts           |   46 +++
 board/nvidia/seaboard/seaboard.c               |    6 +
 doc/device-tree-bindings/README                |   17 +
 doc/device-tree-bindings/clock/tegra-periphclk |   51 +++
 doc/device-tree-bindings/usb/tegra-usb.txt     |   25 ++
 drivers/usb/host/Makefile                      |    1 +
 drivers/usb/host/ehci-hcd.c                    |    7 +
 drivers/usb/host/ehci-tegra.c                  |   62 ++++
 drivers/usb/host/ehci.h                        |    6 +-
 dts/Makefile                                   |    2 +-
 include/configs/seaboard.h                     |   12 +
 include/configs/tegra2-common.h                |   10 +
 include/fdtdec.h                               |   59 +++
 lib/fdtdec.c                                   |   93 +++++
 25 files changed, 1355 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c
 create mode 100644 arch/arm/dts/skeleton.dtsi
 create mode 100644 arch/arm/dts/tegra20.dtsi
 create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h
 create mode 100644 board/nvidia/dts/tegra2-seaboard.dts
 create mode 100644 doc/device-tree-bindings/README
 create mode 100644 doc/device-tree-bindings/clock/tegra-periphclk
 create mode 100644 doc/device-tree-bindings/usb/tegra-usb.txt
 create mode 100644 drivers/usb/host/ehci-tegra.c

1.7.7.3

This adds some support into fdtdec for reading GPIO definitions from the fdt. We permit up to FDT_GPIO_MAX GPIOs in the system. Each GPIO is of the form:

gpio-function-name = <phandle gpio_num flags>;

where:

phandle is a pointer to the GPIO node
gpio_num is the number of the GPIO (0 to 223)
flags is a flag, as follows:

bit meaning
0 0=polarity normal, 1=active low (inverted)

An example is:

enable-propounder-gpios = <&gpio 43 0>;

which means that GPIO 43 is used to enable the propounder (setting the GPIO high), or that you can detect that the propounder is enabled by checking if the GPIO is high (the fdt does not indicate input/output).

Two main functions are provided:

fdtdec_decode_gpio() reads a GPIO property from an fdt node and decodes it into a structure.

fdtdec_setup_gpio() sets up the GPIO by calling gpio_request for you.

Both functions can cope with the property being missing, which is taken to mean that that GPIO function is not available or is not needed.

[For reference, from Stephen Warren <[email protected]>. It may be that we add this extra complexity later if needed:

The correct way to parse such a GPIO property in general is:

* Read the first cell.
* Find the node referenced by the phandle (the controller).
* Ensure property gpio-controller is present in the controller node.
* Read property #gpio-cells from the controller node.
* Extract #gpio-cells from the original property.
* Keep processing more cells from the original property; there may be multiple GPIOs listed.

According to the binding documentation in the Linux kernel, Samsung Exynos4 doesn't use this format, and while all other chips do have a flags cell, about 50% of the controllers indicate the cell is unused. ]

---
Changes in v5:
- Fixed endian bug in fdtdec_decode_gpios()
- Make sure GPIO name is NULL if incorrectly decoded

 include/fdtdec.h |   45 ++++++++++++++++++++++++++++++
 lib/fdtdec.c     |   79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 124 insertions(+), 0 deletions(-)

index 047f603..6c0a2d1 100644
@@ -61,6 +61,23 @@ enum fdt_compat_id {
 	COMPAT_COUNT,
 };
 
+/* GPIOs are numbered from 0 */
+enum {
+	FDT_GPIO_NONE = -1U,	/* an invalid GPIO used to end our list */
+
+	FDT_GPIO_ACTIVE_LOW = 1 << 0,	/* input is active low (else high) */
+};
+
+/* This is the state of a GPIO pin as defined by the fdt */
+struct fdt_gpio_state {
+	const char *name;	/* name of the fdt property defining this */
+	uint gpio;		/* GPIO number, or FDT_GPIO_NONE if none */
+	u8 flags;		/* FDT_GPIO_... flags */
+};
+
+/* This tells us whether a fdt_gpio_state record is valid or not */
+#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE)
+
 /**
  * Find the next numbered alias for a peripheral. This is used to enumerate
  * all the peripherals of a certain type.

@@ -227,3 +244,31 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
  * @return 1 if the properly is present; 0 if it isn't present
  */
 int fdtdec_get_bool(const void *blob, int node, const char *prop_name);
+
+/**
+ * Decode a single GPIOs from an FDT.
+ *
+ * If the property is not found, then the GPIO structure will still be
+ * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to
+ * provide optional GPIOs.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @param prop_name	Node property name
+ * @param gpio		gpio elements to fill from FDT
+ * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing.
+ */
+int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
+		struct fdt_gpio_state *gpio);
+
+/**
+ * Set up a GPIO pin according to the provided gpio information. At present this
+ * just requests the GPIO.
+ *
+ * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to
+ * deal with optional GPIOs.
+ *
+ * @param gpio		GPIO info to use for set up
+ * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error
+ */
+int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);

1.7.7.3

By putting the fdt blob into a distinctive area we can ensure that it appears at the start of the data section and is word-aligned.

Note: It does not seem to be possible to get objcopy to honour its --section-alignment flag, which would otherwise provide an easier fix for this problem.

---

 arch/arm/cpu/armv7/u-boot.lds |    5 +++++
 dts/Makefile                  |    2 +-
 2 files changed, 6 insertions(+), 1 deletions(-)

index 40ecf78..793e51b 100644
@@ -43,6 +43,11 @@ SECTIONS
 
 	. = ALIGN(4);
 	.data : {
+		/*
+		 * Sadly objcopy seems to ignore --section-alignment.
+		 * Put any embedded device tree first so it is aligned.
+		 */
+		*(.dts.data)
 		*(.data)
 	}
 

index 5792afd..83547d4 100644
@@ -79,7 +79,7 @@ $(obj)dt.o: $(DT_BIN)
 	\
 	cd $(dir ${DT_BIN}) && \
 	$(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \
-		$(notdir ${DT_BIN}) $@
+		--prefix-sections=.dts $(notdir ${DT_BIN}) $@
 	rm $(DT_BIN)
 
 OBJS-$(CONFIG_OF_EMBED)	:= dt.o

1.7.7.3

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

---

 arch/arm/dts/skeleton.dtsi |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/skeleton.dtsi

new file mode 100644
index 0000000..b41d241
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+	memory { device_type = "memory"; reg = <0 0>; };
+};

1.7.7.3

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

config.mk is updated to provide this file to boards through the built-in mechanism:

/include/ ARCH_CPU_DTS

---

 arch/arm/cpu/armv7/tegra2/config.mk |    2 +
 arch/arm/dts/tegra20.dtsi           |  168 +++++++++++++++++++++++++++++++++++
 2 files changed, 170 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/dts/tegra20.dtsi

index 2303dba..fe9ef5b 100644
@@ -31,3 +31,5 @@ CFLAGS_arch/arm/lib/board.o += -march=armv4t
 endif
 
 USE_PRIVATE_LIBGCC = yes
+
+CONFIG_ARCH_DEVICE_TREE := tegra20

1.7.7.3

This was taken from commit b48c54e2 at:
git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra.git

---

 board/nvidia/dts/tegra2-seaboard.dts |   36 ++++++++++++++++++++++++++++++++++
 1 files changed, 36 insertions(+), 0 deletions(-)
 create mode 100644 board/nvidia/dts/tegra2-seaboard.dts

new file mode 100644
index 0000000..dde5d03
@@ -0,0 +1,36 @@
+/dts-v1/;
+
+/memreserve/ 0x1c000000 0x04000000;
+/include/ ARCH_CPU_DTS
+
+/ {
+	model = "NVIDIA Seaboard";
+	compatible = "nvidia,seaboard", "nvidia,tegra20";
+
+	chosen {
+		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = < 0x00000000 0x40000000 >;
+	};
+
+	serial@70006300 {
+		clock-frequency = < 216000000 >;
+	};
+
+	sdhci@c8000400 {
+		cd-gpios = <&gpio 69 0>; /* gpio PI5 */
+		wp-gpios = <&gpio 57 0>; /* gpio PH1 */
+		power-gpios = <&gpio 70 0>; /* gpio PI6 */
+	};
+
+	sdhci@c8000600 {
+		support-8bit;
+	};
+
+	usb@c5000000 {
+		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
+	};
+};

1.7.7.3

Add a directory to hold device tree binding files, to permit easy review of this material in U-Boot patches.

---
Changes in v4:
- Add staging area for device tree bindings used in U-Boot

Changes in v5:
- Update README to indicate that we will commit fdt documentation to U-Boot

 doc/device-tree-bindings/README |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/README

new file mode 100644
index 0000000..2ea3439
@@ -0,0 +1,17 @@
+Device Tree Bindings Staging Area
+=================================
+
+This directory contains device tree bindings for U-Boot.
+
+These follow along with Linux kernel bindings, with a few additions. By
+adding the files here, U-Boot patches can clearly show thees additions.
+This makes it easier for device tree people to review these additions in
+patches sent to the U-Boot mailing list.
+
+The intent IS to commit these files to U-Boot. Hopefully at some point
+the files will be stored in another repo (shared with Linux) which is
+brought in as needed. Changes here are intended to mirror changes in the
+Linux Documentation/devicetree/bindings/ directory.
+
[email protected]
+17-Jan-12

1.7.7.3

This file is taken from the Linux mailing list.

---

 doc/device-tree-bindings/usb/tegra-usb.txt |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/usb/tegra-usb.txt

new file mode 100644
index 0000000..035d63d
@@ -0,0 +1,13 @@
+Tegra SOC USB controllers
+
+The device node for a USB controller that is part of a Tegra
+SOC is as described in the document "Open Firmware Recommended
+Practice : Universal Serial Bus" with the following modifications
+and additions :
+
+Required properties :
+ - compatible : Should be "nvidia,tegra20-ehci" for USB controllers
+   used in host mode.
+ - phy_type : Should be one of "ulpi" or "utmi".
+ - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
+   activated for the bus to be powered.

1.7.7.3

This adds a property to indicate a port which can switch between host and device mode.

---
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments

 doc/device-tree-bindings/usb/tegra-usb.txt |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

index 035d63d..b7174a3 100644
@@ -11,3 +11,15 @@ Required properties :
  - phy_type : Should be one of "ulpi" or "utmi".
  - nvidia,vbus-gpio : If present, specifies a gpio that needs to be
    activated for the bus to be powered.
+
+Optional properties:
+  - dr_mode : dual role mode. Indicates the working mode for
+   nvidia,tegra20-ehci compatible controllers.  Can be "host", "peripheral",
+   or "otg".  Default to "host" if not defined for backward compatibility.
+      host means this is a host controller
+      peripheral means it is device controller
+      otg means it can operate as either ("on the go")
+  - nvidia,has-legacy-mode : boolean indicates whether this controller can
+    operate in legacy mode (as APX 2500 / 2600). In legacy mode some
+    registers are accessed through the APB_MISC base address instead of
+    the USB controller.

1.7.7.3

...

...

...

nvpublic

Hi Stephen,

I prefer this because this is a legacy issue, and I feel that creating a different compatible node when no one actually uses legacy mode is an unnecessary complexity.

OK I have done this.

Regards,
Simon

This adds a basic binding for the oscillator and peripheral clocks. The second cell is the clock number, defined as the bit number within the clock enable register if the peripheral clock.

This uses the RFC clock bindings from Grant Likely so may change later:

https://lkml.org/lkml/2011/12/12/498

---
Changes in v4:
- Add clock bindings for Tegra2x

 arch/arm/dts/tegra20.dtsi                      |   27 ++++++++++++
 doc/device-tree-bindings/clock/tegra-periphclk |   51 ++++++++++++++++++++++++
 2 files changed, 78 insertions(+), 0 deletions(-)
 create mode 100644 doc/device-tree-bindings/clock/tegra-periphclk

index a9a98ea..ec75747 100644
@@ -4,6 +4,33 @@
 	compatible = "nvidia,tegra20";
 	interrupt-parent = <&intc>;
 
+	clocks = <&osc_clk>;
+	clock-names = "osc_clk";
+	clock-ranges;
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* The frequency of this clock is board-specific */
+		osc_clk: oscclk {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+		};
+
+		/*
+		 * This node provides clocks to all peripherals. We don't
+		 * enumerate the clock names for now since there are no
+		 * users of this information.
+		 */
+		periph_clk: periphclk {
+			compatible = "tegra,periphclk";
+			#clock-cells = <1>;
+			clocks = <&osc_clk>;
+			reg = <0x60006000 400>;
+		};
+	};
+
 	intc: interrupt-controller@50041000 {
 		compatible = "nvidia,tegra20-gic";
 		interrupt-controller;

1.7.7.3

This adds clock references to the USB part of the device tree for U-Boot.

The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there.

---
Changes in v5:
- Add dr_mode property to control host/device/otg mode
- Add nvidia,has-legacy-mode property per review comments
- Change device tree comment style from // to /* */

 arch/arm/dts/tegra20.dtsi |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

index ec75747..b2e3a40 100644
@@ -176,6 +176,9 @@
 		reg = <0xc5000000 0x4000>;
 		interrupts = < 52 >;
 		phy_type = "utmi";
+		clocks = <&periph_clk 22>;	/* PERIPH_ID_USBD */
+		dr_mode = "otg";
+		nvidia,has-legacy-mode;
 	};
 
 	usb@c5004000 {

@@ -183,6 +186,8 @@
 		reg = <0xc5004000 0x4000>;
 		interrupts = < 53 >;
 		phy_type = "ulpi";
+		clocks = <&periph_clk 58>;	/* PERIPH_ID_USB2 */
+		dr_mode = "host";
 	};
 
 	usb@c5008000 {

@@ -190,6 +195,8 @@
 		reg = <0xc5008000 0x4000>;
 		interrupts = < 129 >;
 		phy_type = "utmi";
+		clocks = <&periph_clk 59>;	/* PERIPH_ID_USB3 */
+		dr_mode = "otg";
 	};
 
 };

1.7.7.3

The patch below does more than what's covered by this description...

nvpublic

Hi Stephen,

Done

OK. I was seeing it as an SOC capability rather than a board feature.

Done. In principle VBUS can be controlled by a bit in the peripheral controller driving out a VBUS enable line, but that's not how it works in this case.

Regards,
Simon

We set up two USB ports, one of which can be host or device. For some reason the kernel version does enable both ports.

---
Changes in v2:
- Remove 0x from fdt aliases
- Use "okay" instead of "ok" for fdt node status

Changes in v3:
- Disable USB2 which is not used on Seaboard
- Fix device tree indenting with tabs instead of spaces
- Remove "okay" from nodes since this is the default anyway

Changes in v5:
- Remove support-host-mode property

 board/nvidia/dts/tegra2-seaboard.dts |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

index dde5d03..f53690f 100644
@@ -11,6 +11,12 @@
 		bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait";
 	};
 
+	aliases {
+		/* This defines the order of our USB ports */
+		usb0 = "/usb@c5008000";
+		usb1 = "/usb@c5000000";
+	};
+
 	memory {
 		device_type = "memory";
 		reg = < 0x00000000 0x40000000 >;

@@ -33,4 +39,8 @@
 	usb@c5000000 {
 		nvidia,vbus-gpio = <&gpio 24 0>; /* PD0 */
 	};
+
+	usb@c5004000 {
+		status = "disabled";
+	};
 };

1.7.7.3

A common requirement is to find the clock ID for a peripheral. This is the second cell of the 'clocks' property (the first being the phandle itself).

---
Changes in v4:
- Add fdtdec function to return peripheral ID

 include/fdtdec.h |   13 +++++++++++++
 lib/fdtdec.c     |   13 +++++++++++++
 2 files changed, 26 insertions(+), 0 deletions(-)

index 6c0a2d1..f3115a6 100644
@@ -272,3 +272,16 @@ int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name,
  * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error
  */
 int fdtdec_setup_gpio(struct fdt_gpio_state *gpio);
+
+/**
+ * Decode a peripheral ID from a device tree node. This may be a temporary
+ * function depending on what happens with clocks in the Linux fdt.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob		FDT blob to use
+ * @param node		Node to look at
+ * @return
+ */
+int fdtdec_decode_periph_id(const void *blob, int node);

index c748cac..f999ed0 100644
@@ -415,3 +415,16 @@ int fdtdec_setup_gpio(struct fdt_gpio_state *gpio)
 		return -1;
 	return 0;
 }
+
+int fdtdec_decode_periph_id(const void *blob, int node)
+{
+	u32 cell[2];
+	int err;
+
+	err = fdtdec_get_int_array(blob, node, "clocks", cell,
+				   ARRAY_SIZE(cell));
+	if (err)
+		return -1;
+
+	return cell[1];
+}

1.7.7.3

This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present.

---
Changes in v3:
- Drop Tegra USB alignment patch as we will deal with this another way

 include/configs/seaboard.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

index b6d9f7a..1dc775a 100644
@@ -27,6 +27,11 @@
 #include <asm/sizes.h>
 #include "tegra2-common.h"
 
+/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE	tegra2-seaboard
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
 /* High-level configuration options */
 #define TEGRA2_SYSMEM		"mem=384M@0M nvmem=128M@384M mem=512M@512M"
 #define V_PROMPT		"Tegra2 (SeaBoard) # "

1.7.7.3

Aside from the issues I've just mentioned in my recent emails, and from needing to update to the clock binding we discussed on the Linux mailing lists, the whole series is:

nvpublic

Hi Stephen,

Thanks - it would be nice to get this in since it is the first actual use of fdt in U-Boot.

I will resend the two patches that need changing as v6.

Regards,
Simon

CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the txfilltuning field in the EHCI controller on reset.

---

 README                      |    3 +++
 drivers/usb/host/ehci-hcd.c |    7 +++++++
 drivers/usb/host/ehci.h     |    6 +++++-
 3 files changed, 15 insertions(+), 1 deletions(-)

index 9d713e8..7adf7c7 100644
@@ -1135,6 +1135,9 @@ The following options need to be configured:
 				May be defined to allow interrupt polling
 				instead of using asynchronous interrupts
 
+		CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
+		txfilltuning field in the EHCI controller on reset.
+
 - USB Device:
 		Define the below if you wish to use the USB console.
 		Once firmware is rebuilt from a serial console issue the

index 3f7bc2c..d893b2a 100644
@@ -259,6 +259,13 @@ static int ehci_reset(void)
 #endif
 		ehci_writel(reg_ptr, tmp);
 	}
+
+#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
+	cmd = ehci_readl(&hcor->or_txfilltuning);
+	cmd &= ~TXFIFO_THRESH(0x3f);
+	cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
+	ehci_writel(&hcor->or_txfilltuning, cmd);
+#endif
 out:
 	return ret;
 }

index 3d0ad0c..cc00ce4 100644
@@ -80,7 +80,11 @@ struct ehci_hcor {
 	uint32_t or_ctrldssegment;
 	uint32_t or_periodiclistbase;
 	uint32_t or_asynclistaddr;
-	uint32_t _reserved_[9];
+	uint32_t _reserved_0_;
+	uint32_t or_burstsize;
+	uint32_t or_txfilltuning;
+#define TXFIFO_THRESH(p)		((p & 0x3f) << 16)
+	uint32_t _reserved_1_[6];
 	uint32_t or_configflag;
 #define FLAG_CF		(1 << 0)	/* true:  we'll support "high speed" */
 	uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];

1.7.7.3

This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up.

Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment:

        aliases {
		/* This defines the order of our USB ports */
                usb0 = "/usb at 0xc5008000";
                usb1 = "/usb at 0xc5000000";
        };

drivers/usb/host files ONLY: Acked-by: Remy Bohmer <[email protected]>

---
Changes in v2:
- Decode USB VBUS GPIO from the fdt
- Decode phy type differently (to match new kernel fdt)
- Improve debug() printouts in case of failure to init USB
- Remove non-fdt operation of USB, since it is not needed
- Rename params to timing
- Rename tegra20-usb to tegra20-ehcui (to match new kernel fdt)
- Store entire fdt config in port list, not just register pointer

Changes in v3:
- Remove usbparams properties from fdt and moved them to C code

Changes in v4:
- Use peripheral clock node to obtain peripheral ID
- Use updated fdtdec alias functiona to get USB aliases

Changes in v5:
- Add additional debugging to report active USB ports
- Allow any port to operate in otg mode
- Correct PTS_MASK value to be unsigned
- Implement new device tree properties
- Remove checking of peripheral ID and try to use only device tree
- Report error if phy clock does not start up

 arch/arm/cpu/armv7/tegra2/Makefile        |    4 +-
 arch/arm/cpu/armv7/tegra2/usb.c           |  460 +++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/tegra2.h |    2 +
 arch/arm/include/asm/arch-tegra2/usb.h    |  252 ++++++++++++++++
 drivers/usb/host/Makefile                 |    1 +
 drivers/usb/host/ehci-tegra.c             |   62 ++++
 include/fdtdec.h                          |    1 +
 lib/fdtdec.c                              |    1 +
 8 files changed, 782 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h
 create mode 100644 drivers/usb/host/ehci-tegra.c

index f668a81..e9ac6c9 100644
@@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-y	:= ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
 
+COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 

index 8941443..baae2eb 100644
@@ -41,6 +41,8 @@
 #define TEGRA2_SPI_BASE		(NV_PA_APB_MISC_BASE + 0xC380)
 #define NV_PA_PMC_BASE		0x7000E400
 #define NV_PA_CSITE_BASE	0x70040000
+#define TEGRA_USB1_BASE		0xC5000000
+#define TEGRA_USB3_BASE		0xC5008000
 
 #define TEGRA2_SDRC_CS0		NV_PA_SDRAM_BASE
 #define LOW_LEVEL_SRAM_STACK	0x4000FFFC

index 77e217f..a11cebb 100644
@@ -47,6 +47,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
+COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 
 COBJS	:= $(COBJS-y)

index f3115a6..bd2222c 100644
@@ -57,6 +57,7 @@ struct fdt_memory {
  */
 enum fdt_compat_id {
 	COMPAT_UNKNOWN,
+	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra2 USB port */
 
 	COMPAT_COUNT,
 };

index f999ed0..7260c73 100644
@@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define COMPAT(id, name) name
 static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(UNKNOWN, "<none>"),
+	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)

1.7.7.3

This adds basic USB support for port 0. The other port is not supported yet.

Tegra2 (SeaBoard) # usb start
(Re)start USB...
USB: Register 10011 NbrPorts 1
USB EHCI 1.00
scanning bus for devices... 5 USB Device(s) found
scanning bus for storage devices... 1 Storage Device(s) found
Tegra2 (SeaBoard) # ext2load usb 0:3 10000000 /boot/vmlinuz Loading file "/boot/vmlinuz" from usb device 0:3 (ROOT-A) 2932976 bytes read

---
Changes in v2:
- Add setting of pinmux for USB VBUS GPIO

Changes in v5:
- Put pinmux setting into a board-specific function

 board/nvidia/common/board.c      |   12 ++++++++++++
 board/nvidia/common/board.h      |    6 ++++++
 board/nvidia/seaboard/seaboard.c |    6 ++++++
 3 files changed, 24 insertions(+), 0 deletions(-)

index e8253a0..72d8630 100644
@@ -33,6 +33,7 @@
 #include <asm/arch/pinmux.h>
 #include <asm/arch/uart.h>
 #include <spi.h>
+#include <asm/arch/usb.h>
 #include "board.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -50,6 +51,12 @@ int timer_init(void)
 	return 0;
 }
 
+void __pin_mux_usb(void)
+{
+}
+
+void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
+
 /*
  * Routine: board_init
  * Description: Early hardware init.

@@ -69,6 +76,11 @@ int board_init(void)
 	/* boot param addr */
 	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
 
+#ifdef CONFIG_USB_EHCI_TEGRA
+	pin_mux_usb();
+	board_usb_init(gd->fdt_blob);
+#endif
+
 	return 0;
 }
 

index a638af2..09fb158 100644
@@ -27,4 +27,10 @@
 void gpio_config_uart(void);
 void gpio_early_init_uart(void);
 
+/*
+ * Set up any pin muxing needed for USB (for now, since fdt doesn't support
+ * it). Boards can overwrite the default fucction which does nothing.
+ */
+void pin_mux_usb(void);
+
 #endif	/* BOARD_H */

index 9ab6825..94efb1e 100644
@@ -90,3 +90,9 @@ int board_mmc_init(bd_t *bd)
 	return 0;
 }
 #endif
+
+void pin_mux_usb(void)
+{
+	/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
+	pinmux_tristate_disable(PINGRP_SLXK);
+}

1.7.7.3

All Tegra2 boards should include tegra2-common. This adds the required USB config to that file.

---
Changes in v5:
- Add CONFIG_EHCI_DCACHE which is needed for dcache operation
- Drop unused CONFIG_USB_EHCI_DATA_ALIGN option

 include/configs/tegra2-common.h |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

index e6f385f..266d0e5 100644
@@ -84,6 +84,16 @@
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
 
+/*
+ * This parameter affects a TXFILLTUNING field that controls how much data is
+ * sent to the latency fifo before it is sent to the wire. Without this
+ * parameter, the default (2) causes occasional Data Buffer Errors in OUT
+ * packets depending on the buffer address and size.
+ */
+#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_EHCI_DCACHE
+
 /* include default commands */
 #include <config_cmd_default.h>
 

1.7.7.3

Seaboard has a top port which is USB host or device, and a side port which is host only.

---
Changes in v2:
- Remove unneeded CONFIG_TEGRA_USBx defines

 include/configs/seaboard.h |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

index 261f952..b6d9f7a 100644
@@ -72,4 +72,11 @@
 
 #define CONFIG_ENV_SECT_SIZE    CONFIG_ENV_SIZE
 #define CONFIG_ENV_OFFSET       (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
 #endif /* __CONFIG_H */

1.7.7.3

Hi,

what's the status of this patch/patchset?

Thanks
M

Hi Marek,

Superceded, v6 is on its way in the next few days.

Regards,
Simon

Hi,

I am about to send v6. Due to the way things are organized, 6 of that patches have changed. I have also dropped the fdt alignment one. So I think it is safest to resend the whole 20-patch series again.

Regards,
Simon

Please wait until wednesday with the submission until we sort out the usb maintainership and until the most significant USB changes find their way into mainline uboot.

Thanks in advance
M

Marek/Simon,

For those that don't want to wait, I've applied this patch series to u-boot-tegra/test and pushed to denx.

Simon - seems to work fine - USB->NET dongle, USB mouse, and USB stick all detected OK, both directly and behind the hub on the USB->NET dongle (Asix 3-port hub w/Ethernet adapter).

I'll wait a couple of days for the reviews & USB issues to sort themselves out before doing a pull request to Albert for ARM, but I want to get this in so I can move forward with the other Tegra2 drivers (I2C, LCD, kbd, etc.) that depend on fdt/DT.

Tom

nvpublic

Hi Tom,

OK thanks, good. Hoping that Puneet's alignment fixes can go in soon also.

I will have to do an update to i2c sorry, due to Stephen's clock binding changes. Yes I know it is acked and ready, but it will not work now. Wil try to do that today. After that is warmboot - have you taken a look at that?

Regards,
Simon