tegra: Add display driver and LCD support for Seaboard

arch/arm/cpu/armv7/tegra2/funcmux.c line 34

Quoted 4 lines · On Saturday 14 January 2012 19:47:16 Simon Glass wrote:

arch/arm/cpu/armv7/tegra2/funcmux.c +1 -0

 
+struct pingroup_config disp1_default[] = {

const ? although it looks like we need to fix pinmux_config_table() first
...
-mike

Add support for adjusting the cachability of an L1 section by updating the MMU. The mmu_set_region_dcache() function allows drivers to make these changes after the MMU is set up.

It is implemented only for ARMv7 at present.

This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back.

Signed-off-by Simon Glass<[email protected]>

---
  arch/arm/cpu/armv7/cache_v7.c |   11 +++++++
  arch/arm/include/asm/system.h |   30 ++++++++++++++++++++
  arch/arm/lib/cache-cp15.c     |   62 +++++++++++++++++++++++++++++++++-------
  3 files changed, 92 insertions(+), 11 deletions(-)

arch/arm/cpu/armv7/cache_v7.c +0 -0

index 1b4e808..5f6d039 100644

arch/arm/cpu/armv7/cache_v7.c +7 -0

+}
+
  /*
   * Flush range from all levels of d-cache/unified-cache used:
   * Affects the range [start, start + size - 1]

@@ -329,6 +335,11 @@ void arm_init_before_mmu(void)
  void  flush_cache(unsigned long start, unsigned long size)
  {
  }
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+
  #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
 
  #ifndef CONFIG_SYS_ICACHE_OFF

arch/arm/include/asm/system.h +30 -0

index 2b28a26..f52a4fc 100644
@@ -75,6 +75,36 @@ static inline void set_cr(unsigned int val)
  	isb();
  }
 
+/* options available for data cache on each page */
+enum dcache_option {
+	DCACHE_OFF,
+	DCACHE_WRITETHROUGH,
+	DCACHE_WRITEBACK,
+};
+
+/* Size of an MMU section */
+enum {
+	MMU_SECTION_SHIFT	= 20,
+	MMU_SECTION_SIZE	= 1<<  MMU_SECTION_SHIFT,
+};
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start		start address of memory region to change
+ * \param size		size of memory region to change
+ * \param option	dcache option to select
+ */
+void mmu_set_region_dcache(u32 start, int size, enum dcache_option option);
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start		start address of update in page table
+ * \param stop		stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
  #endif /* __ASSEMBLY__ */
 
  #define arch_align_stack(x) (x)

arch/arm/lib/cache-cp15.c +49 -8

index e6c3eae..facb1a7 100644
@@ -26,12 +26,6 @@
 
  #if !(defined(CONFIG_SYS_ICACHE_OFF)&&  defined(CONFIG_SYS_DCACHE_OFF))
 
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define CACHE_SETUP	0x1a
-#else
-#define CACHE_SETUP	0x1e
-#endif
-
  DECLARE_GLOBAL_DATA_PTR;
 
  void __arm_init_before_mmu(void)

@@ -50,9 +44,52 @@ static void cp_delay (void)
  	asm volatile("" : : : "memory");
  }
 
-static inline void dram_bank_mmu_setup(int bank)
+void set_section_dcache(int section, enum dcache_option option)
  {
+	u32 value = section<<  MMU_SECTION_SHIFT | (3<<  10);
  	u32 *page_table = (u32 *)gd->tlb_addr;
+
+	switch (option) {
+	case DCACHE_WRITETHROUGH:
+		value |= 0x1a;
+		break;
+
+	case DCACHE_WRITEBACK:
+		value |= 0x1e;
+		break;
+
+	case DCACHE_OFF:
+		value |= 0x12;
+		break;
+	}
+
+	page_table[section] = value;
+}
+
+void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+	debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+	__attribute__((weak, alias("__mmu_page_table_flush")));
+
+void mmu_set_region_dcache(u32 start, int size, enum dcache_option option)
+{
+	u32 *page_table = (u32 *)gd->tlb_addr;
+	u32 upto, end;
+
+	end = ALIGN(start + size, MMU_SECTION_SIZE)>>  MMU_SECTION_SHIFT;
+	start = start>>  MMU_SECTION_SHIFT;
+	debug("mmu_set_region_dcache start=%x, size=%x, option=%d\n",
+	      start, size, option);
+	for (upto = start; upto<  end; upto++)
+		set_section_dcache(upto, option);
+	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+}
+
+static inline void dram_bank_mmu_setup(int bank)
+{
  	bd_t *bd = gd->bd;
  	int	i;
 

@@ -60,21 +97,24 @@ static inline void dram_bank_mmu_setup(int bank)
  	for (i = bd->bi_dram[bank].start>>  20;
  	     i<  (bd->bi_dram[bank].start + bd->bi_dram[bank].size)>>  20;
  	     i++) {
-		page_table[i] = i<<  20 | (3<<  10) | CACHE_SETUP;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+		set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+		set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
  	}
  }
 
  /* to activate the MMU we need to set up virtual memory: use 1M areas */

Hi Simon,

Le 15/01/2012 01:47, Simon Glass a ?crit :

Quoted 25 lines

Add support for adjusting the cachability of an L1 section by updating the MMU. The mmu_set_region_dcache() function allows drivers to make these changes after the MMU is set up.

It is implemented only for ARMv7 at present.

This is needed for LCD support, where we want to make the LCD frame buffer write-through (or off) rather than write-back.

Signed-off-by Simon Glass<[email protected]>

---

?arch/arm/cpu/armv7/cache_v7.c | ? 11 +++++++
?arch/arm/include/asm/system.h | ? 30 ++++++++++++++++++++
?arch/arm/lib/cache-cp15.c ? ? | ? 62

+++++++++++++++++++++++++++++++++-------
?3 files changed, 92 insertions(+), 11 deletions(-)

arch/arm/cpu/armv7/cache_v7.c +0 -0

index 1b4e808..5f6d039 100644
@@ -297,6 +297,12 @@ void arm_init_before_mmu(void)
 ? ? ? ?v7_inval_tlb();
 ?}
 

arch/arm/cpu/armv7/cache_v7.c void arm_init_before_mmu(void)

Quoted 4 lines

arch/arm/cpu/armv7/cache_v7.c +4 -0

+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+ ? ? ? flush_dcache_range(start, stop);
+ ? ? ? v7_inval_tlb();

If that means "invalidate", then spell it out.

Quoted 154 lines

arch/arm/cpu/armv7/cache_v7.c +2 -0

+}
+

?/*
? * Flush range from all levels of d-cache/unified-cache used:
? * Affects the range [start, start + size - 1]

arch/arm/cpu/armv7/cache_v7.c +5 -0

@@ -329,6 +335,11 @@ void arm_init_before_mmu(void)
 ?void ?flush_cache(unsigned long start, unsigned long size)
 ?{
 ?}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+}
+

?#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */

?#ifndef CONFIG_SYS_ICACHE_OFF

arch/arm/include/asm/system.h +30 -0

index 2b28a26..f52a4fc 100644
@@ -75,6 +75,36 @@ static inline void set_cr(unsigned int val)
 ? ? ? ?isb();
 ?}
 
+/* options available for data cache on each page */
+enum dcache_option {
+ ? ? ? DCACHE_OFF,
+ ? ? ? DCACHE_WRITETHROUGH,
+ ? ? ? DCACHE_WRITEBACK,
+};
+
+/* Size of an MMU section */
+enum {
+ ? ? ? MMU_SECTION_SHIFT ? ? ? = 20,
+ ? ? ? MMU_SECTION_SIZE ? ? ? ?= 1<< ?MMU_SECTION_SHIFT,
+};
+
+/**
+ * Change the cache settings for a region.
+ *
+ * \param start ? ? ? ? ? ? ? ?start address of memory region to change
+ * \param size ? ? ? ? size of memory region to change
+ * \param option ? ? ? dcache option to select
+ */
+void mmu_set_region_dcache(u32 start, int size, enum dcache_option
 option);
+
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start ? ? ? ? ? ? ? ?start address of update in page table
+ * \param stop ? ? ? ? stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+

?#endif /* __ASSEMBLY__ */

?#define arch_align_stack(x) (x)

arch/arm/lib/cache-cp15.c +0 -6

index e6c3eae..facb1a7 100644
@@ -26,12 +26,6 @@
 
 ?#if !(defined(CONFIG_SYS_ICACHE_OFF)&& ?defined(CONFIG_SYS_DCACHE_OFF))
 
 
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-#define CACHE_SETUP ? ?0x1a
-#else
-#define CACHE_SETUP ? ?0x1e
-#endif
-
 ?DECLARE_GLOBAL_DATA_PTR;
 

?void __arm_init_before_mmu(void)

arch/arm/lib/cache-cp15.c +44 -1

@@ -50,9 +44,52 @@ static void cp_delay (void)
 ? ? ? ?asm volatile("" : : : "memory");
 ?}
 
-static inline void dram_bank_mmu_setup(int bank)
+void set_section_dcache(int section, enum dcache_option option)
 ?{
+ ? ? ? u32 value = section<< ?MMU_SECTION_SHIFT | (3<< ?10);
 ? ? ? ?u32 *page_table = (u32 *)gd->tlb_addr;
+
+ ? ? ? switch (option) {
+ ? ? ? case DCACHE_WRITETHROUGH:
+ ? ? ? ? ? ? ? value |= 0x1a;
+ ? ? ? ? ? ? ? break;
+
+ ? ? ? case DCACHE_WRITEBACK:
+ ? ? ? ? ? ? ? value |= 0x1e;
+ ? ? ? ? ? ? ? break;
+
+ ? ? ? case DCACHE_OFF:
+ ? ? ? ? ? ? ? value |= 0x12;
+ ? ? ? ? ? ? ? break;
+ ? ? ? }
+
+ ? ? ? page_table[section] = value;
+}
+
+void __mmu_page_table_flush(unsigned long start, unsigned long stop)
+{
+ ? ? ? debug("%s: Warning: not implemented\n", __func__);
+}
+
+void mmu_page_table_flush(unsigned long start, unsigned long stop)
+ ? ? ? __attribute__((weak, alias("__mmu_page_table_flush")));
+
+void mmu_set_region_dcache(u32 start, int size, enum dcache_option
 option)
+{
+ ? ? ? u32 *page_table = (u32 *)gd->tlb_addr;
+ ? ? ? u32 upto, end;
+
+ ? ? ? end = ALIGN(start + size, MMU_SECTION_SIZE)>> ?MMU_SECTION_SHIFT;
+ ? ? ? start = start>> ?MMU_SECTION_SHIFT;
+ ? ? ? debug("mmu_set_region_dcache start=%x, size=%x, option=%d\n",
+ ? ? ? ? ? ? start, size, option);
+ ? ? ? for (upto = start; upto< ?end; upto++)
+ ? ? ? ? ? ? ? set_section_dcache(upto, option);
+ ? ? ? mmu_page_table_flush((u32)&page_table[start],
 (u32)&page_table[end]);
+}
+
+static inline void dram_bank_mmu_setup(int bank)
+{
 ? ? ? ?bd_t *bd = gd->bd;

? ? ? ?int ? ? i;

arch/arm/lib/cache-cp15.c +5 -1

@@ -60,21 +97,24 @@ static inline void dram_bank_mmu_setup(int bank)
 ? ? ? ?for (i = bd->bi_dram[bank].start>> ?20;
 ? ? ? ? ? ? i< ?(bd->bi_dram[bank].start + bd->bi_dram[bank].size)>> ?20;
 ? ? ? ? ? ? i++) {
- ? ? ? ? ? ? ? page_table[i] = i<< ?20 | (3<< ?10) | CACHE_SETUP;
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
+ ? ? ? ? ? ? ? set_section_dcache(i, DCACHE_WRITETHROUGH);
+#else
+ ? ? ? ? ? ? ? set_section_dcache(i, DCACHE_WRITEBACK);
+#endif
 ? ? ? ?}
 ?}
 

?/* to activate the MMU we need to set up virtual memory: use 1M areas */ ?static inline void mmu_setup(void)
?{
- ? ? ? u32 *page_table = (u32 *)gd->tlb_addr;
? ? ? ?int i;
? ? ? ?u32 reg;

Quoted 4 lines

? ? ? ?arm_init_before_mmu();
? ? ? ?/* Set up an identity-mapping for all 4GB, rw for everyone */ ? ? ? ?for (i = 0; i< ?4096; i++)
- ? ? ? ? ? ? ? page_table[i] = i<< ?20 | (3<< ?10) | 0x12;

Maybe give names to some of the magic numbers here (and in other places where they appear).

Quoted 8 lines

+ ? ? ? ? ? ? ? set_section_dcache(i, DCACHE_OFF);

? ? ? ?for (i = 0; i< ?CONFIG_NR_DRAM_BANKS; i++) { ? ? ? ? ? ? ? ?dram_bank_mmu_setup(i);

arch/arm/lib/cache-cp15.c +0 -0

@@ -82,7 +122,7 @@ static inline void mmu_setup(void)
 

Quoted 7 lines

? ? ? ?/* Copy the page table address to cp15 */ ? ? ? ?asm volatile("mcr p15, 0, %0, c2, c0, 0"
- ? ? ? ? ? ? ? ? ? ?: : "r" (page_table) : "memory");
+ ? ? ? ? ? ? ? ? ? ?: : "r" (gd->tlb_addr) : "memory"); ? ? ? ?/* Set the access control to all-supervisor */ ? ? ? ?asm volatile("mcr p15, 0, %0, c3, c0, 0" ? ? ? ? ? ? ? ? ? ? : : "r" (~0));

Amicalement,
--
Albert.

We want to make the display section-aligned on ARM so that we can easily turn off data caching for this.

Is this useful for other architectures? We could perhaps generalise it by adding the ability to specify the alignment size, but at least for ARM it is easier to have it be an architecture feature set by the MMU's system.h header.

Quoted 7 lines · On Saturday 14 January 2012 19:47:23 Simon Glass wrote:

We want to make the display section-aligned on ARM so that we can easily turn off data caching for this.

Is this useful for other architectures? We could perhaps generalise it by adding the ability to specify the alignment size, but at least for ARM it is easier to have it be an architecture feature set by the MMU's system.h header.

seems like a generally useful thing, but the exact alignment is a bit hackish.
so perhaps the CONFIG knob should instead be the size you want to align things
to ?

-mike

Quoted 11 lines · On Saturday 14 January 2012 19:47:24 Simon Glass wrote:

common/cmd_echo.c +2 -1

@@ -44,8 +44,9 @@ int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char *
 const argv[]) }
 ? ? ? }
 
+ ? ? /* Use puts() so that the LCD sees it as a new line */
 ? ? ? if (putnl)
- ? ? ? ? ? ? putc('\n');
+ ? ? ? ? ? ? puts("\n");
 

common/cmd_echo.c int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * · line 52

Quoted 2 lines

common/cmd_echo.c +0 -0

 ? ? ? return 0;
 ?}

this sounds like a hack for a broken LCD core and so the fix should be somewhere in there

common/lcd.c

Quoted 5 lines

common/lcd.c +1 -0

 
+static char lcd_flush_dcache;

seems like it'd be better as a CONFIG knob

Quoted 6 lines

+ ? ? /*
+ ? ? ?* flush_dcache_range() is declared in common.h but it seems that some
+ ? ? ?* architectures do not actually implement it. Is there a way to find
+ ? ? ?* out whether it exists? For now, ARM is safe.
+ ? ? ?*/

if those arches don't implement this func, then the failure is on their head. people should feel free to use the cache api we expose in common.h.

-mike

Quoted 12 lines · Mike Frysinger

Quoted 11 lines · On Saturday 14 January 2012 19:47:24 Simon Glass wrote:

common/cmd_echo.c +2 -1

@@ -44,8 +44,9 @@ int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char
 * const argv[]) }
      }
 
+     /* Use puts() so that the LCD sees it as a new line */
      if (putnl)
-             putc('\n');
+             puts("\n");
 

Quoted 5 lines

common/cmd_echo.c int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) · line 52

Quoted 2 lines

common/cmd_echo.c +0 -0

      return 0;
 }

this sounds like a hack for a broken LCD core and so the fix should be somewhere in there

Well it's actually that I don't want to flush after every character (it slows things down a lot)

so puts is a good place to look

I suppose we could flush after every newline we see in lcd_putc().

Quoted 5 lines · On Saturday 14 January 2012 20:57:25 Simon Glass wrote:

Quoted 4 lines · Mike Frysinger

common/cmd_echo.c int do_echo(cmd_tbl_t *cmdtp, int flag, int argc,

Quoted 3 lines · On Saturday 14 January 2012 19:47:24 Simon Glass wrote:

common/cmd_echo.c +0 -0

@@ -44,8 +44,9 @@ int do_echo(cmd_tbl_t *cmdtp, int flag, int argc,

char

Quoted 8 lines

Quoted 8 lines

Quoted 8 lines

common/cmd_echo.c +2 -1

 * const argv[]) }
      }
 
+     /* Use puts() so that the LCD sees it as a new line */
      if (putnl)
-             putc('\n');
+             puts("\n");
 

Quoted 8 lines

Quoted 5 lines

common/cmd_echo.c int do_echo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) · line 52

Quoted 2 lines

common/cmd_echo.c +0 -0

      return 0;
 }

this sounds like a hack for a broken LCD core and so the fix should be somewhere in there

Well it's actually that I don't want to flush after every character (it slows things down a lot)

right, but ...

Quoted 1 line

so puts is a good place to look

most puts() that i've seen are simple loops that call putc()

Quoted 1 line

I suppose we could flush after every newline we see in lcd_putc().

that would be the right way to go i think

-mike

This series adds support for the Tegra2x's display peripheral. This supports the LCD display on Seaboard and we use this to enable console output in U-Boot on the LCD.

Configuration is via the device tree. Proposed bindings are included in this series.

To improve performance two optimisations are offered:

1. The LCD frame buffer is cached, with the cache being flushed after each call puts(). This dramatically increases performance (around 10x). This requires a few additions to the ARM cache support.

2. The console supports scrolling in steps of more than 1 line. This speeds up scrolling output considerably, particularly commands like 'printenv' which display a lot of output. This requires a new CONFIG and a change to the console_scrollup() function.

Mayuresh Kulkarni (1):
tegra: Enable display/lcd support on Seaboard

Simon Glass (15):
fdt: Add function to look up a phandle's register address
fdt: Add header guard to fdtdec.h
fdt: Correct GPIO name access in fdtdec
tegra: Add display support to funcmux
tegra: fdt: Add LCD definitions for Tegra
tegra: Add support for PWFM
tegra: Add LCD driver
tegra: Add LCD support to Nvidia boards
arm: Add control over cachability of memory regions
lcd: Add CONFIG_ALIGN_LCD_TO_SECTION to align lcd for MMU
lcd: Add support for flushing LCD fb from dcache after update
tegra: Align LCD frame buffer to section boundary
tegra: Support control of cache settings for LCD
tegra: fdt: Add LCD definitions for Seaboard
lcd: Add CONSOLE_SCROLL_LINES option to speed console

Wei Ni (1):
tegra: Add SOC support for display/lcd

  README                                          |   16 +
  arch/arm/cpu/armv7/cache_v7.c                   |   11 +
  arch/arm/cpu/armv7/tegra2/Makefile              |    1 +
  arch/arm/cpu/armv7/tegra2/display.c             |  271 +++++++++++
  arch/arm/cpu/armv7/tegra2/funcmux.c             |   39 ++
  arch/arm/cpu/armv7/tegra2/pwfm.c                |   40 ++
  arch/arm/dts/tegra20.dtsi                       |   25 +
  arch/arm/include/asm/arch-tegra2/dc.h           |  544 +++++++++++++++++++++++
  arch/arm/include/asm/arch-tegra2/display.h      |  133 ++++++
  arch/arm/include/asm/arch-tegra2/pwfm.h         |   54 +++
  arch/arm/include/asm/system.h                   |   30 ++
  arch/arm/lib/cache-cp15.c                       |   62 +++-
  board/nvidia/common/board.c                     |   21 +-
  board/nvidia/dts/tegra2-seaboard.dts            |   21 +
  common/cmd_echo.c                               |    3 +-
  common/lcd.c                                    |   85 +++-
  doc/device-tree-bindings/video/nvidia-video.txt |   92 ++++
  drivers/video/Makefile                          |    1 +
  drivers/video/tegra.c                           |  388 ++++++++++++++++
  include/configs/seaboard.h                      |   12 +-
  include/configs/tegra2-common.h                 |    1 +
  include/fdtdec.h                                |   17 +
  include/lcd.h                                   |   11 +
  lib/fdtdec.c                                    |   15 +-
  24 files changed, 1862 insertions(+), 31 deletions(-)

create mode 100644 arch/arm/cpu/armv7/tegra2/display.c create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h create mode 100644 arch/arm/include/asm/arch-tegra2/display.h create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt create mode 100644 drivers/video/tegra.c

Quoted 69 lines · Simon Glass

This series adds support for the Tegra2x's display peripheral. This supports the LCD display on Seaboard and we use this to enable console output in U-Boot on the LCD.

Configuration is via the device tree. Proposed bindings are included in this series.

To improve performance two optimisations are offered:

1. The LCD frame buffer is cached, with the cache being flushed after each call puts(). This dramatically increases performance (around 10x). This requires a few additions to the ARM cache support.

2. The console supports scrolling in steps of more than 1 line. This speeds up scrolling output considerably, particularly commands like 'printenv' which display a lot of output. This requires a new CONFIG and a change to the console_scrollup() function.

Mayuresh Kulkarni (1):
tegra: Enable display/lcd support on Seaboard

Simon Glass (15):
fdt: Add function to look up a phandle's register address
fdt: Add header guard to fdtdec.h
fdt: Correct GPIO name access in fdtdec
tegra: Add display support to funcmux
tegra: fdt: Add LCD definitions for Tegra
tegra: Add support for PWFM
tegra: Add LCD driver
tegra: Add LCD support to Nvidia boards
arm: Add control over cachability of memory regions
lcd: Add CONFIG_ALIGN_LCD_TO_SECTION to align lcd for MMU
lcd: Add support for flushing LCD fb from dcache after update
tegra: Align LCD frame buffer to section boundary
tegra: Support control of cache settings for LCD
tegra: fdt: Add LCD definitions for Seaboard
lcd: Add CONSOLE_SCROLL_LINES option to speed console

Wei Ni (1):
tegra: Add SOC support for display/lcd

  README                                          |   16 +
  arch/arm/cpu/armv7/cache_v7.c                   |   11 +
  arch/arm/cpu/armv7/tegra2/Makefile              |    1 +
  arch/arm/cpu/armv7/tegra2/display.c             |  271 +++++++++++
  arch/arm/cpu/armv7/tegra2/funcmux.c             |   39 ++
  arch/arm/cpu/armv7/tegra2/pwfm.c                |   40 ++
  arch/arm/dts/tegra20.dtsi                       |   25 +
  arch/arm/include/asm/arch-tegra2/dc.h           |  544
+++++++++++++++++++++++
  arch/arm/include/asm/arch-tegra2/display.h      |  133 ++++++
  arch/arm/include/asm/arch-tegra2/pwfm.h         |   54 +++
  arch/arm/include/asm/system.h                   |   30 ++
  arch/arm/lib/cache-cp15.c                       |   62 +++-
  board/nvidia/common/board.c                     |   21 +-
  board/nvidia/dts/tegra2-seaboard.dts            |   21 +
  common/cmd_echo.c                               |    3 +-
  common/lcd.c                                    |   85 +++-
  doc/device-tree-bindings/video/nvidia-video.txt |   92 ++++
  drivers/video/Makefile                          |    1 +
  drivers/video/tegra.c                           |  388 ++++++++++++++++
  include/configs/seaboard.h                      |   12 +-
  include/configs/tegra2-common.h                 |    1 +
  include/fdtdec.h                                |   17 +
  include/lcd.h                                   |   11 +
  lib/fdtdec.c                                    |   15 +-
  24 files changed, 1862 insertions(+), 31 deletions(-)

Quoted 8 lines

create mode 100644 arch/arm/cpu/armv7/tegra2/display.c create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h create mode 100644 arch/arm/include/asm/arch-tegra2/display.h create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt create mode 100644 drivers/video/tegra.c

Hi Simon,

I have added your patch sources manually into the "Prepare v2012.04-rc1 release", because I got errors at apply. Also I added a device tree source file for Harmony.

I tested the device tree source file for Harmony and your patch sources on our Harmony hardware and generated a new patch file:

http://poeggi.dotsec.net/nvidia/uboot-lvds-init-patch/0001-Add-display-driver-and-LCD-support-for-Harmony-board.patch

I hope it's all okay, this my first patch release.

In the display.c source file I implemented a bug fix, because I get garbled images on the LCD without this fix.

Greetings
Christian

Changes:

- Add device tree source file for Harmony board
- Add bug fix in display.c
- Patch based on the "Prepare v2012.04-rc1" release

---
 README                                          |    7 +

 arch/arm/cpu/armv7/cache_v7.c                   |   11 +
 arch/arm/cpu/armv7/tegra2/Makefile              |    1 +
 arch/arm/cpu/armv7/tegra2/display.c             |  282 ++++++++++++
 arch/arm/cpu/armv7/tegra2/funcmux.c             |   41 ++
 arch/arm/cpu/armv7/tegra2/pwfm.c                |   45 ++
 arch/arm/dts/tegra20.dtsi                       |   26 ++

 arch/arm/include/asm/arch-tegra2/dc.h           |  544
+++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/display.h      |  133 ++++++
 arch/arm/include/asm/arch-tegra2/pwfm.h         |   54 +++
 arch/arm/include/asm/system.h                   |   30 ++
 arch/arm/lib/cache-cp15.c                       |   61 +++-
 board/nvidia/common/board.c                     |   20 +
 board/nvidia/dts/tegra2-harmony.dts             |   97 ++++
 board/nvidia/dts/tegra2-seaboard.dts            |   21 +
 common/cmd_echo.c                               |    2 +-
 common/lcd.c                                    |   86 +++-

 doc/device-tree-bindings/video/nvidia-video.txt |   92 ++++
 drivers/video/Makefile                          |    1 +
 drivers/video/tegra.c                           |  397 +++++++++++++++++
 dts/Makefile                                    |    2 +-
 include/configs/harmony.h                       |   39 ++-
 include/configs/tegra2-common.h                 |  218 +++++++++-
 include/fdtdec.h                                |   19 +-
 include/lcd.h                                   |   12 +
 lib/fdtdec.c                                    |   12 +
 26 files changed, 2206 insertions(+), 47 deletions(-)

 create mode 100644 arch/arm/cpu/armv7/tegra2/display.c
 create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/display.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h
 create mode 100644 board/nvidia/dts/tegra2-harmony.dts

 create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt
 create mode 100644 drivers/video/tegra.c

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Hi Christian,

Quoted 88 lines · Christian Kroehnert

Quoted 69 lines · Simon Glass

This series adds support for the Tegra2x's display peripheral. This supports the LCD display on Seaboard and we use this to enable console output in U-Boot on the LCD.

Configuration is via the device tree. Proposed bindings are included in this series.

To improve performance two optimisations are offered:

1. The LCD frame buffer is cached, with the cache being flushed after each call puts(). This dramatically increases performance (around 10x). This requires a few additions to the ARM cache support.

2. The console supports scrolling in steps of more than 1 line. This speeds up scrolling output considerably, particularly commands like 'printenv' which display a lot of output. This requires a new CONFIG and a change to the console_scrollup() function.

Mayuresh Kulkarni (1):
tegra: Enable display/lcd support on Seaboard

Simon Glass (15):
fdt: Add function to look up a phandle's register address
fdt: Add header guard to fdtdec.h
fdt: Correct GPIO name access in fdtdec
tegra: Add display support to funcmux
tegra: fdt: Add LCD definitions for Tegra
tegra: Add support for PWFM
tegra: Add LCD driver
tegra: Add LCD support to Nvidia boards
arm: Add control over cachability of memory regions
lcd: Add CONFIG_ALIGN_LCD_TO_SECTION to align lcd for MMU
lcd: Add support for flushing LCD fb from dcache after update
tegra: Align LCD frame buffer to section boundary
tegra: Support control of cache settings for LCD
tegra: fdt: Add LCD definitions for Seaboard
lcd: Add CONSOLE_SCROLL_LINES option to speed console

Wei Ni (1):
tegra: Add SOC support for display/lcd

  README                                          |   16 +
  arch/arm/cpu/armv7/cache_v7.c                   |   11 +
  arch/arm/cpu/armv7/tegra2/Makefile              |    1 +
  arch/arm/cpu/armv7/tegra2/display.c             |  271 +++++++++++
  arch/arm/cpu/armv7/tegra2/funcmux.c             |   39 ++
  arch/arm/cpu/armv7/tegra2/pwfm.c                |   40 ++
  arch/arm/dts/tegra20.dtsi                       |   25 +
  arch/arm/include/asm/arch-tegra2/dc.h           |  544
+++++++++++++++++++++++
  arch/arm/include/asm/arch-tegra2/display.h      |  133 ++++++
  arch/arm/include/asm/arch-tegra2/pwfm.h         |   54 +++
  arch/arm/include/asm/system.h                   |   30 ++
  arch/arm/lib/cache-cp15.c                       |   62 +++-
  board/nvidia/common/board.c                     |   21 +-
  board/nvidia/dts/tegra2-seaboard.dts            |   21 +
  common/cmd_echo.c                               |    3 +-
  common/lcd.c                                    |   85 +++-
  doc/device-tree-bindings/video/nvidia-video.txt |   92 ++++
  drivers/video/Makefile                          |    1 +
  drivers/video/tegra.c                           |  388 ++++++++++++++++
  include/configs/seaboard.h                      |   12 +-
  include/configs/tegra2-common.h                 |    1 +
  include/fdtdec.h                                |   17 +
  include/lcd.h                                   |   11 +
  lib/fdtdec.c                                    |   15 +-
  24 files changed, 1862 insertions(+), 31 deletions(-)

Quoted 8 lines

create mode 100644 arch/arm/cpu/armv7/tegra2/display.c create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h create mode 100644 arch/arm/include/asm/arch-tegra2/display.h create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt create mode 100644 drivers/video/tegra.c

Hi Simon,

I have added your patch sources manually into the "Prepare v2012.04-rc1 release", because I got errors at apply. Also I added a device tree source file for Harmony.

I tested the device tree source file for Harmony and your patch sources on our Harmony hardware and generated a new patch file:

Quoted 6 lines

http://poeggi.dotsec.net/nvidia/uboot-lvds-init-patch/0001-Add-display-driver-and-LCD-support-for-Harmony-board.patch

I hope it's all okay, this my first patch release.

In the display.c source file I implemented a bug fix, because I get garbled images on the LCD without this fix.

I see this code:

	u32 m_value;

	m_value = readl(0x54202e04);
	m_value &= ~0x2;
	writel(m_value, 0x54202e04);

What register are you actually writing here? I can't find it in my manual, but maybe I just haven't seen that address.

Quoted 101 lines · Simon Glass

Hi Christian,

Quoted 88 lines · Christian Kroehnert

Quoted 69 lines · Simon Glass

This series adds support for the Tegra2x's display peripheral. This supports the LCD display on Seaboard and we use this to enable console output in U-Boot on the LCD.

Configuration is via the device tree. Proposed bindings are included in this series.

To improve performance two optimisations are offered:

1. The LCD frame buffer is cached, with the cache being flushed after each call puts(). This dramatically increases performance (around 10x). This requires a few additions to the ARM cache support.

2. The console supports scrolling in steps of more than 1 line. This speeds up scrolling output considerably, particularly commands like 'printenv' which display a lot of output. This requires a new CONFIG and a change to the console_scrollup() function.

Mayuresh Kulkarni (1):
tegra: Enable display/lcd support on Seaboard

Simon Glass (15):
fdt: Add function to look up a phandle's register address
fdt: Add header guard to fdtdec.h
fdt: Correct GPIO name access in fdtdec
tegra: Add display support to funcmux
tegra: fdt: Add LCD definitions for Tegra
tegra: Add support for PWFM
tegra: Add LCD driver
tegra: Add LCD support to Nvidia boards
arm: Add control over cachability of memory regions
lcd: Add CONFIG_ALIGN_LCD_TO_SECTION to align lcd for MMU
lcd: Add support for flushing LCD fb from dcache after update
tegra: Align LCD frame buffer to section boundary
tegra: Support control of cache settings for LCD
tegra: fdt: Add LCD definitions for Seaboard
lcd: Add CONSOLE_SCROLL_LINES option to speed console

Wei Ni (1):
tegra: Add SOC support for display/lcd

  README                                          |   16 +
  arch/arm/cpu/armv7/cache_v7.c                   |   11 +
  arch/arm/cpu/armv7/tegra2/Makefile              |    1 +
  arch/arm/cpu/armv7/tegra2/display.c             |  271 +++++++++++
  arch/arm/cpu/armv7/tegra2/funcmux.c             |   39 ++
  arch/arm/cpu/armv7/tegra2/pwfm.c                |   40 ++
  arch/arm/dts/tegra20.dtsi                       |   25 +
  arch/arm/include/asm/arch-tegra2/dc.h           |  544
+++++++++++++++++++++++
  arch/arm/include/asm/arch-tegra2/display.h      |  133 ++++++
  arch/arm/include/asm/arch-tegra2/pwfm.h         |   54 +++
  arch/arm/include/asm/system.h                   |   30 ++
  arch/arm/lib/cache-cp15.c                       |   62 +++-
  board/nvidia/common/board.c                     |   21 +-
  board/nvidia/dts/tegra2-seaboard.dts            |   21 +
  common/cmd_echo.c                               |    3 +-
  common/lcd.c                                    |   85 +++-
  doc/device-tree-bindings/video/nvidia-video.txt |   92 ++++
  drivers/video/Makefile                          |    1 +
  drivers/video/tegra.c                           |  388 ++++++++++++++++
  include/configs/seaboard.h                      |   12 +-
  include/configs/tegra2-common.h                 |    1 +
  include/fdtdec.h                                |   17 +
  include/lcd.h                                   |   11 +
  lib/fdtdec.c                                    |   15 +-
  24 files changed, 1862 insertions(+), 31 deletions(-)

Quoted 8 lines

create mode 100644 arch/arm/cpu/armv7/tegra2/display.c create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h create mode 100644 arch/arm/include/asm/arch-tegra2/display.h create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt create mode 100644 drivers/video/tegra.c

Hi Simon,

I have added your patch sources manually into the "Prepare v2012.04-rc1 release", because I got errors at apply. Also I added a device tree source file for Harmony.

I tested the device tree source file for Harmony and your patch sources on our Harmony hardware and generated a new patch file:

Quoted 6 lines

http://poeggi.dotsec.net/nvidia/uboot-lvds-init-patch/0001-Add-display-driver-and-LCD-support-for-Harmony-board.patch

I hope it's all okay, this my first patch release.

In the display.c source file I implemented a bug fix, because I get garbled images on the LCD without this fix.

I see this code:

Quoted 8 lines

      u32 m_value;

      m_value = readl(0x54202e04);
      m_value &= ~0x2;
      writel(m_value, 0x54202e04);

What register are you actually writing here? I can't find it in my manual, but maybe I just haven't seen that address.

At the time I did look for that register as well but couldn't find anything. But I believe that we saw the garbled display issue that has been mentioned in another thread. If I remember correctly this particular register write was the fix for it.

But I wasn't very much involved at the time, so maybe Christian can clarify. However I was going to test your newest version of the LCD patch series on our hardware and see if the issue is still there.

Thierry

+Tom, Stephen

Quoted 111 lines · Thierry Reding

Quoted 101 lines · Simon Glass

Hi Christian,

Quoted 88 lines · Christian Kroehnert

Quoted 69 lines · Simon Glass

This series adds support for the Tegra2x's display peripheral. This supports the LCD display on Seaboard and we use this to enable console output in U-Boot on the LCD.

Configuration is via the device tree. Proposed bindings are included in this series.

To improve performance two optimisations are offered:

1. The LCD frame buffer is cached, with the cache being flushed after each call puts(). This dramatically increases performance (around 10x). This requires a few additions to the ARM cache support.

2. The console supports scrolling in steps of more than 1 line. This speeds up scrolling output considerably, particularly commands like 'printenv' which display a lot of output. This requires a new CONFIG and a change to the console_scrollup() function.

Mayuresh Kulkarni (1):
tegra: Enable display/lcd support on Seaboard

Simon Glass (15):
fdt: Add function to look up a phandle's register address
fdt: Add header guard to fdtdec.h
fdt: Correct GPIO name access in fdtdec
tegra: Add display support to funcmux
tegra: fdt: Add LCD definitions for Tegra
tegra: Add support for PWFM
tegra: Add LCD driver
tegra: Add LCD support to Nvidia boards
arm: Add control over cachability of memory regions
lcd: Add CONFIG_ALIGN_LCD_TO_SECTION to align lcd for MMU
lcd: Add support for flushing LCD fb from dcache after update
tegra: Align LCD frame buffer to section boundary
tegra: Support control of cache settings for LCD
tegra: fdt: Add LCD definitions for Seaboard
lcd: Add CONSOLE_SCROLL_LINES option to speed console

Wei Ni (1):
tegra: Add SOC support for display/lcd

   README                                          |   16 +
   arch/arm/cpu/armv7/cache_v7.c                   |   11 +
   arch/arm/cpu/armv7/tegra2/Makefile              |    1 +
   arch/arm/cpu/armv7/tegra2/display.c             |  271 +++++++++++
   arch/arm/cpu/armv7/tegra2/funcmux.c             |   39 ++
   arch/arm/cpu/armv7/tegra2/pwfm.c                |   40 ++
   arch/arm/dts/tegra20.dtsi                       |   25 +
   arch/arm/include/asm/arch-tegra2/dc.h           |  544
+++++++++++++++++++++++
   arch/arm/include/asm/arch-tegra2/display.h      |  133 ++++++
   arch/arm/include/asm/arch-tegra2/pwfm.h         |   54 +++
   arch/arm/include/asm/system.h                   |   30 ++
   arch/arm/lib/cache-cp15.c                       |   62 +++-
   board/nvidia/common/board.c                     |   21 +-
   board/nvidia/dts/tegra2-seaboard.dts            |   21 +
   common/cmd_echo.c                               |    3 +-
   common/lcd.c                                    |   85 +++-
   doc/device-tree-bindings/video/nvidia-video.txt |   92 ++++
   drivers/video/Makefile                          |    1 +
   drivers/video/tegra.c                           |  388 ++++++++++++++++
   include/configs/seaboard.h                      |   12 +-
   include/configs/tegra2-common.h                 |    1 +
   include/fdtdec.h                                |   17 +
   include/lcd.h                                   |   11 +
   lib/fdtdec.c                                    |   15 +-
   24 files changed, 1862 insertions(+), 31 deletions(-)

Quoted 8 lines

create mode 100644 arch/arm/cpu/armv7/tegra2/display.c create mode 100644 arch/arm/cpu/armv7/tegra2/pwfm.c create mode 100644 arch/arm/include/asm/arch-tegra2/dc.h create mode 100644 arch/arm/include/asm/arch-tegra2/display.h create mode 100644 arch/arm/include/asm/arch-tegra2/pwfm.h create mode 100644 doc/device-tree-bindings/video/nvidia-video.txt create mode 100644 drivers/video/tegra.c

Hi Simon,

I have added your patch sources manually into the "Prepare v2012.04-rc1 release", because I got errors at apply. Also I added a device tree source file for Harmony.

I tested the device tree source file for Harmony and your patch sources on our Harmony hardware and generated a new patch file:

Quoted 6 lines

http://poeggi.dotsec.net/nvidia/uboot-lvds-init-patch/0001-Add-display-driver-and-LCD-support-for-Harmony-board.patch

I hope it's all okay, this my first patch release.

In the display.c source file I implemented a bug fix, because I get garbled images on the LCD without this fix.

I see this code:

Quoted 8 lines

       u32 m_value;

       m_value = readl(0x54202e04);
       m_value &= ~0x2;
       writel(m_value, 0x54202e04);

What register are you actually writing here? I can't find it in my manual, but maybe I just haven't seen that address.

Quoted 8 lines

At the time I did look for that register as well but couldn't find anything. But I believe that we saw the garbled display issue that has been mentioned in another thread. If I remember correctly this particular register write was the fix for it.

But I wasn't very much involved at the time, so maybe Christian can clarify. However I was going to test your newest version of the LCD patch series on our hardware and see if the issue is still there.

Does anyone know what this register is for? I am reluctant to add this code to the patch without at least a comment.

Quoted 2 lines

Thierry

Regards,
Simon

+Tom, Stephen

Quoted 5 lines · Thierry Reding

Quoted 4 lines · Simon Glass

Hi Christian,

On Thu, Apr 19, 2012 at 2:41 PM, Christian Kroehnert <[email protected]> wrote:

Quoted 19 lines

Quoted 5 lines

Quoted 2 lines

In the display.c source file I implemented a bug fix, because I get garbled images on the LCD without this fix.

I see this code:

Quoted 8 lines

      u32 m_value;

      m_value = readl(0x54202e04);
      m_value &= ~0x2;
      writel(m_value, 0x54202e04);

What register are you actually writing here? I can't find it in my manual, but maybe I just haven't seen that address.

At the time I did look for that register as well but couldn't find anything. But I believe that we saw the garbled display issue that has been mentioned in another thread. If I remember correctly this particular register write was the fix for it.

Quoted 3 lines

But I wasn't very much involved at the time, so maybe Christian can clarify. However I was going to test your newest version of the LCD patch series on our hardware and see if the issue is still there.

Does anyone know what this register is for? I am reluctant to add this code to the patch without at least a comment.