irq_domain for imx tzic and gpio

PATCH Superseded Shawn Guo 3 participants 16 messages Feb 11, 2012 – Feb 15, 2012

Subsystems (7)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm i.MX and Layerscape +3 more subsystems

lore

Share & tools

lore

Shawn Guo

author

2012-02-11 17:14 UTC #0 lore raw

cover irq_domain for imx tzic and gpio

The imx tzic and gpio interrupt controllers are implemented as generic-chip, so we can adopt irq_domain support for them based on Rob Herring's effort which adds irq_domain support for genric-chip.

The first patch makes a small change on Rob's series. If he chooses to integrate the change in his patch, I will drop mine. The second patch adds an empty OF function to help !CONFIG_OF buld. The third patch migrates tzic to irq_domain. And rest of the patches change all the static gpio irq number assigning to dynamic one using gpio_to_irq() call, migrate gpio driver to irq_domain, and then eliminates MXC_GPIO_IRQ_START in the end.

The series is based on Rob's branch below.

git://sources.calxeda.com/kernel/linux.git calxeda/pl061-domain-v6

Shawn Guo (8):
irq: choose irq_domain type for generic-chip based on irq_base
dt: add empty of_find_compatible_node function
ARM: imx5: adopt generic_chip irq_domain support for tzic
ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
ARM: imx: eliminate macro IOMUX_TO_IRQ()
ARM: imx: eliminate macro IRQ_GPIOx()
gpio/mxc: adopt irq_domain for gpio interrupt support
ARM: imx: remove macro MXC_GPIO_IRQ_START

 arch/arm/boot/dts/imx51.dtsi                 |    6 +++
 arch/arm/boot/dts/imx53.dtsi                 |    6 +++
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c |    3 +-
 arch/arm/mach-imx/mach-apf9328.c             |    6 ++-
 arch/arm/mach-imx/mach-armadillo5x0.c        |   12 ++++--
 arch/arm/mach-imx/mach-cpuimx27.c            |   12 ++++--
 arch/arm/mach-imx/mach-cpuimx35.c            |    3 +-
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c  |    8 ++--
 arch/arm/mach-imx/mach-imx6q.c               |   14 ------
 arch/arm/mach-imx/mach-kzm_arm11_01.c        |   20 +++++++--
 arch/arm/mach-imx/mach-mx21ads.c             |    5 +-
 arch/arm/mach-imx/mach-mx27_3ds.c            |    3 +-
 arch/arm/mach-imx/mach-mx27ads.c             |   12 +++---
 arch/arm/mach-imx/mach-mx31_3ds.c            |   13 +++---
 arch/arm/mach-imx/mach-mx31ads.c             |   14 ++++--
 arch/arm/mach-imx/mach-mx31lilly.c           |   10 +++-
 arch/arm/mach-imx/mach-mx31lite.c            |   10 +++-
 arch/arm/mach-imx/mach-mx31moboard.c         |    4 +-
 arch/arm/mach-imx/mach-mxt_td60.c            |    6 +-
 arch/arm/mach-imx/mach-pca100.c              |    4 +-
 arch/arm/mach-imx/mach-pcm037.c              |   18 ++++++---
 arch/arm/mach-imx/mach-pcm038.c              |    4 +-
 arch/arm/mach-imx/mach-qong.c                |    9 ++--
 arch/arm/mach-imx/mach-scb9328.c             |    6 ++-
 arch/arm/mach-imx/mach-vpr200.c              |    3 +-
 arch/arm/mach-imx/mx31lilly-db.c             |    5 +-
 arch/arm/mach-imx/mx31lite-db.c              |    5 +-
 arch/arm/mach-imx/pcm970-baseboard.c         |   13 +++---
 arch/arm/mach-mx5/board-cpuimx51.c           |   12 ++++--
 arch/arm/mach-mx5/board-cpuimx51sd.c         |    6 ++-
 arch/arm/mach-mx5/board-mx53_ard.c           |    5 +-
 arch/arm/mach-mx5/clock-mx51-mx53.c          |    4 +-
 arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c |    3 +-
 arch/arm/mach-mx5/imx51-dt.c                 |   29 -------------
 arch/arm/mach-mx5/imx53-dt.c                 |   29 -------------
 arch/arm/mach-mx5/mx51_efika.c               |    3 +-
 arch/arm/plat-mxc/include/mach/common.h      |    2 +
 arch/arm/plat-mxc/include/mach/hardware.h    |    2 -
 arch/arm/plat-mxc/include/mach/iomux-mx3.h   |    3 -
 arch/arm/plat-mxc/include/mach/iomux-v1.h    |   12 +++---
 arch/arm/plat-mxc/include/mach/irqs.h        |    2 -
 arch/arm/plat-mxc/tzic.c                     |   32 ++++++++-------
 drivers/gpio/gpio-mxc.c                      |   56 ++++++++++----------------
 include/linux/of.h                           |    8 ++++
 kernel/irq/generic-chip.c                    |    2 +-
 45 files changed, 218 insertions(+), 226 deletions(-)

Shawn Guo

author

2012-02-11 17:14 UTC #1 lore raw

PATCH 1/8 irq: choose irq_domain type for generic-chip based on irq_base

Choosing irq_domain type for generic-chip based on device_node forces non-DT users to use legacy irq_domain, which makes no sense, because linear irq_domain is actually encouraged to be used by both DT and non-DT users.

The patch changes it to make the decision based on irq_base. If users pass in a negative irq_base value, a linear irq_domain will be created, otherwise a legacy irq_domain will be created.

Signed-off-by Shawn Guo <[email protected]>

Cc Rob Herring <[email protected]>

Cc Grant Likely <[email protected]>

Cc Thomas Gleixner <[email protected]>

---
 kernel/irq/generic-chip.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

kernel/irq/generic-chip.c +1 -1

index 3ac7fa1..839f882 100644
@@ -346,7 +346,7 @@ int irq_setup_generic_chip_domain(const char *name, struct device_node *node,
 		irq_setup_generic_chip(gc[i], 0, flags, clr, set);
 	}
 
-	if (node)
+	if ((int) irq_base < 0)
 		d = irq_domain_add_linear(node, hwirq_cnt,
 					  &irq_gc_irq_domain_ops, gc);
 	else

Signature · 1 line

1.7.5.4

Rob Herring

NAK

2012-02-13 21:38 UTC #2 lore raw

PATCH 1/8 irq: choose irq_domain type for generic-chip based on irq_base

Quoted 4 lines · Shawn Guo

Choosing irq_domain type for generic-chip based on device_node forces non-DT users to use legacy irq_domain, which makes no sense, because linear irq_domain is actually encouraged to be used by both DT and non-DT users.

NAK

Encouraged by who? As we discussed in person at Connect, I said you should use legacy domain for non-DT case. Grant and I have discussed this as well and agree.

Quoted 3 lines

The patch changes it to make the decision based on irq_base. If users pass in a negative irq_base value, a linear irq_domain will be created, otherwise a legacy irq_domain will be created.

This allows DT users to decide as well and possibly use legacy domains which is explicitly what I was trying to prevent. DT users must use linear domains and non-DT must use legacy. Otherwise, we'll get more half done DT conversions like mx5 is.

Getting linear domains to work for non-DT to work would be a worthwhile goal if we didn't plan to remove non-DT boards. I don't think we really need linear to work for non-DT case.

Rob

Quoted 21 lines

Signed-off-by Shawn Guo <[email protected]>

Cc Rob Herring <[email protected]>

Cc Grant Likely <[email protected]>

Cc Thomas Gleixner <[email protected]>

---
 kernel/irq/generic-chip.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

kernel/irq/generic-chip.c +1 -1

index 3ac7fa1..839f882 100644
@@ -346,7 +346,7 @@ int irq_setup_generic_chip_domain(const char *name, struct device_node *node,
 		irq_setup_generic_chip(gc[i], 0, flags, clr, set);
 	}
 
-	if (node)
+	if ((int) irq_base < 0)
 		d = irq_domain_add_linear(node, hwirq_cnt,
 					  &irq_gc_irq_domain_ops, gc);
 	else

Grant Likely

2012-02-15 21:20 UTC #3 lore raw

PATCH 1/8 irq: choose irq_domain type for generic-chip based on irq_base

Quoted 11 lines · Rob Herring

Quoted 4 lines · Shawn Guo
Choosing irq_domain type for generic-chip based on device_node forces non-DT users to use legacy irq_domain, which makes no sense, because linear irq_domain is actually encouraged to be used by both DT and non-DT users.
NAK
Encouraged by who? As we discussed in person at Connect, I said you should use legacy domain for non-DT case. Grant and I have discussed this as well and agree.

Yes. I'd *like* for everyone (DT and non-DT) to be able to use the linear revmap, but I can't see any nice way to do it as long as devices are registered with hard coded #define irq numbers.

Quoted 5 lines

Quoted 4 lines
The patch changes it to make the decision based on irq_base. If users pass in a negative irq_base value, a linear irq_domain will be created, otherwise a legacy irq_domain will be created.

Quoted 8 lines

This allows DT users to decide as well and possibly use legacy domains which is explicitly what I was trying to prevent. DT users must use linear domains and non-DT must use legacy. Otherwise, we'll get more half done DT conversions like mx5 is.
Getting linear domains to work for non-DT to work would be a worthwhile goal if we didn't plan to remove non-DT boards. I don't think we really need linear to work for non-DT case.

I agree with that.

Quoted 25 lines

Rob

Quoted 21 lines

Signed-off-by Shawn Guo <[email protected]>

Cc Rob Herring <[email protected]>

Cc Grant Likely <[email protected]>

Cc Thomas Gleixner <[email protected]>

---
 kernel/irq/generic-chip.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

kernel/irq/generic-chip.c +1 -1

index 3ac7fa1..839f882 100644
@@ -346,7 +346,7 @@ int irq_setup_generic_chip_domain(const char *name, struct device_node *node,
 		irq_setup_generic_chip(gc[i], 0, flags, clr, set);
 	}
 
-	if (node)
+	if ((int) irq_base < 0)
 		d = irq_domain_add_linear(node, hwirq_cnt,
 					  &irq_gc_irq_domain_ops, gc);
 	else

Shawn Guo

author

2012-02-11 17:14 UTC #4 lore raw

PATCH 2/8 dt: add empty of_find_compatible_node function

In reply to Shawn Guo

Add empty of_find_compatible_node function for !CONFIG_OF build.

Signed-off-by Shawn Guo <[email protected]>

---
 include/linux/of.h |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

include/linux/of.h +8 -0

index a75a831..92cf6ad 100644
@@ -281,6 +281,14 @@ static inline struct property *of_find_property(const struct device_node *np,
 	return NULL;
 }
 
+static inline struct device_node *of_find_compatible_node(
+						struct device_node *from,
+						const char *type,
+						const char *compat)
+{
+	return NULL;
+}
+
 static inline int of_property_read_u32_array(const struct device_node *np,
 					     const char *propname,
 					     u32 *out_values, size_t sz)

Signature · 1 line

1.7.5.4

Shawn Guo

author

2012-02-11 17:14 UTC #5 lore raw

PATCH 3/8 ARM: imx5: adopt generic_chip irq_domain support for tzic

In reply to Shawn Guo

It adopts generic_chip irq_domain support for tzic, so that the irq_domain initialization for tzic in imx5 DT platform code can be removed.

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/boot/dts/imx51.dtsi            |    6 +++++
 arch/arm/boot/dts/imx53.dtsi            |    6 +++++
 arch/arm/mach-mx5/clock-mx51-mx53.c     |    4 +-
 arch/arm/mach-mx5/imx51-dt.c            |    8 -------
 arch/arm/mach-mx5/imx53-dt.c            |    8 -------
 arch/arm/plat-mxc/include/mach/common.h |    2 +
 arch/arm/plat-mxc/tzic.c                |   32 ++++++++++++++++--------------
 7 files changed, 33 insertions(+), 33 deletions(-)

arch/arm/boot/dts/imx51.dtsi +6 -0

index 6663986..a5fda43 100644
@@ -171,6 +171,12 @@
 				status = "disabled";
 			};
 
+			gpt at 73fa0000 {
+				compatible = "fsl,imx51-gpt", "fsl,gpt";
+				reg = <0x73fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 73fbc000 {
 				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 				reg = <0x73fbc000 0x4000>;

arch/arm/boot/dts/imx53.dtsi +6 -0

index 5dd91b9..05e6412 100644
@@ -173,6 +173,12 @@
 				status = "disabled";
 			};
 
+			gpt at 53fa0000 {
+				compatible = "fsl,imx53-gpt", "fsl,gpt";
+				reg = <0x53fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 53fbc000 {
 				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 				reg = <0x53fbc000 0x4000>;

arch/arm/mach-mx5/clock-mx51-mx53.c +2 -2

index 4cb2769..c558cb1 100644
@@ -1593,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-		MX51_INT_GPT);
+		       tzic_irq_create_mapping(MX51_INT_GPT));
 	return 0;
 }

@@ -1630,7 +1630,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
 
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
-		MX53_INT_GPT);
+		       tzic_irq_create_mapping(MX53_INT_GPT));
 	return 0;
 }

arch/arm/mach-mx5/imx51-dt.c +0 -8

index 1e03ef4..45abf11 100644
@@ -44,13 +44,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static int __init imx51_tzic_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-	return 0;
-}
-
 static int __init imx51_gpio_add_irq_domain(struct device_node *np,
 				struct device_node *interrupt_parent)
 {

@@ -63,7 +56,6 @@ static int __init imx51_gpio_add_irq_domain(struct device_node *np,
 }
 
 static const struct of_device_id imx51_irq_match[] __initconst = {
-	{ .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
 	{ .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };

arch/arm/mach-mx5/imx53-dt.c +0 -8

index fd5be0f..52efb32 100644
@@ -48,13 +48,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static int __init imx53_tzic_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-	return 0;
-}
-
 static int __init imx53_gpio_add_irq_domain(struct device_node *np,
 				struct device_node *interrupt_parent)
 {

@@ -67,7 +60,6 @@ static int __init imx53_gpio_add_irq_domain(struct device_node *np,
 }
 
 static const struct of_device_id imx53_irq_match[] __initconst = {
-	{ .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
 	{ .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };

arch/arm/plat-mxc/include/mach/common.h +2 -0

index 1bf0df8..590153c 100644
@@ -101,6 +101,8 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx53_handle_irq tzic_handle_irq
 #define imx6q_handle_irq gic_handle_irq
 
+extern unsigned int tzic_irq_create_mapping(unsigned int hwirq);
+
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 #ifdef CONFIG_DEBUG_LL

arch/arm/plat-mxc/tzic.c +17 ~~-15~~

index 98308ec..69afe59 100644
@@ -15,6 +15,7 @@
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
 
 #include <asm/mach/irq.h>
 #include <asm/exception.h>

@@ -49,6 +50,7 @@
 #define TZIC_ID0	0x0FD0	/* Indentification Register 0 */
 
 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
+static struct irq_chip_generic *tzic_gc;
 
 #define TZIC_NUM_IRQS 128

@@ -77,15 +79,14 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 static void tzic_irq_suspend(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	int idx = gc->irq_base >> 5;
+	int idx = d->hwirq / 32;
 
 	__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
 }
 
 static void tzic_irq_resume(struct irq_data *d)
 {
-	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	int idx = gc->irq_base >> 5;
+	int idx = d->hwirq / 32;
 
 	__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
 		     tzic_base + TZIC_WAKEUP0(idx));

@@ -102,18 +103,14 @@ static struct mxc_extra_irq tzic_extra_irq = {
 #endif
 };
 
-static __init void tzic_init_gc(unsigned int irq_start)
+static __init void tzic_init_gc(struct irq_chip_generic *gc)
 {
-	struct irq_chip_generic *gc;
-	struct irq_chip_type *ct;
-	int idx = irq_start >> 5;
+	struct irq_chip_type *ct = gc->chip_types;
+	int idx = gc->hwirq_base / 32;
 
-	gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
-				    handle_level_irq);
-	gc->private = &tzic_extra_irq;
+	tzic_gc = gc;
 	gc->wake_enabled = IRQ_MSK(32);
 
-	ct = gc->chip_types;
 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 	ct->chip.irq_set_wake = irq_gc_set_wake;

@@ -121,8 +118,6 @@ static __init void tzic_init_gc(unsigned int irq_start)
 	ct->chip.irq_resume = tzic_irq_resume;
 	ct->regs.disable = TZIC_ENCLEAR0(idx);
 	ct->regs.enable = TZIC_ENSET0(idx);
-
-	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
 
 asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)

@@ -175,8 +170,10 @@ void __init tzic_init_irq(void __iomem *irqbase)
 
 	/* all IRQ no FIQ Warning :: No selection */
 
-	for (i = 0; i < TZIC_NUM_IRQS; i += 32)
-		tzic_init_gc(i);
+	irq_setup_generic_chip_domain("tzic",
+			of_find_compatible_node(NULL, NULL, "fsl,tzic"),
+			1, 0, tzic_base, handle_level_irq, TZIC_NUM_IRQS,
+			0, IRQ_NOREQUEST, 0, tzic_init_gc, &tzic_extra_irq);
 
 #ifdef CONFIG_FIQ
 	/* Initialize FIQ */

@@ -205,3 +202,8 @@ int tzic_enable_wake(void)
 
 	return 0;
 }
+
+unsigned int tzic_irq_create_mapping(unsigned int hwirq)
+{
+	return irq_create_mapping(tzic_gc->domain, hwirq);
+}

Signature · 1 line

1.7.5.4

Rob Herring

2012-02-12 03:31 UTC #6 lore raw

PATCH 3/8 ARM: imx5: adopt generic_chip irq_domain support for tzic

Shawn,

Quoted 4 lines · Shawn Guo

It adopts generic_chip irq_domain support for tzic, so that the irq_domain initialization for tzic in imx5 DT platform code can be removed.

As I found in my attempt to re-factor this and we discussed, the init flow is all wrong for mx5.

The mach .init_irq function should call of_irq_init. mx5 is initializing tzic and then calling of_irq_init in the platform init calls which is wrong. Ultimately the compatible list should probably include avic, tzic, gic and any other secondary controllers you have. The of_irq_init callbacks need to do ioremap and initialize the controller. You're basically removing the use of of_irq_init here.

Some more comments below.

Quoted 50 lines

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/boot/dts/imx51.dtsi            |    6 +++++
 arch/arm/boot/dts/imx53.dtsi            |    6 +++++
 arch/arm/mach-mx5/clock-mx51-mx53.c     |    4 +-
 arch/arm/mach-mx5/imx51-dt.c            |    8 -------
 arch/arm/mach-mx5/imx53-dt.c            |    8 -------
 arch/arm/plat-mxc/include/mach/common.h |    2 +
 arch/arm/plat-mxc/tzic.c                |   32 ++++++++++++++++--------------
 7 files changed, 33 insertions(+), 33 deletions(-)

arch/arm/boot/dts/imx51.dtsi +6 -0

index 6663986..a5fda43 100644
@@ -171,6 +171,12 @@
 				status = "disabled";
 			};
 
+			gpt at 73fa0000 {
+				compatible = "fsl,imx51-gpt", "fsl,gpt";
+				reg = <0x73fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 73fbc000 {
 				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 				reg = <0x73fbc000 0x4000>;

arch/arm/boot/dts/imx53.dtsi +6 -0

index 5dd91b9..05e6412 100644
@@ -173,6 +173,12 @@
 				status = "disabled";
 			};
 
+			gpt at 53fa0000 {
+				compatible = "fsl,imx53-gpt", "fsl,gpt";
+				reg = <0x53fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 53fbc000 {
 				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 				reg = <0x53fbc000 0x4000>;

arch/arm/mach-mx5/clock-mx51-mx53.c +0 -0

index 4cb2769..c558cb1 100644

arch/arm/mach-mx5/clock-mx51-mx53.c int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, · line 1596

Quoted 5 lines

arch/arm/mach-mx5/clock-mx51-mx53.c +1 -1

@@ -1593,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-		MX51_INT_GPT);
+		       tzic_irq_create_mapping(MX51_INT_GPT));

In the DT case, you should be calling irq_of_parse_and_map to setup the timer irq.

I really think you need to separate DT and non-DT init functions. You need to ultimately be getting both the base address and the irq from the dts. This applies to both timer and irq controllers. If you make the init code better separated, then you won't have the problems with legacy vs. linear domains.

Quoted 148 lines

arch/arm/mach-mx5/clock-mx51-mx53.c +1 -1

 	return 0;
 }

@@ -1630,7 +1630,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
 
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
-		MX53_INT_GPT);
+		       tzic_irq_create_mapping(MX53_INT_GPT));
 	return 0;
 }

arch/arm/mach-mx5/imx51-dt.c +0 -8

index 1e03ef4..45abf11 100644
@@ -44,13 +44,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static int __init imx51_tzic_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-	return 0;
-}
-
 static int __init imx51_gpio_add_irq_domain(struct device_node *np,
 				struct device_node *interrupt_parent)
 {

@@ -63,7 +56,6 @@ static int __init imx51_gpio_add_irq_domain(struct device_node *np,
 }
 
 static const struct of_device_id imx51_irq_match[] __initconst = {
-	{ .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
 	{ .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };

arch/arm/mach-mx5/imx53-dt.c +0 -8

index fd5be0f..52efb32 100644
@@ -48,13 +48,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static int __init imx53_tzic_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	irq_domain_add_legacy(np, 128, 0, 0, &irq_domain_simple_ops, NULL);
-	return 0;
-}
-
 static int __init imx53_gpio_add_irq_domain(struct device_node *np,
 				struct device_node *interrupt_parent)
 {

@@ -67,7 +60,6 @@ static int __init imx53_gpio_add_irq_domain(struct device_node *np,
 }
 
 static const struct of_device_id imx53_irq_match[] __initconst = {
-	{ .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
 	{ .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };

arch/arm/plat-mxc/include/mach/common.h +2 -0

index 1bf0df8..590153c 100644
@@ -101,6 +101,8 @@ void tzic_handle_irq(struct pt_regs *);
 #define imx53_handle_irq tzic_handle_irq
 #define imx6q_handle_irq gic_handle_irq
 
+extern unsigned int tzic_irq_create_mapping(unsigned int hwirq);
+
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 #ifdef CONFIG_DEBUG_LL

arch/arm/plat-mxc/tzic.c +8 ~~-13~~

index 98308ec..69afe59 100644
@@ -15,6 +15,7 @@
 #include <linux/device.h>
 #include <linux/errno.h>
 #include <linux/io.h>
+#include <linux/irqdomain.h>
 
 #include <asm/mach/irq.h>
 #include <asm/exception.h>

@@ -49,6 +50,7 @@
 #define TZIC_ID0	0x0FD0	/* Indentification Register 0 */
 
 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
+static struct irq_chip_generic *tzic_gc;
 
 #define TZIC_NUM_IRQS 128

@@ -77,15 +79,14 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
 static void tzic_irq_suspend(struct irq_data *d)
 {
 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	int idx = gc->irq_base >> 5;
+	int idx = d->hwirq / 32;
 
 	__raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx));
 }
 
 static void tzic_irq_resume(struct irq_data *d)
 {
-	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
-	int idx = gc->irq_base >> 5;
+	int idx = d->hwirq / 32;
 
 	__raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)),
 		     tzic_base + TZIC_WAKEUP0(idx));

@@ -102,18 +103,14 @@ static struct mxc_extra_irq tzic_extra_irq = {
 #endif
 };
 
-static __init void tzic_init_gc(unsigned int irq_start)
+static __init void tzic_init_gc(struct irq_chip_generic *gc)
 {
-	struct irq_chip_generic *gc;
-	struct irq_chip_type *ct;
-	int idx = irq_start >> 5;
+	struct irq_chip_type *ct = gc->chip_types;
+	int idx = gc->hwirq_base / 32;
 
-	gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
-				    handle_level_irq);
-	gc->private = &tzic_extra_irq;
+	tzic_gc = gc;
 	gc->wake_enabled = IRQ_MSK(32);
 
-	ct = gc->chip_types;
 	ct->chip.irq_mask = irq_gc_mask_disable_reg;
 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
 	ct->chip.irq_set_wake = irq_gc_set_wake;

@@ -121,8 +118,6 @@ static __init void tzic_init_gc(unsigned int irq_start)
 	ct->chip.irq_resume = tzic_irq_resume;
 	ct->regs.disable = TZIC_ENCLEAR0(idx);
 	ct->regs.enable = TZIC_ENSET0(idx);
-
-	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
 
 asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)

arch/arm/plat-mxc/tzic.c void __init tzic_init_irq(void __iomem *irqbase) · line 174

Quoted 7 lines

arch/arm/plat-mxc/tzic.c +2 -2

@@ -175,8 +170,10 @@ void __init tzic_init_irq(void __iomem *irqbase)
 
 	/* all IRQ no FIQ Warning :: No selection */
 
-	for (i = 0; i < TZIC_NUM_IRQS; i += 32)
-		tzic_init_gc(i);
+	irq_setup_generic_chip_domain("tzic",
+			of_find_compatible_node(NULL, NULL, "fsl,tzic"),

You should already have a node pointer at this point. Pass it into this function and get it from the of_irq_init callback.

Rob

Quoted 14 lines

arch/arm/plat-mxc/tzic.c +7 -0

+			1, 0, tzic_base, handle_level_irq, TZIC_NUM_IRQS,
+			0, IRQ_NOREQUEST, 0, tzic_init_gc, &tzic_extra_irq);
 
 #ifdef CONFIG_FIQ
 	/* Initialize FIQ */

@@ -205,3 +202,8 @@ int tzic_enable_wake(void)
 
 	return 0;
 }
+
+unsigned int tzic_irq_create_mapping(unsigned int hwirq)
+{
+	return irq_create_mapping(tzic_gc->domain, hwirq);
+}

Shawn Guo

author

2012-02-13 13:51 UTC #7 lore raw

PATCH 3/8 ARM: imx5: adopt generic_chip irq_domain support for tzic

Quoted 11 lines · Rob Herring

Shawn,
Quoted 4 lines · Shawn Guo
It adopts generic_chip irq_domain support for tzic, so that the irq_domain initialization for tzic in imx5 DT platform code can be removed.
As I found in my attempt to re-factor this and we discussed, the init flow is all wrong for mx5.

But if we put this from point of supporting DT and non-DT with less code churning, I would not way it's "wrong", or I would say I made it "wrong" on purpose.

Quoted 5 lines

The mach .init_irq function should call of_irq_init. mx5 is initializing tzic and then calling of_irq_init in the platform init calls which is wrong. Ultimately the compatible list should probably include avic, tzic, gic and any other secondary controllers you have. The of_irq_init callbacks need to do ioremap and initialize the controller.

Yes, this is absolutely right for DT only support. But we are supporting both DT and non-DT in a single image with the desire of less code churning.

Quoted 3 lines

You're
basically removing the use of of_irq_init here.

The of_irq_init was added for hacking irqdomain initialization on imx5 at the first place. Now the hack is replaced by generic-chip irqdomain support, so the of_irq_init goes away here. And I agree that we need it for separating DT from non-DT support, but that belongs to another series, and this series is just cleaning up irqdomain support.

Quoted 61 lines

Some more comments below.

Quoted 50 lines

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/boot/dts/imx51.dtsi            |    6 +++++
 arch/arm/boot/dts/imx53.dtsi            |    6 +++++
 arch/arm/mach-mx5/clock-mx51-mx53.c     |    4 +-
 arch/arm/mach-mx5/imx51-dt.c            |    8 -------
 arch/arm/mach-mx5/imx53-dt.c            |    8 -------
 arch/arm/plat-mxc/include/mach/common.h |    2 +
 arch/arm/plat-mxc/tzic.c                |   32 ++++++++++++++++--------------
 7 files changed, 33 insertions(+), 33 deletions(-)

arch/arm/boot/dts/imx51.dtsi +6 -0

index 6663986..a5fda43 100644
@@ -171,6 +171,12 @@
 				status = "disabled";
 			};
 
+			gpt at 73fa0000 {
+				compatible = "fsl,imx51-gpt", "fsl,gpt";
+				reg = <0x73fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 73fbc000 {
 				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 				reg = <0x73fbc000 0x4000>;

arch/arm/boot/dts/imx53.dtsi +6 -0

index 5dd91b9..05e6412 100644
@@ -173,6 +173,12 @@
 				status = "disabled";
 			};
 
+			gpt at 53fa0000 {
+				compatible = "fsl,imx53-gpt", "fsl,gpt";
+				reg = <0x53fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 53fbc000 {
 				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 				reg = <0x53fbc000 0x4000>;

arch/arm/mach-mx5/clock-mx51-mx53.c +0 -0

index 4cb2769..c558cb1 100644

arch/arm/mach-mx5/clock-mx51-mx53.c int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, · line 1596

Quoted 5 lines

arch/arm/mach-mx5/clock-mx51-mx53.c +1 -1

@@ -1593,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-		MX51_INT_GPT);
+		       tzic_irq_create_mapping(MX51_INT_GPT));

In the DT case, you should be calling irq_of_parse_and_map to setup the timer irq.

Quoted 3 lines

I really think you need to separate DT and non-DT init functions. You need to ultimately be getting both the base address and the irq from the dts. This applies to both timer and irq controllers.

Yes, I agree with you I need to do those at some point when we fully support DT and get ready to remove the non-DT support completely. But we are not there yet. Can I cook another series to do that when we get there, so that we make this series stay clean and focusing?

Quoted 4 lines

If you make the
init code better separated, then you won't have the problems with legacy vs. linear domains.

I do not have any problem here, since both DT and non-DT are using linear domain. Isn't this something encouraged to do?

Signature · 2 lines

Regards,
Shawn

Rob Herring

2012-02-13 14:22 UTC #8 lore raw

PATCH 3/8 ARM: imx5: adopt generic_chip irq_domain support for tzic

Quoted 22 lines · Shawn Guo

Quoted 11 lines · Rob Herring
Shawn,
Quoted 4 lines · Shawn Guo
It adopts generic_chip irq_domain support for tzic, so that the irq_domain initialization for tzic in imx5 DT platform code can be removed.
As I found in my attempt to re-factor this and we discussed, the init flow is all wrong for mx5.
But if we put this from point of supporting DT and non-DT with less code churning, I would not way it's "wrong", or I would say I made it "wrong" on purpose.
Quoted 5 lines
The mach .init_irq function should call of_irq_init. mx5 is initializing tzic and then calling of_irq_init in the platform init calls which is wrong. Ultimately the compatible list should probably include avic, tzic, gic and any other secondary controllers you have. The of_irq_init callbacks need to do ioremap and initialize the controller.

Quoted 4 lines

Yes, this is absolutely right for DT only support. But we are supporting both DT and non-DT in a single image with the desire of less code churning.

You're not saving anything, just delaying changes when you want to remove the non-DT code paths in the future.

Quoted 9 lines

Quoted 3 lines
You're
basically removing the use of of_irq_init here.
The of_irq_init was added for hacking irqdomain initialization on imx5 at the first place. Now the hack is replaced by generic-chip irqdomain support, so the of_irq_init goes away here. And I agree that we need it for separating DT from non-DT support, but that belongs to another series, and this series is just cleaning up irqdomain support.

No. Those are completely orthogonal. The way it was added for mx5 was certainly a hack though. of_irq_init has nothing to do with domains. It's purpose is to initialize interrupt controllers in the right order. You can't initialize secondary controllers before primary controllers. It removes the init ordering knowledge from the kernel and uses knowledge that's already present in the DT.

Quoted 61 lines

Some more comments below.

Quoted 50 lines

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/boot/dts/imx51.dtsi            |    6 +++++
 arch/arm/boot/dts/imx53.dtsi            |    6 +++++
 arch/arm/mach-mx5/clock-mx51-mx53.c     |    4 +-
 arch/arm/mach-mx5/imx51-dt.c            |    8 -------
 arch/arm/mach-mx5/imx53-dt.c            |    8 -------
 arch/arm/plat-mxc/include/mach/common.h |    2 +
 arch/arm/plat-mxc/tzic.c                |   32 ++++++++++++++++--------------
 7 files changed, 33 insertions(+), 33 deletions(-)

arch/arm/boot/dts/imx51.dtsi +6 -0

index 6663986..a5fda43 100644
@@ -171,6 +171,12 @@
 				status = "disabled";
 			};
 
+			gpt at 73fa0000 {
+				compatible = "fsl,imx51-gpt", "fsl,gpt";
+				reg = <0x73fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 73fbc000 {
 				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 				reg = <0x73fbc000 0x4000>;

arch/arm/boot/dts/imx53.dtsi +6 -0

index 5dd91b9..05e6412 100644
@@ -173,6 +173,12 @@
 				status = "disabled";
 			};
 
+			gpt at 53fa0000 {
+				compatible = "fsl,imx53-gpt", "fsl,gpt";
+				reg = <0x53fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 53fbc000 {
 				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 				reg = <0x53fbc000 0x4000>;

arch/arm/mach-mx5/clock-mx51-mx53.c +0 -0

index 4cb2769..c558cb1 100644

arch/arm/mach-mx5/clock-mx51-mx53.c int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, · line 1596

Quoted 5 lines

arch/arm/mach-mx5/clock-mx51-mx53.c +1 -1

@@ -1593,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-		MX51_INT_GPT);
+		       tzic_irq_create_mapping(MX51_INT_GPT));

In the DT case, you should be calling irq_of_parse_and_map to setup the timer irq.

Quoted 9 lines

Quoted 3 lines
I really think you need to separate DT and non-DT init functions. You need to ultimately be getting both the base address and the irq from the dts. This applies to both timer and irq controllers.
Yes, I agree with you I need to do those at some point when we fully support DT and get ready to remove the non-DT support completely. But we are not there yet. Can I cook another series to do that when we get there, so that we make this series stay clean and focusing?

Removing non-DT support has nothing to do with having full DT support.

Quoted 6 lines

Quoted 4 lines
If you make the
init code better separated, then you won't have the problems with legacy vs. linear domains.
I do not have any problem here, since both DT and non-DT are using linear domain. Isn't this something encouraged to do?

You are making things harder on yourself trying to get linear domains to work for non-DT. Just use legacy.

Rob

Shawn Guo

author

2012-02-13 15:19 UTC #9 lore raw

PATCH 3/8 ARM: imx5: adopt generic_chip irq_domain support for tzic

Quoted 23 lines · Rob Herring

Quoted 22 lines · Shawn Guo
Quoted 11 lines · Rob Herring
Shawn,
Quoted 4 lines · Shawn Guo
It adopts generic_chip irq_domain support for tzic, so that the irq_domain initialization for tzic in imx5 DT platform code can be removed.
As I found in my attempt to re-factor this and we discussed, the init flow is all wrong for mx5.
But if we put this from point of supporting DT and non-DT with less code churning, I would not way it's "wrong", or I would say I made it "wrong" on purpose.
Quoted 5 lines
The mach .init_irq function should call of_irq_init. mx5 is initializing tzic and then calling of_irq_init in the platform init calls which is wrong. Ultimately the compatible list should probably include avic, tzic, gic and any other secondary controllers you have. The of_irq_init callbacks need to do ioremap and initialize the controller.

Quoted 8 lines

Quoted 4 lines
Yes, this is absolutely right for DT only support. But we are supporting both DT and non-DT in a single image with the desire of less code churning.
You're not saving anything, just delaying changes when you want to remove the non-DT code paths in the future.

Yes, that's right. But what's the pressure to do that with mixing two different things in one series. To me, the separation belongs to another series.

Quoted 10 lines

Quoted 9 lines
Quoted 3 lines
You're
basically removing the use of of_irq_init here.
The of_irq_init was added for hacking irqdomain initialization on imx5 at the first place. Now the hack is replaced by generic-chip irqdomain support, so the of_irq_init goes away here. And I agree that we need it for separating DT from non-DT support, but that belongs to another series, and this series is just cleaning up irqdomain support.

Quoted 7 lines

No. Those are completely orthogonal. The way it was added for mx5 was certainly a hack though. of_irq_init has nothing to do with domains. It's purpose is to initialize interrupt controllers in the right order. You can't initialize secondary controllers before primary controllers. It removes the init ordering knowledge from the kernel and uses knowledge that's already present in the DT.

Ok, that makes sense to me. But on imx5, tzic is the primary interrupt controller which gets initialized in .init_irq, and gpio is the secondary interrupt controller which gets initialized in gpio driver probe function. There is no init order issue, and I do not even have a init function for imx gpio driver to be called by of_irq_init. (Do you one for highbank/pl061 case?) So there is really no need for imx5 to call of_irq_init in terms of init order of multiple interrupt controllers.

Quoted 65 lines

Quoted 64 lines

Some more comments below.

Quoted 50 lines

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/boot/dts/imx51.dtsi            |    6 +++++
 arch/arm/boot/dts/imx53.dtsi            |    6 +++++
 arch/arm/mach-mx5/clock-mx51-mx53.c     |    4 +-
 arch/arm/mach-mx5/imx51-dt.c            |    8 -------
 arch/arm/mach-mx5/imx53-dt.c            |    8 -------
 arch/arm/plat-mxc/include/mach/common.h |    2 +
 arch/arm/plat-mxc/tzic.c                |   32 ++++++++++++++++--------------
 7 files changed, 33 insertions(+), 33 deletions(-)

arch/arm/boot/dts/imx51.dtsi +6 -0

index 6663986..a5fda43 100644
@@ -171,6 +171,12 @@
 				status = "disabled";
 			};
 
+			gpt at 73fa0000 {
+				compatible = "fsl,imx51-gpt", "fsl,gpt";
+				reg = <0x73fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 73fbc000 {
 				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
 				reg = <0x73fbc000 0x4000>;

arch/arm/boot/dts/imx53.dtsi +6 -0

index 5dd91b9..05e6412 100644
@@ -173,6 +173,12 @@
 				status = "disabled";
 			};
 
+			gpt at 53fa0000 {
+				compatible = "fsl,imx53-gpt", "fsl,gpt";
+				reg = <0x53fa0000 0x4000>;
+				interrupts = <39>;
+			};
+
 			uart1: uart at 53fbc000 {
 				compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 				reg = <0x53fbc000 0x4000>;

arch/arm/mach-mx5/clock-mx51-mx53.c +0 -0

index 4cb2769..c558cb1 100644

arch/arm/mach-mx5/clock-mx51-mx53.c int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, · line 1596

Quoted 5 lines

arch/arm/mach-mx5/clock-mx51-mx53.c +1 -1

@@ -1593,7 +1593,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
 
 	/* System timer */
 	mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
-		MX51_INT_GPT);
+		       tzic_irq_create_mapping(MX51_INT_GPT));

In the DT case, you should be calling irq_of_parse_and_map to setup the timer irq.

I really think you need to separate DT and non-DT init functions. You need to ultimately be getting both the base address and the irq from the dts. This applies to both timer and irq controllers.

Quoted 8 lines

Quoted 5 lines
Yes, I agree with you I need to do those at some point when we fully support DT and get ready to remove the non-DT support completely. But we are not there yet. Can I cook another series to do that when we get there, so that we make this series stay clean and focusing?
Removing non-DT support has nothing to do with having full DT support.

Sorry, I do not quite understanding that. How can we remove non-DT support before we get a full DT support ready?

Quoted 10 lines

Quoted 6 lines
Quoted 4 lines
If you make the
init code better separated, then you won't have the problems with legacy vs. linear domains.
I do not have any problem here, since both DT and non-DT are using linear domain. Isn't this something encouraged to do?
You are making things harder on yourself trying to get linear domains to work for non-DT. Just use legacy.

On the contrary, I'm seeing it's harder to use legacy for non-DT and linear for DT in a single image.

Supposing we are doing what you suggest to do here, before we call irq_setup_generic_chip_domain for imx gpio driver (gpio-mxc.c) to set up legacy domain for DT users, we need to have an irq_base for the gpio interrupt controller. Since we are cleaning those static irq number, we have to call irq_alloc_desc to get the irq_base and pass it to irq_setup_generic_chip_domain. However, this should not be done for DT/linear users. So you will need to fork the code patch for DT and non-DT case. It will be much simpler with using linear for both DT and non-DT because passing a -1 as the irq_base just works for both cases.

Signature · 2 lines

Regards,
Shawn

Shawn Guo

author

2012-02-13 15:34 UTC #10 lore raw

PATCH 3/8 ARM: imx5: adopt generic_chip irq_domain support for tzic

Sorry, one typo below.

On Mon, Feb 13, 2012 at 07:19:55AM -0800, Shawn Guo wrote:
...

Quoted 3 lines

Supposing we are doing what you suggest to do here, before we call irq_setup_generic_chip_domain for imx gpio driver (gpio-mxc.c) to set up legacy domain for DT users, we need to have an irq_base for the gpio

s/DT/non-DT

Quoted 7 lines

interrupt controller. Since we are cleaning those static irq number, we have to call irq_alloc_desc to get the irq_base and pass it to irq_setup_generic_chip_domain. However, this should not be done for DT/linear users. So you will need to fork the code patch for DT and non-DT case. It will be much simpler with using linear for both DT and non-DT because passing a -1 as the irq_base just works for both cases.

Signature · 2 lines

Regards,
Shawn

Shawn Guo

author

2012-02-11 17:14 UTC #11 lore raw

PATCH 4/8 ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()

In reply to Shawn Guo

This patch changes all the static gpio irq number assigning with IMX_GPIO_TO_IRQ() to run-time assigning with gpio_to_irq call, and in turn eliminates the macro IMX_GPIO_TO_IRQ().

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/mach-imx/mach-cpuimx35.c            |    3 ++-
 arch/arm/mach-imx/mach-mx27_3ds.c            |    3 ++-
 arch/arm/mach-imx/mach-vpr200.c              |    3 ++-
 arch/arm/mach-mx5/board-cpuimx51.c           |   12 ++++++++----
 arch/arm/mach-mx5/board-cpuimx51sd.c         |    6 ++++--
 arch/arm/mach-mx5/board-mx53_ard.c           |    5 +++--
 arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c |    3 ++-
 arch/arm/mach-mx5/mx51_efika.c               |    3 ++-
 arch/arm/plat-mxc/include/mach/hardware.h    |    2 --
 9 files changed, 25 insertions(+), 15 deletions(-)

arch/arm/mach-imx/mach-cpuimx35.c +2 -1

index 8ecc872..ad52a61 100644
@@ -72,7 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
 		I2C_BOARD_INFO("tsc2007", 0x48),
 		.type		= "tsc2007",
 		.platform_data	= &tsc2007_info,
-		.irq		= IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
+		/* irq number is run-time assigned */
 	},
 };

@@ -173,6 +173,7 @@ static void __init eukrea_cpuimx35_init(void)
 	imx35_add_imx_uart0(&uart_pdata);
 	imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
 
+	eukrea_cpuimx35_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
 	i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
 			ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
 	imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);

arch/arm/mach-imx/mach-mx27_3ds.c +2 -1

index 18f3581..0b0d9f0 100644
@@ -356,7 +356,7 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
 		.bus_num	= 1,
 		.chip_select	= 0, /* SS0 */
 		.platform_data	= &mc13783_pdata,
-		.irq = IMX_GPIO_TO_IRQ(PMIC_INT),
+		/* irq number is run-time assigned */
 		.mode = SPI_CS_HIGH,
 	}, {
 		.modalias	= "l4f00242t03",

@@ -398,6 +398,7 @@ static void __init mx27pdk_init(void)
 
 	imx27_add_spi_imx1(&spi2_pdata);
 	imx27_add_spi_imx0(&spi1_pdata);
+	mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
 	spi_register_board_info(mx27_3ds_spi_devs,
 						ARRAY_SIZE(mx27_3ds_spi_devs));

arch/arm/mach-imx/mach-vpr200.c +2 -1

index 033257e..7b06020 100644
@@ -162,7 +162,7 @@ static struct i2c_board_info vpr200_i2c_devices[] = {
 	}, {
 		I2C_BOARD_INFO("mc13892", 0x08),
 		.platform_data = &vpr200_pmic,
-		.irq = IMX_GPIO_TO_IRQ(GPIO_PMIC_INT),
+		/* irq number is run-time assigned */
 	}
 };

@@ -299,6 +299,7 @@ static void __init vpr200_board_init(void)
 	imx35_add_mxc_nand(&vpr200_nand_board_info);
 	imx35_add_sdhci_esdhc_imx(0, NULL);
 
+	vpr200_i2c_devices[1].irq = gpio_to_irq(GPIO_PMIC_INT);
 	i2c_register_board_info(0, vpr200_i2c_devices,
 			ARRAY_SIZE(vpr200_i2c_devices));

arch/arm/mach-mx5/board-cpuimx51.c +8 -4

index 944025d..156a692 100644
@@ -54,7 +54,7 @@
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
-		.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTA_GPIO),
+		/* irq number is run-time assigned */
 		.irqflags = IRQF_TRIGGER_HIGH,
 		.uartclk = CPUIMX51_QUART_XTAL,
 		.regshift = CPUIMX51_QUART_REGSHIFT,

@@ -62,7 +62,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
 		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
 	}, {
 		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
-		.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTB_GPIO),
+		/* irq number is run-time assigned */
 		.irqflags = IRQF_TRIGGER_HIGH,
 		.uartclk = CPUIMX51_QUART_XTAL,
 		.regshift = CPUIMX51_QUART_REGSHIFT,

@@ -70,7 +70,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
 		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
 	}, {
 		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
-		.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTC_GPIO),
+		/* irq number is run-time assigned */
 		.irqflags = IRQF_TRIGGER_HIGH,
 		.uartclk = CPUIMX51_QUART_XTAL,
 		.regshift = CPUIMX51_QUART_REGSHIFT,

@@ -78,7 +78,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
 		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
 	}, {
 		.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
-		.irq = IMX_GPIO_TO_IRQ(CPUIMX51_QUARTD_GPIO),
+		/* irq number is run-time assigned */
 		.irqflags = IRQF_TRIGGER_HIGH,
 		.uartclk = CPUIMX51_QUART_XTAL,
 		.regshift = CPUIMX51_QUART_REGSHIFT,

@@ -260,6 +260,10 @@ static void __init eukrea_cpuimx51_init(void)
 	gpio_free(CPUIMX51_QUARTD_GPIO);
 
 	imx51_add_fec(NULL);
+	serial_platform_data[0].irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO);
+	serial_platform_data[1].irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO);
+	serial_platform_data[2].irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO);
+	serial_platform_data[3].irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);

arch/arm/mach-mx5/board-cpuimx51sd.c +4 -2

index 9fbe923..674fd10 100644
@@ -126,7 +126,7 @@ static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
 		I2C_BOARD_INFO("tsc2007", 0x49),
 		.type		= "tsc2007",
 		.platform_data	= &tsc2007_info,
-		.irq		= IMX_GPIO_TO_IRQ(TSC2007_IRQGPIO),
+		/* irq number is run-time assigned */
 	},
 };

@@ -242,7 +242,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
 		.mode		= SPI_MODE_0,
 		.chip_select     = 0,
 		.platform_data   = &mcp251x_info,
-		.irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
+		/* irq number is run-time assigned */
 	},
 };

@@ -288,6 +288,7 @@ static void __init eukrea_cpuimx51sd_init(void)
 	msleep(20);
 	gpio_set_value(CAN_RST, 1);
 	imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
+	cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
 	spi_register_board_info(cpuimx51sd_spi_device,
 				ARRAY_SIZE(cpuimx51sd_spi_device));

@@ -295,6 +296,7 @@ static void __init eukrea_cpuimx51sd_init(void)
 	gpio_direction_input(TSC2007_IRQGPIO);
 	gpio_free(TSC2007_IRQGPIO);
 
+	eukrea_cpuimx51sd_i2c_devices[1].irq = gpio_to_irq(TSC2007_IRQGPIO);
 	i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
 			ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

arch/arm/mach-mx5/board-mx53_ard.c +3 -2

index 5f224f1..4a24765 100644
@@ -134,8 +134,7 @@ static struct resource ard_smsc911x_resources[] = {
 		.flags = IORESOURCE_MEM,
 	},
 	{
-		.start =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
-		.end =  IMX_GPIO_TO_IRQ(ARD_ETHERNET_INT_B),
+		/* irq number is run-time assigned */
 		.flags = IORESOURCE_IRQ,
 	},
 };

@@ -231,6 +230,8 @@ static void __init mx53_ard_board_init(void)
 
 	imx53_ard_common_init();
 	mx53_ard_io_init();
+	ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
+	ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);

arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c +2 -1

index a6a3ab8..2e686f2 100644
@@ -159,7 +159,7 @@ struct tsc2007_platform_data tsc2007_data = {
 static struct i2c_board_info mbimx51_i2c_devices[] = {
 	{
 		I2C_BOARD_INFO("tsc2007", 0x49),
-		.irq  = IMX_GPIO_TO_IRQ(MBIMX51_TSC2007_GPIO),
+		/* irq number is run-time assigned */
 		.platform_data = &tsc2007_data,
 	}, {
 		I2C_BOARD_INFO("tlv320aic23", 0x1a),

@@ -198,6 +198,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
 	gpio_direction_input(MBIMX51_TSC2007_GPIO);
 	irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
 					IRQF_TRIGGER_FALLING);
+	mbimx51_i2c_devices[0].irq = gpio_to_irq(MBIMX51_TSC2007_GPIO);
 	i2c_register_board_info(1, mbimx51_i2c_devices,
 				ARRAY_SIZE(mbimx51_i2c_devices));

arch/arm/mach-mx5/mx51_efika.c +2 -1

index ec6ca91..ee870c4 100644
@@ -587,7 +587,7 @@ static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
 		.bus_num = 0,
 		.chip_select = 0,
 		.platform_data = &mx51_efika_mc13892_data,
-		.irq = IMX_GPIO_TO_IRQ(EFIKAMX_PMIC),
+		/* irq number is run-time assigned */
 	},
 };

@@ -620,6 +620,7 @@ void __init efika_board_common_init(void)
 
 	gpio_request(EFIKAMX_PMIC, "pmic irq");
 	gpio_direction_input(EFIKAMX_PMIC);
+	mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
 	spi_register_board_info(mx51_efika_spi_board_info,
 		ARRAY_SIZE(mx51_efika_spi_board_info));
 	imx51_add_ecspi(0, &mx51_efika_spi_pdata);

arch/arm/plat-mxc/include/mach/hardware.h +0 -2

index a599f01..f743a95 100644
@@ -131,6 +131,4 @@
 /* range e.g. GPIO_1_5 is gpio 5 under linux */
 #define IMX_GPIO_NR(bank, nr)		(((bank) - 1) * 32 + (nr))
 
-#define IMX_GPIO_TO_IRQ(gpio)	(MXC_GPIO_IRQ_START + (gpio))
-
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

Signature · 1 line

1.7.5.4

Shawn Guo

author

2012-02-11 17:14 UTC #12 lore raw

PATCH 5/8 ARM: imx: eliminate macro IOMUX_TO_IRQ()

In reply to Shawn Guo

This patch changes all the static gpio irq number assigning with IOMUX_TO_IRQ() to run-time assigning with gpio_to_irq call, and in turn eliminates the macro IOMUX_TO_IRQ().

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/mach-imx/mach-armadillo5x0.c      |   12 ++++++++----
 arch/arm/mach-imx/mach-kzm_arm11_01.c      |   20 +++++++++++++++-----
 arch/arm/mach-imx/mach-mx31_3ds.c          |   13 ++++++-------
 arch/arm/mach-imx/mach-mx31ads.c           |   14 +++++++++-----
 arch/arm/mach-imx/mach-mx31lilly.c         |   10 +++++++---
 arch/arm/mach-imx/mach-mx31lite.c          |   10 +++++++---
 arch/arm/mach-imx/mach-mx31moboard.c       |    4 +++-
 arch/arm/mach-imx/mach-pcm037.c            |   18 ++++++++++++------
 arch/arm/mach-imx/mach-qong.c              |    9 +++++----
 arch/arm/mach-imx/mx31lilly-db.c           |    5 +++--
 arch/arm/mach-imx/mx31lite-db.c            |    5 +++--
 arch/arm/plat-mxc/include/mach/iomux-mx3.h |    3 ---
 12 files changed, 78 insertions(+), 45 deletions(-)

arch/arm/mach-imx/mach-armadillo5x0.c +8 -4

index e4f426a..ad56ff0 100644
@@ -406,7 +406,8 @@ static int armadillo5x0_sdhc1_init(struct device *dev,
 	gpio_direction_input(gpio_wp);
 
 	/* When supported the trigger type have to be BOTH */
-	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
+	ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)),
+			  detect_irq,
 			  IRQF_DISABLED | IRQF_TRIGGER_FALLING,
 			  "sdhc-detect", data);

@@ -427,7 +428,7 @@ err_gpio_free:
 
 static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
 {
-	free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
+	free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK)), data);
 	gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
 	gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
 }

@@ -448,8 +449,7 @@ static struct resource armadillo5x0_smc911x_resources[] = {
 		.end	= MX31_CS3_BASE_ADDR + SZ_32M - 1,
 		.flags	= IORESOURCE_MEM,
 	}, {
-		.start	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
-		.end	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+		/* irq number is run-time assigned */
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 	},
 };

@@ -489,6 +489,10 @@ static void __init armadillo5x0_init(void)
 	mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
 			ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
+	armadillo5x0_smc911x_resources[1].start =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
+	armadillo5x0_smc911x_resources[1].end =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	imx_add_gpio_keys(&armadillo5x0_button_data);
 	imx31_add_imx_i2c1(NULL);

arch/arm/mach-imx/mach-kzm_arm11_01.c +15 -5

index fc78e80..e8b41ec 100644
@@ -71,7 +71,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.membase	= KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
 		.mapbase	= KZM_ARM11_16550,
-		.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+		/* irq number is run-time assigned */
 		.irqflags	= IRQ_TYPE_EDGE_RISING,
 		.uartclk	= 14745600,
 		.regshift	= 0,

@@ -89,8 +89,7 @@ static struct resource serial8250_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	{
-		.start	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
-		.end	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+		/* irq number is run-time assigned */
 		.flags	= IORESOURCE_IRQ,
 	},
 };

@@ -123,6 +122,13 @@ static int __init kzm_init_ext_uart(void)
 	tmp |= 0x2;
 	__raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
 
+	serial_platform_data[0].irq =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+	serial8250_resources[1].start =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+	serial8250_resources[1].end =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+
 	return platform_device_register(&serial_device);
 }
 #else

@@ -150,8 +156,7 @@ static struct resource kzm_smsc9118_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	{
-		.start	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
-		.end	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+		/* irq number is run-time assigned */
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 	},
 };

@@ -175,6 +180,11 @@ static int __init kzm_init_smsc9118(void)
 	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
 	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
 
+	kzm_smsc9118_resources[1].start =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+	kzm_smsc9118_resources[1].end =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+
 	return platform_device_register(&kzm_smsc9118_device);
 }
 #else

arch/arm/mach-imx/mach-mx31_3ds.c +6 -7

index 4d1aab1..ab56702 100644
@@ -44,9 +44,6 @@
 
 #include "devices-imx31.h"
 
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
 static int mx31_3ds_pins[] = {
 	/* UART1 */
 	MX31_PIN_CTS1__CTS1,

@@ -312,7 +309,7 @@ static int mx31_3ds_sdhc1_init(struct device *dev,
 		return ret;
 	}
 
-	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+	ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)),
 			  detect_irq, IRQF_DISABLED |
 			  IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
 			  "sdhc1-detect", data);

@@ -331,7 +328,7 @@ gpio_free:
 
 static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
 {
-	free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
+	free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)), data);
 	gpio_free_array(mx31_3ds_sdhc1_gpios,
 			 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
 }

@@ -523,7 +520,7 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
 		.bus_num	= 1,
 		.chip_select	= 1, /* SS2 */
 		.platform_data	= &mc13783_pdata,
-		.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+		/* irq number is run-time assigned */
 		.mode = SPI_CS_HIGH,
 	}, {
 		.modalias	= "l4f00242t03",

@@ -698,6 +695,7 @@ static void __init mx31_3ds_init(void)
 	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
 	imx31_add_spi_imx1(&spi1_pdata);
+	mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
 	spi_register_board_info(mx31_3ds_spi_devs,
 						ARRAY_SIZE(mx31_3ds_spi_devs));

@@ -720,7 +718,8 @@ static void __init mx31_3ds_init(void)
 	if (!otg_mode_host)
 		imx31_add_fsl_usb2_udc(&usbotg_pdata);
 
-	if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+	if (mxc_expio_init(MX31_CS5_BASE_ADDR,
+			   gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1))))
 		printk(KERN_WARNING "Init of the debug board failed, all "
 				    "devices on the debug board are unusable.\n");
 	imx31_add_imx2_wdt(NULL);

arch/arm/mach-imx/mach-mx31ads.c +9 -5

index 4917aab..2e878ee 100644
@@ -60,7 +60,6 @@
 #define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
 #define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
 #define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
 
 #define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)

@@ -184,7 +183,7 @@ static struct irq_chip expio_irq_chip = {
 
 static void __init mx31ads_init_expio(void)
 {
-	int i;
+	int i, irq;
 
 	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");

@@ -201,8 +200,9 @@ static void __init mx31ads_init_expio(void)
 		irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
 		set_irq_flags(i, IRQF_VALID);
 	}
-	irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
-	irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
+	irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_4));
+	irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+	irq_set_chained_handler(irq, mx31ads_expio_irq_handler);
 }
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1

@@ -463,13 +463,17 @@ static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
 	{
 		I2C_BOARD_INFO("wm8350", 0x1a),
 		.platform_data = &mx31_wm8350_pdata,
-		.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+		/* irq number is run-time assigned */
 	},
 #endif
 };
 
 static void __init mxc_init_i2c(void)
 {
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+	mx31ads_i2c1_devices[0].irq =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+#endif
 	i2c_register_board_info(1, mx31ads_i2c1_devices,
 				ARRAY_SIZE(mx31ads_i2c1_devices));

arch/arm/mach-imx/mach-mx31lilly.c +7 -3

index 02401bb..2ba43aa 100644
@@ -63,8 +63,7 @@ static struct resource smsc91x_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	{
-		.start	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
-		.end	= IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+		/* irq number is run-time assigned */
 		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
 	}
 };

@@ -231,7 +230,7 @@ static struct spi_board_info mc13783_dev __initdata = {
 	.bus_num	= 1,
 	.chip_select	= 0,
 	.platform_data	= &mc13783_pdata,
-	.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+	/* irq number is run-time assigned */
 };
 
 static struct platform_device *devices[] __initdata = {

@@ -278,8 +277,13 @@ static void __init mx31lilly_board_init(void)
 
 	imx31_add_spi_imx0(&spi0_pdata);
 	imx31_add_spi_imx1(&spi1_pdata);
+	mc13783_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
 	spi_register_board_info(&mc13783_dev, 1);
 
+	smsc91x_resources[1].start =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
+	smsc91x_resources[1].end =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_0));
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	/* USB */

arch/arm/mach-imx/mach-mx31lite.c +7 -3

index ef80751..8adb1fc 100644
@@ -81,8 +81,7 @@ static struct resource smsc911x_resources[] = {
 		.end		= MX31_CS4_BASE_ADDR + 0x100,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= IOMUX_TO_IRQ(MX31_PIN_SFS6),
-		.end		= IOMUX_TO_IRQ(MX31_PIN_SFS6),
+		/* irq number is run-time assigned */
 		.flags		= IORESOURCE_IRQ,
 	},
 };

@@ -122,7 +121,7 @@ static struct spi_board_info mc13783_spi_dev __initdata = {
 	.bus_num	= 1,
 	.chip_select    = 0,
 	.platform_data  = &mc13783_pdata,
-	.irq		= IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+	/* irq number is run-time assigned */
 };
 
 /*

@@ -251,6 +250,7 @@ static void __init mx31lite_init(void)
 	imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
 	imx31_add_spi_imx1(&spi1_pdata);
+	mc13783_spi_dev.irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
 	spi_register_board_info(&mc13783_spi_dev, 1);
 
 	/* USB */

@@ -265,6 +265,10 @@ static void __init mx31lite_init(void)
 		pr_warning("could not get LAN irq gpio\n");
 	else {
 		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+		smsc911x_resources[1].start =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+		smsc911x_resources[1].end =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SFS6));
 		platform_device_register(&smsc911x_device);
 	}
 }

arch/arm/mach-imx/mach-mx31moboard.c +3 -1

index f225262..4ff84c0 100644
@@ -289,7 +289,7 @@ static struct mc13xxx_platform_data moboard_pmic = {
 static struct spi_board_info moboard_spi_board_info[] __initdata = {
 	{
 		.modalias = "mc13783",
-		.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+		/* irq number is run-time assigned */
 		.max_speed_hz = 300000,
 		.bus_num = 1,
 		.chip_select = 0,

@@ -541,6 +541,8 @@ static void __init mx31moboard_init(void)
 
 	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
 	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+	moboard_spi_board_info[0].irq =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
 	spi_register_board_info(moboard_spi_board_info,
 		ARRAY_SIZE(moboard_spi_board_info));

arch/arm/mach-imx/mach-pcm037.c +12 -6

index e48854b..92dc17c 100644
@@ -223,8 +223,7 @@ static struct resource smsc911x_resources[] = {
 		.end		= MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
 		.flags		= IORESOURCE_MEM,
 	}, {
-		.start		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
-		.end		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+		/* irq number is run-time assigned */
 		.flags		= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 	},
 };

@@ -369,7 +368,7 @@ static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 	gpio_direction_input(SDHC1_GPIO_WP);
 #endif
 
-	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
+	ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), detect_irq,
 			IRQF_DISABLED | IRQF_TRIGGER_FALLING,
 				"sdhc-detect", data);
 	if (ret)

@@ -389,7 +388,7 @@ err_gpio_free:
 
 static void pcm970_sdhc1_exit(struct device *dev, void *data)
 {
-	free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
+	free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_SCK6)), data);
 	gpio_free(SDHC1_GPIO_DET);
 	gpio_free(SDHC1_GPIO_WP);
 }

@@ -509,8 +508,7 @@ static struct resource pcm970_sja1000_resources[] = {
 		.end     = MX31_CS5_BASE_ADDR + 0x100 - 1,
 		.flags   = IORESOURCE_MEM,
 	}, {
-		.start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
-		.end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+		/* irq number is run-time assigned */
 		.flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };

@@ -624,6 +622,10 @@ static void __init pcm037_init(void)
 		pr_warning("could not get LAN irq gpio\n");
 	else {
 		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+		smsc911x_resources[1].start =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+		smsc911x_resources[1].end =
+			gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
 		platform_device_register(&pcm037_eth);
 	}

@@ -650,6 +652,10 @@ static void __init pcm037_init(void)
 
 	pcm037_init_camera();
 
+	pcm970_sja1000_resources[1].start =
+			gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
+	pcm970_sja1000_resources[1].end =
+			gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
 	platform_device_register(&pcm970_sja1000);
 
 	if (otg_mode_host) {

arch/arm/mach-imx/mach-qong.c +5 -4

index 2606210..b6f11d2 100644
@@ -51,8 +51,6 @@
 	(QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
 #define QONG_DNET_SIZE		0x00001000
 
-#define QONG_FPGA_IRQ		IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
-
 static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };

@@ -78,8 +76,7 @@ static struct resource dnet_resources[] = {
 		.end	= QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
 		.flags	= IORESOURCE_MEM,
 	}, {
-		.start	= QONG_FPGA_IRQ,
-		.end	= QONG_FPGA_IRQ,
+		/* irq number is run-time assigned */
 		.flags	= IORESOURCE_IRQ,
 	},
 };

@@ -95,6 +92,10 @@ static int __init qong_init_dnet(void)
 {
 	int ret;
 
+	dnet_resources[1].start =
+		gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
+	dnet_resources[1].end =
+		gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1));
 	ret = platform_device_register(&dnet_device);
 	return ret;
 }

arch/arm/mach-imx/mx31lilly-db.c +3 -2

index 7d26f76..2df625b 100644
@@ -130,7 +130,8 @@ static int mxc_mmc1_init(struct device *dev,
 	gpio_direction_input(gpio_det);
 	gpio_direction_input(gpio_wp);
 
-	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
+	ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)),
+			  detect_irq,
 			  IRQF_DISABLED | IRQF_TRIGGER_FALLING,
 			  "MMC detect", data);
 	if (ret)

@@ -151,7 +152,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
 {
 	gpio_free(gpio_det);
 	gpio_free(gpio_wp);
-	free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
+	free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1)), data);
 }
 
 static const struct imxmmc_platform_data mmc_pdata __initconst = {

arch/arm/mach-imx/mx31lite-db.c +3 -2

index bf0fb87..d639391 100644
@@ -116,7 +116,8 @@ static int mxc_mmc1_init(struct device *dev,
 	gpio_direction_input(gpio_det);
 	gpio_direction_input(gpio_wp);
 
-	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
+	ret = request_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)),
+			  detect_irq,
 			  IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
 			  "MMC detect", data);
 	if (ret)

@@ -137,7 +138,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
 {
 	gpio_free(gpio_det);
 	gpio_free(gpio_wp);
-	free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
+	free_irq(gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)), data);
 }
 
 static const struct imxmmc_platform_data mmc_pdata __initconst = {

arch/arm/plat-mxc/include/mach/iomux-mx3.h +0 -3

index 63f22a0..d8b65b5 100644
@@ -160,9 +160,6 @@ int mxc_iomux_mode(unsigned int pin_mode);
 
 #define IOMUX_TO_GPIO(iomux_pin) \
 	((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
-#define IOMUX_TO_IRQ(iomux_pin) \
-	(((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
-	MXC_GPIO_IRQ_START)
 
 /*
  * This enumeration is constructed based on the Section

Signature · 1 line

1.7.5.4

Shawn Guo

author

2012-02-11 17:14 UTC #13 lore raw

PATCH 6/8 ARM: imx: eliminate macro IRQ_GPIOx()

In reply to Shawn Guo

This patch changes all the static gpio irq number assigning with IRQ_GPIOA() ... IRQ_GPIOF() to run-time assigning with gpio_to_irq call, and in turn eliminates these macros.

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c |    3 ++-
 arch/arm/mach-imx/mach-apf9328.c             |    6 ++++--
 arch/arm/mach-imx/mach-cpuimx27.c            |   12 ++++++++----
 arch/arm/mach-imx/mach-imx27_visstrim_m10.c  |    8 ++++----
 arch/arm/mach-imx/mach-mx21ads.c             |    5 ++---
 arch/arm/mach-imx/mach-mx27ads.c             |   12 ++++++------
 arch/arm/mach-imx/mach-mxt_td60.c            |    6 +++---
 arch/arm/mach-imx/mach-pca100.c              |    4 ++--
 arch/arm/mach-imx/mach-pcm038.c              |    4 +++-
 arch/arm/mach-imx/mach-scb9328.c             |    6 ++++--
 arch/arm/mach-imx/pcm970-baseboard.c         |   13 +++++++------
 arch/arm/plat-mxc/include/mach/iomux-v1.h    |   12 ++++++------
 12 files changed, 51 insertions(+), 40 deletions(-)

arch/arm/mach-imx/eukrea_mbimx27-baseboard.c +2 -1

index 5db3e14..420ef06 100644
@@ -267,7 +267,7 @@ static struct spi_board_info __maybe_unused
 		.bus_num	= 0,
 		.chip_select	= 0,
 		.max_speed_hz	= 1500000,
-		.irq		= IRQ_GPIOD(25),
+		/* irq number is run-time assigned */
 		.platform_data	= &ads7846_config,
 		.mode           = SPI_MODE_2,
 	},

@@ -349,6 +349,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	/* SPI_CS0 init */
 	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
 	imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
+	eukrea_mbimx27_spi_board_info[0].irq = gpio_to_irq(IMX_GPIOD(25));
 	spi_register_board_info(eukrea_mbimx27_spi_board_info,
 			ARRAY_SIZE(eukrea_mbimx27_spi_board_info));

arch/arm/mach-imx/mach-apf9328.c +4 -2

index f4a63ee..1265b33 100644
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/dm9000.h>
+#include <linux/gpio.h>
 #include <linux/i2c.h>
 
 #include <asm/mach-types.h>

@@ -87,8 +88,7 @@ static struct resource dm9000_resources[] = {
 		.end    = MX1_CS4_PHYS + 0x00C00003,
 		.flags  = IORESOURCE_MEM,
 	}, {
-		.start  = IRQ_GPIOB(14),
-		.end    = IRQ_GPIOB(14),
+		/* irq number is run-time assigned */
 		.flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 	},
 };

@@ -129,6 +129,8 @@ static void __init apf9328_init(void)
 
 	imx1_add_imx_i2c(&apf9328_i2c_data);
 
+	dm9000_resources[2].start = gpio_to_irq(IMX_GPIOB(14));
+	dm9000_resources[2].end = gpio_to_irq(IMX_GPIOB(14));
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 }

arch/arm/mach-imx/mach-cpuimx27.c +8 -4

index d085aea..5c3792c 100644
@@ -169,28 +169,28 @@ static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
 static struct plat_serial8250_port serial_platform_data[] = {
 	{
 		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x200000),
-		.irq = IRQ_GPIOB(23),
+		/* irq number is run-time assigned */
 		.uartclk = 14745600,
 		.regshift = 1,
 		.iotype = UPIO_MEM,
 		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
 	}, {
 		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x400000),
-		.irq = IRQ_GPIOB(22),
+		/* irq number is run-time assigned */
 		.uartclk = 14745600,
 		.regshift = 1,
 		.iotype = UPIO_MEM,
 		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
 	}, {
 		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x800000),
-		.irq = IRQ_GPIOB(27),
+		/* irq number is run-time assigned */
 		.uartclk = 14745600,
 		.regshift = 1,
 		.iotype = UPIO_MEM,
 		.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
 	}, {
 		.mapbase = (unsigned long)(MX27_CS3_BASE_ADDR + 0x1000000),
-		.irq = IRQ_GPIOB(30),
+		/* irq number is run-time assigned */
 		.uartclk = 14745600,
 		.regshift = 1,
 		.iotype = UPIO_MEM,

@@ -279,6 +279,10 @@ static void __init eukrea_cpuimx27_init(void)
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+	serial_platform_data[0].irq = IMX_GPIOB(23);
+	serial_platform_data[1].irq = IMX_GPIOB(22);
+	serial_platform_data[2].irq = IMX_GPIOB(27);
+	serial_platform_data[3].irq = IMX_GPIOB(30);
 	platform_device_register(&serial_device);
 #endif

arch/arm/mach-imx/mach-imx27_visstrim_m10.c +4 -4

index c2766ae..603ee9a 100644
@@ -40,7 +40,7 @@
 #include "devices-imx27.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
-#define SDHC1_IRQ IRQ_GPIOB(25)
+#define SDHC1_IRQ_GPIO IMX_GPIOB(25)
 
 static const int visstrim_m10_pins[] __initconst = {
 	/* UART1 (console) */

@@ -142,14 +142,14 @@ static int visstrim_m10_sdhc1_init(struct device *dev,
 {
 	int ret;
 
-	ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
-				"mmc-detect", data);
+	ret = request_irq(gpio_to_irq(SDHC1_IRQ_GPIO), detect_irq,
+			  IRQF_TRIGGER_FALLING, "mmc-detect", data);
 	return ret;
 }
 
 static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
 {
-	free_irq(SDHC1_IRQ, data);
+	free_irq(gpio_to_irq(SDHC1_IRQ_GPIO), data);
 }
 
 static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {

arch/arm/mach-imx/mach-mx21ads.c +2 -3

index 8d9f955..a3bce99 100644
@@ -37,7 +37,6 @@
 #define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
 		(MX21ADS_MMIO_BASE_ADDR + (offset))
 
-#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
 #define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
 #define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
 #define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)

@@ -229,13 +228,13 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
 	void *data)
 {
-	return request_irq(IRQ_GPIOD(25), detect_irq,
+	return request_irq(gpio_to_irq(IMX_GPIOD(25)), detect_irq,
 		IRQF_TRIGGER_FALLING, "mmc-detect", data);
 }
 
 static void mx21ads_sdhc_exit(struct device *dev, void *data)
 {
-	free_irq(IRQ_GPIOD(25), data);
+	free_irq(gpio_to_irq(IMX_GPIOD(25)), data);
 }
 
 static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {

arch/arm/mach-imx/mach-mx27ads.c +6 -6

index 0228d2e..9be8e50 100644
@@ -246,25 +246,25 @@ static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
 static int mx27ads_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 			      void *data)
 {
-	return request_irq(IRQ_GPIOE(21), detect_irq, IRQF_TRIGGER_RISING,
-			   "sdhc1-card-detect", data);
+	return request_irq(gpio_to_irq(IMX_GPIOE(21)), detect_irq,
+			   IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
 }
 
 static int mx27ads_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 			      void *data)
 {
-	return request_irq(IRQ_GPIOB(7), detect_irq, IRQF_TRIGGER_RISING,
-			   "sdhc2-card-detect", data);
+	return request_irq(gpio_to_irq(IMX_GPIOB(7)), detect_irq,
+			   IRQF_TRIGGER_RISING, "sdhc2-card-detect", data);
 }
 
 static void mx27ads_sdhc1_exit(struct device *dev, void *data)
 {
-	free_irq(IRQ_GPIOE(21), data);
+	free_irq(gpio_to_irq(IMX_GPIOE(21)), data);
 }
 
 static void mx27ads_sdhc2_exit(struct device *dev, void *data)
 {
-	free_irq(IRQ_GPIOB(7), data);
+	free_irq(gpio_to_irq(IMX_GPIOB(7)), data);
 }
 
 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {

arch/arm/mach-imx/mach-mxt_td60.c +3 -3

index 8b3d3f0..45e63ec 100644
@@ -213,13 +213,13 @@ static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
 static int mxt_td60_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
 				void *data)
 {
-	return request_irq(IRQ_GPIOF(8), detect_irq, IRQF_TRIGGER_FALLING,
-				"sdhc1-card-detect", data);
+	return request_irq(gpio_to_irq(IMX_GPIOF(8)), detect_irq,
+			   IRQF_TRIGGER_FALLING, "sdhc1-card-detect", data);
 }
 
 static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
 {
-	free_irq(IRQ_GPIOF(8), data);
+	free_irq(gpio_to_irq(IMX_GPIOF(8)), data);
 }
 
 static const struct imxmmc_platform_data sdhc1_pdata __initconst = {

arch/arm/mach-imx/mach-pca100.c +2 -2

index d3b9c6b..8cd7c6f 100644
@@ -246,7 +246,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 {
 	int ret;
 
-	ret = request_irq(IRQ_GPIOC(29), detect_irq,
+	ret = request_irq(gpio_to_irq(IMX_GPIOC(29)), detect_irq,
 			  IRQF_DISABLED | IRQF_TRIGGER_FALLING,
 			  "imx-mmc-detect", data);
 	if (ret)

@@ -258,7 +258,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
 
 static void pca100_sdhc2_exit(struct device *dev, void *data)
 {
-	free_irq(IRQ_GPIOC(29), data);
+	free_irq(gpio_to_irq(IMX_GPIOC(29)), data);
 }
 
 static const struct imxmmc_platform_data sdhc_pdata __initconst = {

arch/arm/mach-imx/mach-pcm038.c +3 -1

index 16f126d..3255d7b 100644
@@ -27,6 +27,7 @@
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>

@@ -274,7 +275,7 @@ static struct mc13xxx_platform_data pcm038_pmic = {
 static struct spi_board_info pcm038_spi_board_info[] __initdata = {
 	{
 		.modalias = "mc13783",
-		.irq = IRQ_GPIOB(23),
+		/* irq number is run-time assigned */
 		.max_speed_hz = 300000,
 		.bus_num = 0,
 		.chip_select = 0,

@@ -325,6 +326,7 @@ static void __init pcm038_init(void)
 	mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
 
 	imx27_add_spi_imx0(&pcm038_spi0_data);
+	pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIOB(23));
 	spi_register_board_info(pcm038_spi_board_info,
 				ARRAY_SIZE(pcm038_spi_board_info));

arch/arm/mach-imx/mach-scb9328.c +4 -2

index cb9ceae..3c94228 100644
@@ -14,6 +14,7 @@
 #include <linux/mtd/physmap.h>
 #include <linux/interrupt.h>
 #include <linux/dm9000.h>
+#include <linux/gpio.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>

@@ -78,8 +79,7 @@ static struct resource dm9000x_resources[] = {
 		.end	= MX1_CS5_PHYS + 5,
 		.flags	= IORESOURCE_MEM,	/* data access */
 	}, {
-		.start	= IRQ_GPIOC(3),
-		.end	= IRQ_GPIOC(3),
+		/* irq number is run-time assigned */
 		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 	},
 };

@@ -123,6 +123,8 @@ static void __init scb9328_init(void)
 	imx1_add_imx_uart0(&uart_pdata);
 
 	printk(KERN_INFO"Scb9328: Adding devices\n");
+	dm9000x_resources[2].start = gpio_to_irq(IMX_GPIOC(3));
+	dm9000x_resources[2].end = gpio_to_irq(IMX_GPIOC(3));
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 }

arch/arm/mach-imx/pcm970-baseboard.c +7 -6

index 99afbc3..8ca349e 100644
@@ -95,14 +95,14 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
 {
 	int ret;
 
-	ret = request_irq(IRQ_GPIOC(29), detect_irq, IRQF_TRIGGER_FALLING,
-				"imx-mmc-detect", data);
+	ret = request_irq(gpio_to_irq(IMX_GPIOC(29)), detect_irq,
+			  IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
 	if (ret)
 		return ret;
 
 	ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
 	if (ret) {
-		free_irq(IRQ_GPIOC(29), data);
+		free_irq(gpio_to_irq(IMX_GPIOC(29)), data);
 		return ret;
 	}

@@ -113,7 +113,7 @@ static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void
 
 static void pcm970_sdhc2_exit(struct device *dev, void *data)
 {
-	free_irq(IRQ_GPIOC(29), data);
+	free_irq(gpio_to_irq(IMX_GPIOC(29)), data);
 	gpio_free(GPIO_PORTC + 28);
 }

@@ -192,8 +192,7 @@ static struct resource pcm970_sja1000_resources[] = {
 		.end     = MX27_CS4_BASE_ADDR + 0x100 - 1,
 		.flags   = IORESOURCE_MEM,
 	}, {
-		.start   = IRQ_GPIOE(19),
-		.end     = IRQ_GPIOE(19),
+		/* irq number is run-time assigned */
 		.flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 	},
 };

@@ -227,5 +226,7 @@ void __init pcm970_baseboard_init(void)
 	imx27_add_imx_fb(&pcm038_fb_data);
 	mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
 	imx27_add_mxc_mmc(1, &sdhc_pdata);
+	pcm970_sja1000_resources[1].start = gpio_to_irq(IMX_GPIOE(19));
+	pcm970_sja1000_resources[1].end = gpio_to_irq(IMX_GPIOE(19));
 	platform_device_register(&pcm970_sja1000);
 }

arch/arm/plat-mxc/include/mach/iomux-v1.h +6 -6

index 6fa8a70..2820341 100644
@@ -85,12 +85,12 @@
 #define GPIO_BOUT_0	(2 << GPIO_BOUT_SHIFT)
 #define GPIO_BOUT_1	(3 << GPIO_BOUT_SHIFT)
 
-#define IRQ_GPIOA(x)  (MXC_GPIO_IRQ_START + x)
-#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
-#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
-#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
-#define IRQ_GPIOE(x)  (IRQ_GPIOD(32) + x)
-#define IRQ_GPIOF(x)  (IRQ_GPIOE(32) + x)
+#define IMX_GPIOA(x)  (GPIO_PORTA + x)
+#define IMX_GPIOB(x)  (GPIO_PORTB + x)
+#define IMX_GPIOC(x)  (GPIO_PORTC + x)
+#define IMX_GPIOD(x)  (GPIO_PORTD + x)
+#define IMX_GPIOE(x)  (GPIO_PORTE + x)
+#define IMX_GPIOF(x)  (GPIO_PORTF + x)
 
 extern int mxc_gpio_mode(int gpio_mode);
 extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,

Signature · 1 line

1.7.5.4

Shawn Guo

author

2012-02-11 17:14 UTC #14 lore raw

PATCH 7/8 gpio/mxc: adopt irq_domain for gpio interrupt support

In reply to Shawn Guo

It adopts irq_domain for imx gpio interrupt support, and fixes the translation between irq and gpio number for DT users.

As the results, macro MXC_GPIO_IRQ_START is referenced nowhere in gpio-mxc driver, and the gpio irq_domain initilization in DT platform code is removed.

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/mach-imx/mach-imx6q.c |   14 ----------
 arch/arm/mach-mx5/imx51-dt.c   |   21 ---------------
 arch/arm/mach-mx5/imx53-dt.c   |   21 ---------------
 drivers/gpio/gpio-mxc.c        |   56 +++++++++++++++------------------------
 4 files changed, 22 insertions(+), 90 deletions(-)

arch/arm/mach-imx/mach-imx6q.c +0 ~~-14~~

index 6075d4d..8268471 100644
@@ -14,7 +14,6 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
-#include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>

@@ -91,21 +90,8 @@ static void __init imx6q_map_io(void)
 	imx6q_clock_map_io();
 }
 
-static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
-	gpio_irq_base -= 32;
-	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
-			      NULL);
-
-	return 0;
-}
-
 static const struct of_device_id imx6q_irq_match[] __initconst = {
 	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{ .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };

arch/arm/mach-mx5/imx51-dt.c +0 ~~-21~~

index 45abf11..6ff8bf8 100644
@@ -10,9 +10,6 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>

@@ -44,22 +41,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static int __init imx51_gpio_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
-	gpio_irq_base -= 32;
-	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-
-	return 0;
-}
-
-static const struct of_device_id imx51_irq_match[] __initconst = {
-	{ .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
-	{ /* sentinel */ }
-};
-
 static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
 	{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
 	{ /* sentinel */ }

@@ -71,8 +52,6 @@ static void __init imx51_dt_init(void)
 	const struct of_device_id *of_id;
 	void (*func)(void);
 
-	of_irq_init(imx51_irq_match);
-
 	node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
 	if (node) {
 		of_id = of_match_node(imx51_iomuxc_of_match, node);

arch/arm/mach-mx5/imx53-dt.c +0 ~~-21~~

index 52efb32..8986e32 100644
@@ -11,9 +11,6 @@
  */
 
 #include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/irqdomain.h>
-#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>

@@ -48,22 +45,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
 	{ /* sentinel */ }
 };
 
-static int __init imx53_gpio_add_irq_domain(struct device_node *np,
-				struct device_node *interrupt_parent)
-{
-	static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
-
-	gpio_irq_base -= 32;
-	irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
-
-	return 0;
-}
-
-static const struct of_device_id imx53_irq_match[] __initconst = {
-	{ .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
-	{ /* sentinel */ }
-};
-
 static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
 	{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
 	{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },

@@ -78,8 +59,6 @@ static void __init imx53_dt_init(void)
 	const struct of_device_id *of_id;
 	void (*func)(void);
 
-	of_irq_init(imx53_irq_match);
-
 	node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
 	if (node) {
 		of_id = of_match_node(imx53_iomuxc_of_match, node);

drivers/gpio/gpio-mxc.c +22 ~~-34~~

152 lines not on this page · raw message

Signature · 1 line

1.7.5.4

Shawn Guo

author

2012-02-11 17:14 UTC #15 lore raw

PATCH 8/8 ARM: imx: remove macro MXC_GPIO_IRQ_START

In reply to Shawn Guo

Now, macro MXC_GPIO_IRQ_START is referenced nowhere, so remove it.

Signed-off-by Shawn Guo <[email protected]>

---
 arch/arm/plat-mxc/include/mach/irqs.h |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

arch/arm/plat-mxc/include/mach/irqs.h +0 -2

index fd9efb0..612fcf1 100644
@@ -28,8 +28,6 @@
 #define MXC_INTERNAL_IRQS	64
 #endif
 
-#define MXC_GPIO_IRQ_START	MXC_INTERNAL_IRQS
-
 /*
  * The next 16 interrupts are for board specific purposes.  Since
  * the kernel can only run on one machine at a time, we can re-use

Signature · 1 line

1.7.5.4