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at91: modified NAND flash timing on meesc board

PATCH New Daniel Gorsulowski 2 participants 4 messages Jan 25, 2012 – Feb 20, 2012

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Daniel Gorsulowski

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#0 lore raw

PATCH 1/2 at91: modified NAND flash timing on meesc board

Signed-off-by Daniel Gorsulowski <[email protected]>
---
 board/esd/meesc/meesc.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)
board/esd/meesc/meesc.c +4 -4
index 4882ffc..9dd4375 100644
@@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void)
 	writel(csa, &matrix->csa[0]);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
-		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
 		&smc->cs[3].setup);
 
 	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
 		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
 		&smc->cs[3].pulse);
 
-	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
 		&smc->cs[3].cycle);
 	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
 		AT91_SMC_MODE_EXNW_DISABLE |
 		AT91_SMC_MODE_DBW_8 |
-		AT91_SMC_MODE_TDF_CYCLE(3),
+		AT91_SMC_MODE_TDF_CYCLE(12),
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
Signature · 1 line
1.5.3
#1 lore raw

PATCH 1/2 at91: modified NAND flash timing on meesc board

Hi Daniel,

Le 25/01/2012 14:19, Daniel Gorsulowski a ?crit :

Quoted 24 lines
Signed-off-by Daniel Gorsulowski<[email protected]>
---
  board/esd/meesc/meesc.c |    8 ++++----
  1 files changed, 4 insertions(+), 4 deletions(-)
board/esd/meesc/meesc.c +2 -3
index 4882ffc..9dd4375 100644
@@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void)
  	writel(csa,&matrix->csa[0]);
 
  	/* Configure SMC CS3 for NAND/SmartMedia */
-	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
-		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  		&smc->cs[3].setup);
 
  	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  		&smc->cs[3].pulse);
 
-	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),

board/esd/meesc/meesc.c static void meesc_nand_hw_init(void) · line 92

Quoted 10 lines
board/esd/meesc/meesc.c +2 -1
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  		&smc->cs[3].cycle);
  	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  		AT91_SMC_MODE_EXNW_DISABLE |
  		AT91_SMC_MODE_DBW_8 |
-		AT91_SMC_MODE_TDF_CYCLE(3),
+		AT91_SMC_MODE_TDF_CYCLE(12),
  		&smc->cs[3].mode);
 
  	/* Configure RDY/BSY */

Is this (and its counterpart for otc570) a performance improvement or a bug fix?.

Amicalement,

Signature · 1 line
Albert.
author
#2 lore raw

PATCH 1/2 at91: modified NAND flash timing on meesc board

Hi Albert,

Quoted 36 lines · Albert ARIBAUD

Hi Daniel,

Le 25/01/2012 14:19, Daniel Gorsulowski a ?crit :

Quoted 33 lines
Signed-off-by Daniel Gorsulowski<[email protected]>
---
  board/esd/meesc/meesc.c |    8 ++++----
  1 files changed, 4 insertions(+), 4 deletions(-)
board/esd/meesc/meesc.c +4 -4
index 4882ffc..9dd4375 100644
@@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void)
      writel(csa,&matrix->csa[0]);
 
      /* Configure SMC CS3 for NAND/SmartMedia */
-    writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
-        AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+    writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+        AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
          &smc->cs[3].setup);
 
      writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
          AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
          &smc->cs[3].pulse);
 
-    writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+    writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
          &smc->cs[3].cycle);
      writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
          AT91_SMC_MODE_EXNW_DISABLE |
          AT91_SMC_MODE_DBW_8 |
-        AT91_SMC_MODE_TDF_CYCLE(3),
+        AT91_SMC_MODE_TDF_CYCLE(12),
          &smc->cs[3].mode);
Quoted 4 lines

board/esd/meesc/meesc.c static void meesc_nand_hw_init(void) · line 92

Quoted 1 line
board/esd/meesc/meesc.c +0 -0
      /* Configure RDY/BSY */

Is this (and its counterpart for otc570) a performance improvement or a bug fix?.

There were problems with a new batch of NAND flashes in our production process. We figured out, that the NAND timing is too fast. So I would call this a bug fix.

Quoted 4 lines

Amicalement,
--
Albert.

Kind regards,
Daniel Gorsulowski

#3 lore raw

PATCH 1/2 at91: modified NAND flash timing on meesc board

In reply to Daniel Gorsulowski

Hi Daniel,

Le 25/01/2012 14:19, Daniel Gorsulowski a ?crit :

Quoted 24 lines
Signed-off-by Daniel Gorsulowski<[email protected]>
---
  board/esd/meesc/meesc.c |    8 ++++----
  1 files changed, 4 insertions(+), 4 deletions(-)
board/esd/meesc/meesc.c +2 -3
index 4882ffc..9dd4375 100644
@@ -73,20 +73,20 @@ static void meesc_nand_hw_init(void)
  	writel(csa,&matrix->csa[0]);
 
  	/* Configure SMC CS3 for NAND/SmartMedia */
-	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
-		AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+		AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  		&smc->cs[3].setup);
 
  	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  		AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  		&smc->cs[3].pulse);
 
-	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),

board/esd/meesc/meesc.c static void meesc_nand_hw_init(void) · line 92

Quoted 10 lines
board/esd/meesc/meesc.c +2 -1
+	writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  		&smc->cs[3].cycle);
  	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  		AT91_SMC_MODE_EXNW_DISABLE |
  		AT91_SMC_MODE_DBW_8 |
-		AT91_SMC_MODE_TDF_CYCLE(3),
+		AT91_SMC_MODE_TDF_CYCLE(12),
  		&smc->cs[3].mode);
 
  	/* Configure RDY/BSY */

Considered as a bug fix, and

Applied to u-boot-arm/master, thanks.

Amicalement,

Signature · 1 line
Albert.