Change ARM926EJ-S startup code, hawkboard and calimain

PATCH New Christian Riesch 2 participants 10 messages Feb 2, 2012 – Feb 19, 2012

Subsystems (2)

Arm (32-bit) Arm/actions semi architecture

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Christian Riesch

author

2012-02-02 10:44 UTC #0 lore raw

v6 cover Change ARM926EJ-S startup code, hawkboard and calimain

Hi,

In this patchset I tried to put everything from the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html

Although this is the second version of this patchset, the version number is v6 since Sughosh's patches were already v4.

Changes since v5:
- introduced CONFIG_SYS_EXCEPTION_VECTORS_HIGH as requested by Sughosh and Heiko
- added Acked-bys and Tested-bys

Regards, Christian

Christian Riesch (5):
arm, davinci: Add lowlevel_init for SoCs other than DM644X arm, arm926ejs: Do cpu critical inits only for boards that require it arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not
defined
arm, davinci: Add support for the Calimain board from OMICRON
electronics

Sughosh Ganu (2):
arm, arm926ejs: Flush the data cache before disabling it Changes to move hawkboard to the new spl infrastructure

 MAINTAINERS                                        |    5 +
 README                                             |    6 +
 arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c    |   24 +-
 arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S     |    4 +
 arch/arm/cpu/arm926ejs/davinci/spl.c               |    4 +-
 arch/arm/cpu/arm926ejs/start.S                     |   28 ++-
 arch/arm/include/asm/arch-davinci/da850_lowlevel.h |    9 +
 board/davinci/da8xxevm/da850evm.c                  |    4 +-
 board/davinci/da8xxevm/hawkboard.c                 |   23 ++
 board/davinci/da8xxevm/hawkboard_nand_spl.c        |  115 ------
 .../{u-boot-spl.lds => u-boot-spl-da850evm.lds}    |    0
 .../davinci/da8xxevm/u-boot-spl-hawk.lds           |   22 +-
 board/enbw/enbw_cmc/enbw_cmc.c                     |   13 +-
 board/omicron/calimain/Makefile                    |   45 +++
 board/omicron/calimain/calimain.c                  |  188 ++++++++++
 boards.cfg                                         |    2 +-
 doc/README.hawkboard                               |   43 ++--
 include/configs/calimain.h                         |  363 ++++++++++++++++++++
 include/configs/cam_enc_4xx.h                      |    6 -
 include/configs/da850evm.h                         |    7 +-
 include/configs/enbw_cmc.h                         |    6 +-
 include/configs/hawkboard.h                        |   24 +-
 nand_spl/board/davinci/da8xxevm/Makefile           |  155 ---------
 23 files changed, 750 insertions(+), 346 deletions(-)
 delete mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c
 rename board/davinci/da8xxevm/{u-boot-spl.lds => u-boot-spl-da850evm.lds} (100%)
 rename nand_spl/board/davinci/da8xxevm/u-boot.lds => board/davinci/da8xxevm/u-boot-spl-hawk.lds (86%)
 create mode 100644 board/omicron/calimain/Makefile
 create mode 100644 board/omicron/calimain/calimain.c
 create mode 100644 include/configs/calimain.h
 delete mode 100644 nand_spl/board/davinci/da8xxevm/Makefile

Christian Riesch

author

2012-02-02 10:44 UTC #1 lore raw

PATCH v6 1/7 arm, davinci: Add lowlevel_init for SoCs other than DM644X

The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X.

Signed-off-by Christian Riesch <[email protected]>

Cc Tom Rini <[email protected]>

Cc Sergey Kubushyn <[email protected]>

Acked-by Heiko Schocher <[email protected]>

Tested-by Heiko Schocher <[email protected]>

---
 arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +4 -0

index 7a169b1..5b39484 100644
@@ -49,6 +49,7 @@
 
 .globl	lowlevel_init
 lowlevel_init:
+#ifdef CONFIG_SOC_DM644X
 
 	/*-------------------------------------------------------*
 	 * Mask all IRQs by setting all bits in the EINT default *

@@ -707,3 +708,6 @@ DDR2_START_ADDR:
 	.word	0x80000000
 DUMMY_VAL:
 	.word	0xa55aa55a
+#else /* CONFIG_SOC_DM644X */
+	mov pc, lr
+#endif

Signature · 1 line

1.7.0.4

Albert ARIBAUD

2012-02-19 09:07 UTC #2 lore raw

PATCH v6 1/7 arm, davinci: Add lowlevel_init for SoCs other than DM644X

Hi Christian,

Le 02/02/2012 11:44, Christian Riesch a ?crit :

Quoted 27 lines

The low level initialization code in arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for DM644X SoCs only. This patch makes the lowlevel_init function in this file a dummy function for SoCs other than DM644X.
Signed-off-by Christian Riesch<[email protected]>
Cc Tom Rini<[email protected]>
Cc Sergey Kubushyn<[email protected]>
Acked-by Heiko Schocher<[email protected]>
Tested-by Heiko Schocher<[email protected]>
---
  arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S |    4 ++++
  1 files changed, 4 insertions(+), 0 deletions(-)
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +1 -0
index 7a169b1..5b39484 100644
@@ -49,6 +49,7 @@
 
  .globl	lowlevel_init
  lowlevel_init:
+#ifdef CONFIG_SOC_DM644X
 
  	/*-------------------------------------------------------*
  	 * Mask all IRQs by setting all bits in the EINT default *

arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S DDR2_START_ADDR: · line 713

Quoted 6 lines

arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S +3 -0

@@ -707,3 +708,6 @@ DDR2_START_ADDR:
  	.word	0x80000000
  DUMMY_VAL:
  	.word	0xa55aa55a
+#else /* CONFIG_SOC_DM644X */
+	mov pc, lr
+#endif

Nitpicking here, but:

I don't link the "mov pc, lr" added in #else while it already exists in the #if part. Can we have a cleaner pair of #if/#else/#endif sections, one for code, ending right *before* the 'mov pc,lr' and one for the literals that follow it?

Amicalement,

Signature · 1 line

Albert.

Christian Riesch

author

2012-02-02 10:44 UTC #3 lore raw

PATCH v6 2/7 arm, arm926ejs: Do cpu critical inits only for boards that require it

In reply to Christian Riesch

This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416 "arm, arm926ejs: always do cpu critical inits" since it impacts all arm926ejs based configurations and caused problems, e.g., with the hawkboard.

Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines from the board configurations that need low level initialization.

Signed-off-by Christian Riesch <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Tom Rini <[email protected]>

Cc Heiko Schocher <[email protected]>

Acked-by Heiko Schocher <[email protected]>

Tested-by Heiko Schocher <[email protected]>

---
 arch/arm/cpu/arm926ejs/start.S |    6 ++++--
 include/configs/cam_enc_4xx.h  |    6 ------
 include/configs/da850evm.h     |    1 -
 include/configs/enbw_cmc.h     |    1 -
 4 files changed, 4 insertions(+), 10 deletions(-)

arch/arm/cpu/arm926ejs/start.S +4 -2

index 6a09c02..bb4d00b 100644
@@ -194,7 +194,9 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
+#endif
 
 /* Set stackpointer in internal RAM to call board_init_f */
 call_board_init_f:

@@ -353,6 +355,7 @@ _dynsym_start_ofs:
  *
  *************************************************************************
  */
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches

@@ -371,15 +374,14 @@ cpu_init_crit:
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 	mcr	p15, 0, r0, c1, c0, 0
 
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	/*
 	 * Go setup Memory and board specific bits prior to relocation.
 	 */
 	mov	ip, lr		/* perserve link reg across call */
 	bl	lowlevel_init	/* go setup pll,mux,memory */
 	mov	lr, ip		/* restore link */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 	mov	pc, lr		/* back to my caller */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
 
 #ifndef CONFIG_SPL_BUILD
 /*

include/configs/cam_enc_4xx.h +0 -6

index a21d448..f4fe444 100644
@@ -265,12 +265,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0xc0000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	0x60000
 
-/*
- * U-Boot is a 3rd stage loader and if booting with spl, cpu setup is
- * done in board_init_f from c code.
- */
-#define CONFIG_SKIP_LOWLEVEL_INIT
-
 /* for UBL header */
 #define CONFIG_SYS_UBL_BLOCK		(CONFIG_SYS_NAND_PAGE_SIZE)

include/configs/da850evm.h +0 -1

index fcbbace..f15a0a6 100644
@@ -42,7 +42,6 @@
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ			1000
-#define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
 
 /*

include/configs/enbw_cmc.h +0 -1

index c427dc7..21cf647 100644
@@ -45,7 +45,6 @@
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ			1000
-#define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_DA850_LOWLEVEL
 #define CONFIG_ARCH_CPU_INIT
 #define CONFIG_DA8XX_GPIO

Signature · 1 line

1.7.0.4

Christian Riesch

author

2012-02-02 10:44 UTC #4 lore raw

PATCH v6 3/7 arm, arm926ejs: Flush the data cache before disabling it

In reply to Christian Riesch

From: Sughosh Ganu <[email protected]>

The current implementation invalidates the data cache before turning it off and causes problems on the hawkboard. See the discussion in
http://lists.denx.de/pipermail/u-boot/2012-January/115212.html

According to the ARM926EJ-S Technical Reference Manual, the cache should be flushed instead.

Also fix the comments to match code.

Signed-off-by Sughosh Ganu <[email protected]>

Rebased and corrected commit message.

Signed-off-by Christian Riesch <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Tom Rini <[email protected]>

Acked-by Heiko Schocher <[email protected]>

Tested-by Heiko Schocher <[email protected]>

---
 arch/arm/cpu/arm926ejs/start.S |   12 ++++++++----
 1 files changed, 8 insertions(+), 4 deletions(-)

arch/arm/cpu/arm926ejs/start.S +8 -4

index bb4d00b..b39ed8a 100644
@@ -358,14 +358,18 @@ _dynsym_start_ofs:
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
-	 * flush v4 I/D caches
+	 * flush D cache before disabling it
 	 */
 	mov	r0, #0
-	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
-	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */
+flush_dcache:
+	mrc	p15, 0, r15, c7, c10, 3
+	bne	flush_dcache
+
+	mcr	p15, 0, r0, c8, c7, 0	/* invalidate TLB */
+	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I Cache */
 
 	/*
-	 * disable MMU stuff and caches
+	 * disable MMU and D cache, and enable I cache
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */

Signature · 1 line

1.7.0.4

Christian Riesch

author

2012-02-02 10:44 UTC #5 lore raw

PATCH v6 4/7 arm, arm926ejs: Add option CONFIG_SYS_EXCEPTION_VECTORS_HIGH

In reply to Christian Riesch

The V bit of the c1 register of CP15 should not be cleared on DA850 SoCs since they have no valid memory at 0x00000000. This patch introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH that allows setting the correct value for the V bit.

Signed-off-by Christian Riesch <[email protected]>

Reported-by Sughosh Ganu <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Tom Rini <[email protected]>

Cc Sughosh Ganu <[email protected]>

Cc Heiko Schocher <[email protected]>

---
 README                         |    6 ++++++
 arch/arm/cpu/arm926ejs/start.S |    7 ++++++-
 include/configs/da850evm.h     |    1 +
 include/configs/enbw_cmc.h     |    1 +
 include/configs/hawkboard.h    |    1 +
 5 files changed, 15 insertions(+), 1 deletions(-)

README +6 -0

index 9d713e8..c5b0941 100644
@@ -420,6 +420,12 @@ The following options need to be configured:
 		XWAY SoCs for booting from NOR flash. The U-Boot image needs to
 		be swapped if a flash programmer is used.
 
+- ARM options:
+		CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+
+		Select high exception vectors of the ARM core, e.g., do not
+		clear the V bit of the c1 register of CP15.
+
 - Linux Kernel Interface:
 		CONFIG_CLOCKS_IN_MHZ

arch/arm/cpu/arm926ejs/start.S +6 -1

index b39ed8a..525c112 100644
@@ -372,8 +372,13 @@ flush_dcache:
 	 * disable MMU and D cache, and enable I cache
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
-	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
+	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */
 	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
+#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
+	orr	r0, r0, #0x00002000	/* set bit 13 (--V- ----) */
+#else
+	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
+#endif
 	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
 	mcr	p15, 0, r0, c1, c0, 0

include/configs/da850evm.h +1 -0

index f15a0a6..85016df 100644
@@ -37,6 +37,7 @@
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
 #define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE

include/configs/enbw_cmc.h +1 -0

index 21cf647..0c9ab4c 100644
@@ -40,6 +40,7 @@
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
 #define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE

include/configs/hawkboard.h +1 -0

index 12acb27..ce78d3c 100644
@@ -35,6 +35,7 @@
 #define CONFIG_ARM926EJS		/* arm926ejs CPU core */
 #define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
 #define CONFIG_SOC_DA850		/* TI DA850 SoC */
+#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE

Signature · 1 line

1.7.0.4

Christian Riesch

author

2012-02-02 10:44 UTC #6 lore raw

PATCH v6 5/7 arm, arm926ejs: Enable icache only if CONFIG_SYS_ICACHE_OFF is not defined

In reply to Christian Riesch

Signed-off-by Christian Riesch <[email protected]>

Cc Albert Aribaud <[email protected]>

Cc Tom Rini <[email protected]>

Acked-by Heiko Schocher <[email protected]>

Tested-by Heiko Schocher <[email protected]>

---
 arch/arm/cpu/arm926ejs/start.S |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

arch/arm/cpu/arm926ejs/start.S +4 -1

index 525c112..6f05f1a 100644
@@ -369,7 +369,8 @@ flush_dcache:
 	mcr	p15, 0, r0, c7, c5, 0	/* invalidate I Cache */
 
 	/*
-	 * disable MMU and D cache, and enable I cache
+	 * disable MMU and D cache
+	 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
 	 */
 	mrc	p15, 0, r0, c1, c0, 0
 	bic	r0, r0, #0x00000300	/* clear bits 9:8 (---- --RS) */

@@ -380,7 +381,9 @@ flush_dcache:
 	bic	r0, r0, #0x00002000	/* clear bit 13 (--V- ----) */
 #endif
 	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
+#ifndef CONFIG_SYS_ICACHE_OFF
 	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
+#endif
 	mcr	p15, 0, r0, c1, c0, 0
 
 	/*

Signature · 1 line

1.7.0.4

Christian Riesch

author

2012-02-02 10:44 UTC #7 lore raw

PATCH v6 6/7 Changes to move hawkboard to the new spl infrastructure

In reply to Christian Riesch

From: Sughosh Ganu <[email protected]>

This patch moves hawkboard to the new spl infrastructure from the older nand_spl one.

Removed the hawkboard_nand_config build option -- The spl code now gets compiled with hawkboard_config, after building the main u-boot image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard to reflect the same.

Signed-off-by Sughosh Ganu <[email protected]>

Signed-off-by Heiko Schocher <[email protected]>

Cc Heiko Schocher <[email protected]>

Cc Christian Riesch <[email protected]>

Cc Sudhakar Rajashekhara <[email protected]>

Cc Tom Rini <[email protected]>

Acked-by Christian Riesch <[email protected]>

---
 arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c    |   24 ++-
 arch/arm/cpu/arm926ejs/davinci/spl.c               |    4 +-
 arch/arm/include/asm/arch-davinci/da850_lowlevel.h |    9 +
 board/davinci/da8xxevm/da850evm.c                  |    4 +-
 board/davinci/da8xxevm/hawkboard.c                 |   23 +++
 board/davinci/da8xxevm/hawkboard_nand_spl.c        |  115 ---------------
 .../{u-boot-spl.lds => u-boot-spl-da850evm.lds}    |    0
 .../davinci/da8xxevm/u-boot-spl-hawk.lds           |   22 ++-
 board/enbw/enbw_cmc/enbw_cmc.c                     |   13 +--
 boards.cfg                                         |    1 -
 doc/README.hawkboard                               |   43 +++---
 include/configs/da850evm.h                         |    5 +-
 include/configs/enbw_cmc.h                         |    4 +-
 include/configs/hawkboard.h                        |   23 +++-
 nand_spl/board/davinci/da8xxevm/Makefile           |  155 --------------------
 15 files changed, 114 insertions(+), 331 deletions(-)
 delete mode 100644 board/davinci/da8xxevm/hawkboard_nand_spl.c
 rename board/davinci/da8xxevm/{u-boot-spl.lds => u-boot-spl-da850evm.lds} (100%)
 rename nand_spl/board/davinci/da8xxevm/u-boot.lds => board/davinci/da8xxevm/u-boot-spl-hawk.lds (86%)
 delete mode 100644 nand_spl/board/davinci/da8xxevm/Makefile

arch/arm/cpu/arm926ejs/davinci/da850_lowlevel.c +15 -9

index eec06bc..df7d6a2 100644
@@ -32,6 +32,7 @@
 #include <asm/arch/emif_defs.h>
 #include <asm/arch/pll_defs.h>
 
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
 void da850_waitloop(unsigned long loopcnt)
 {
 	unsigned long	i;

@@ -163,7 +164,9 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 
 	return 0;
 }
+#endif /* CONFIG_SYS_DA850_PLL_INIT */
 
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
 int da850_ddr_setup(void)
 {
 	unsigned long	tmp;

@@ -242,6 +245,7 @@ int da850_ddr_setup(void)
 
 	return 0;
 }
+#endif /* CONFIG_SYS_DA850_DDR_INIT */
 
 __attribute__((weak))
 void board_gpio_init(void)

@@ -249,10 +253,6 @@ void board_gpio_init(void)
 	return;
 }
 
-/* pinmux_resource[] vector is defined in the board specific file */
-extern const struct pinmux_resource pinmuxes[];
-extern const int pinmuxes_size;
-
 int arch_cpu_init(void)
 {
 	/* Unlock kick registers */

@@ -266,13 +266,11 @@ int arch_cpu_init(void)
 	if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
 		return 1;
 
+#if defined(CONFIG_SYS_DA850_PLL_INIT)
 	/* PLL setup */
 	da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
 	da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
-
-	/* GPIO setup */
-	board_gpio_init();
-
+#endif
 	/* setup CSn config */
 #if defined(CONFIG_SYS_DA850_CS2CFG)
 	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);

@@ -281,7 +279,12 @@ int arch_cpu_init(void)
 	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
 #endif
 
-	lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
+	da8xx_configure_lpsc_items(lpsc, lpsc_size);
+
+	/* GPIO setup */
+	board_gpio_init();
+
+
 	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);

@@ -293,6 +296,9 @@ int arch_cpu_init(void)
 		DAVINCI_UART_PWREMU_MGMT_UTRST),
 	       &davinci_uart2_ctrl_regs->pwremu_mgmt);
 
+#if defined(CONFIG_SYS_DA850_DDR_INIT)
 	da850_ddr_setup();
+#endif
+
 	return 0;
 }

arch/arm/cpu/arm926ejs/davinci/spl.c +2 -2

index f475f9b..74632e5 100644
@@ -74,12 +74,12 @@ void board_init_f(ulong dummy)
 
 void board_init_r(gd_t *id, ulong dummy)
 {
-#ifdef CONFIG_SOC_DM365
+#ifdef CONFIG_SPL_NAND_LOAD
 	nand_init();
 	puts("Nand boot...\n");
 	nand_boot();
 #endif
-#ifdef CONFIG_SOC_DA8XX
+#ifdef CONFIG_SPL_SPI_LOAD
 	mem_malloc_init(CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN,
 			CONFIG_SYS_MALLOC_LEN);

arch/arm/include/asm/arch-davinci/da850_lowlevel.h +9 -0

index e489c47..11ed91d 100644
@@ -24,6 +24,15 @@
 #ifndef __DA850_LOWLEVEL_H
 #define __DA850_LOWLEVEL_H
 
+#include <asm/arch/pinmux_defs.h>
+
+/* pinmux_resource[] vector is defined in the board specific file */
+extern const struct pinmux_resource pinmuxes[];
+extern const int pinmuxes_size;
+
+extern const struct lpsc_resource lpsc[];
+extern const int lpsc_size;
+
 /* NOR Boot Configuration Word Field Descriptions */
 #define DA850_NORBOOT_COPY_XK(X)	((X - 1) << 8)
 #define DA850_NORBOOT_METHOD_DIRECT	(1 << 4)

board/davinci/da8xxevm/da850evm.c +3 -1

index 9bd3e71..34ef53d 100644
@@ -137,7 +137,7 @@ const struct pinmux_resource pinmuxes[] = {
 
 const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
 
-static const struct lpsc_resource lpsc[] = {
+const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
 	{ DAVINCI_LPSC_EMAC },	/* image download */

@@ -145,6 +145,8 @@ static const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_GPIO },
 };
 
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
 #ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
 #define CONFIG_DA850_EVM_MAX_CPU_CLK	300000000
 #endif

board/davinci/da8xxevm/hawkboard.c +23 -0

index 9d4e238..b694258 100644
@@ -27,10 +27,33 @@
 #include <asm/arch/hardware.h>
 #include <asm/io.h>
 #include <asm/arch/davinci_misc.h>
+#include <asm/arch/pinmux_defs.h>
 #include <ns16550.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
+const struct pinmux_resource pinmuxes[] = {
+	PINMUX_ITEM(emac_pins_mii),
+	PINMUX_ITEM(emac_pins_mdio),
+	PINMUX_ITEM(emifa_pins_cs3),
+	PINMUX_ITEM(emifa_pins_cs4),
+	PINMUX_ITEM(emifa_pins_nand),
+	PINMUX_ITEM(uart2_pins_txrx),
+	PINMUX_ITEM(uart2_pins_rtscts),
+};
+
+const int pinmuxes_size = ARRAY_SIZE(pinmuxes);
+
+const struct lpsc_resource lpsc[] = {
+	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
+	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
+	{ DAVINCI_LPSC_EMAC },	/* image download */
+	{ DAVINCI_LPSC_UART2 },	/* console */
+	{ DAVINCI_LPSC_GPIO },
+};
+
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
 int board_init(void)
 {
 	/* arch number of the board */

board/davinci/da8xxevm/hawkboard_nand_spl.c deleted +0 ~~-115~~

115 lines not on this page · raw message

board/davinci/da8xxevm/u-boot-spl-da850evm.lds renamed from board/davinci/da8xxevm/u-boot-spl.lds +0 -0

similarity index 100%
rename from board/davinci/da8xxevm/u-boot-spl.lds
rename to board/davinci/da8xxevm/u-boot-spl-da850evm.lds

board/davinci/da8xxevm/u-boot-spl-hawk.lds renamed from nand_spl/board/davinci/da8xxevm/u-boot.lds +13 -9

similarity index 86%
rename from nand_spl/board/davinci/da8xxevm/u-boot.lds
rename to board/davinci/da8xxevm/u-boot-spl-hawk.lds
index 638ffd9..b3a41af 100644
@@ -34,11 +34,11 @@ SECTIONS
 	. = ALIGN(4);
 	.text      :
 	{
-	  start.o	(.text)
-	  cpu.o		(.text)
-	  nand_boot.o	(.text)
+	  arch/arm/cpu/arm926ejs/start.o		(.text)
+	  arch/arm/cpu/arm926ejs/davinci/libdavinci.o	(.text)
+	  drivers/mtd/nand/libnand.o			(.text)
 
-	  *(.text)
+	  *(.text*)
 	}
 
 	. = ALIGN(4);

@@ -68,10 +68,14 @@ SECTIONS
 
 	__got_end = .;
 
-	_end = .;
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	}
 
-	. = ALIGN(4);
-	__bss_start = .;
-	.bss : { *(.bss) }
-	__bss_end__ = .;
+	_end = .;
 }

board/enbw/enbw_cmc/enbw_cmc.c +3 ~~-10~~

index 98dda1e..16d1b08 100644
@@ -49,7 +49,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct lpsc_resource lpsc[] = {
+const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_AEMIF },
 	{ DAVINCI_LPSC_SPI1 },
 	{ DAVINCI_LPSC_ARM_RAM_ROM },

@@ -65,6 +65,8 @@ static const struct lpsc_resource lpsc[] = {
 	{ DAVINCI_LPSC_USB11 },
 };
 
+const int lpsc_size = ARRAY_SIZE(lpsc);
+
 static const struct pinmux_config enbw_pins[] = {
 	{ pinmux(0), 8, 0 },
 	{ pinmux(0), 8, 1 },

@@ -549,15 +551,6 @@ void board_gpio_init(void)
 	struct davinci_gpio *gpio = davinci_gpio_bank01;
 
 	/*
-	 * Power on required peripherals
-	 * ARM does not have access by default to PSC0 and PSC1
-	 * assuming here that the DSP bootloader has set the IOPU
-	 * such that PSC access is available to ARM
-	 */
-	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
-		return;
-
-	/*
 	 * set LED (gpio Interface not usable here)
 	 * set LED pins to output and state 0
 	 */

boards.cfg +0 -1

index 7e065bf..fc782dc 100644
@@ -133,7 +133,6 @@ davinci_sffsdr               arm         arm926ejs   sffsdr              davinci
 davinci_sonata               arm         arm926ejs   sonata              davinci        davinci
 ea20			     arm	 arm926ejs   ea20		 davinci	davinci
 hawkboard                    arm         arm926ejs   da8xxevm            davinci        davinci
-hawkboard_nand               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:NAND_U_BOOT
 hawkboard_uart               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:UART_U_BOOT
 enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw           davinci
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_DISABLE_PCI

doc/README.hawkboard +21 ~~-22~~

80 lines not on this page · raw message

include/configs/da850evm.h +3 -2

index 85016df..e49a7b2 100644
@@ -44,6 +44,8 @@
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
+#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
 
 /*
  * Memory Info

@@ -142,7 +144,6 @@
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_SYS_DA850_LPSC_UART DAVINCI_LPSC_UART2
 
 #define CONFIG_SPI
 #define CONFIG_SPI_FLASH

@@ -319,7 +320,7 @@
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
-#define CONFIG_SPL_LDSCRIPT	"$(BOARDDIR)/u-boot-spl.lds"
+#define CONFIG_SPL_LDSCRIPT	"board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
 #define CONFIG_SPL_STACK	0x8001ff00
 #define CONFIG_SPL_TEXT_BASE	0x80000000
 #define CONFIG_SPL_MAX_SIZE	32768

include/configs/enbw_cmc.h +3 -1

index 0c9ab4c..e732fa8 100644
@@ -48,6 +48,8 @@
 #define CONFIG_SYS_HZ			1000
 #define CONFIG_DA850_LOWLEVEL
 #define CONFIG_ARCH_CPU_INIT
+#define CONFIG_SYS_DA850_PLL_INIT
+#define CONFIG_SYS_DA850_DDR_INIT
 #define CONFIG_DA8XX_GPIO
 #define CONFIG_HOSTNAME		enbw_cmc
 #define CONFIG_DISPLAY_CPUINFO

@@ -83,7 +85,7 @@
 #define CONFIG_CONS_INDEX	1		/* use UART0 for console */
 #define CONFIG_BAUDRATE		115200		/* Default baud rate */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-#define CONFIG_SYS_DA850_LPSC_UART	DAVINCI_LPSC_UART2
+
 /*
  * I2C Configuration
  */

include/configs/hawkboard.h +19 -4

index ce78d3c..709f155 100644
@@ -44,12 +44,29 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 
-#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_UART_U_BOOT)
+#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
+	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
+	DAVINCI_SYSCFG_SUSPSRC_I2C  |		\
+	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
+	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
+	DAVINCI_SYSCFG_SUSPSRC_UART2)
+
+#if defined(CONFIG_UART_U_BOOT)
 #define CONFIG_SYS_TEXT_BASE		0xc1080000
-#else
+#elif !defined(CONFIG_SPL_BUILD)
 #define CONFIG_SYS_TEXT_BASE		0xc1180000
 #endif
 
+/* Spl */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_LOAD
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"board/$(BOARDDIR)/u-boot-spl-hawk.lds"
+#define CONFIG_SPL_TEXT_BASE		0xc1080000
+#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
+
 /*
  * Memory Info
  */

@@ -85,9 +102,7 @@
 /*
  * Network & Ethernet Configuration
  */
-#if !defined(CONFIG_NAND_SPL)
 #define CONFIG_DRIVER_TI_EMAC
-#endif
 #define CONFIG_MII
 #define CONFIG_BOOTP_DEFAULT
 #define CONFIG_BOOTP_DNS

nand_spl/board/davinci/da8xxevm/Makefile deleted +0 ~~-155~~

155 lines not on this page · raw message

Signature · 1 line

1.7.0.4

Christian Riesch

author

2012-02-02 10:44 UTC #8 lore raw

PATCH v6 7/7 arm, davinci: Add support for the Calimain board from OMICRON electronics

In reply to Christian Riesch

This patch adds support for the Calimain board from
OMICRON electronics GmbH. The board features a Texas Instruments AM1808 SoC, 128 MB DDR2 memory, and 64 MB NOR flash memory connected to CS2 and CS3.

Signed-off-by Christian Riesch <[email protected]>

---
 MAINTAINERS                       |    5 +
 board/omicron/calimain/Makefile   |   45 +++++
 board/omicron/calimain/calimain.c |  188 +++++++++++++++++++
 boards.cfg                        |    1 +
 include/configs/calimain.h        |  363 +++++++++++++++++++++++++++++++++++++
 5 files changed, 602 insertions(+), 0 deletions(-)
 create mode 100644 board/omicron/calimain/Makefile
 create mode 100644 board/omicron/calimain/calimain.c
 create mode 100644 include/configs/calimain.h

MAINTAINERS +5 -0

index 353f23d..61f9537 100644
@@ -796,6 +796,11 @@ Thierry Reding <[email protected]>
 	plutux		Tegra2 (ARM7 & A9 Dual Core)
 	medcom		Tegra2 (ARM7 & A9 Dual Core)
 
+Christian Riesch <[email protected]>
+Manfred Rudigier <[email protected]>
+
+	calimain	ARM926EJS (AM1808 SoC)
+
 Tom Rini <[email protected]>
 
 	omap3_evm	ARM ARMV7 (OMAP3xx SoC)

board/omicron/calimain/Makefile new file +45 -0

45 lines not on this page · raw message

board/omicron/calimain/calimain.c new file +188 -0

188 lines not on this page · raw message

boards.cfg +1 -0

index fc782dc..e8269ef 100644
@@ -135,6 +135,7 @@ ea20			     arm	 arm926ejs   ea20		 davinci	davinci
 hawkboard                    arm         arm926ejs   da8xxevm            davinci        davinci
 hawkboard_uart               arm         arm926ejs   da8xxevm            davinci        davinci     hawkboard:UART_U_BOOT
 enbw_cmc                     arm         arm926ejs   enbw_cmc            enbw           davinci
+calimain                     arm         arm926ejs   calimain            omicron        davinci
 km_kirkwood                  arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_DISABLE_PCI
 km_kirkwood_pci              arm         arm926ejs   km_arm              keymile        kirkwood	km_kirkwood:KM_RECONFIG_XLX
 mgcoge3un                    arm         arm926ejs   km_arm              keymile        kirkwood

include/configs/calimain.h new file +363 -0

363 lines not on this page · raw message

Signature · 1 line

1.7.0.4

Albert ARIBAUD

2012-02-19 09:11 UTC #9 lore raw

v6 cover Change ARM926EJ-S startup code, hawkboard and calimain

In reply to Christian Riesch

Le 02/02/2012 11:44, Christian Riesch a ?crit :

Quoted 7 lines

Hi,
In this patchset I tried to put everything from the discussion in http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
Although this is the second version of this patchset, the version number is v6 since Sughosh's patches were already v4.

Note: unless there is strong opposition to this, I consider the patch original submission date to be that of Sughosh's series, i.e. before the merge window closure, and I thus intend to pull it in for 2012.03.

Amicalement,

Signature · 1 line

Albert.