Define UART4 and UART5 base addresses

PATCH New Stefano Babic 3 participants 15 messages Feb 22, 2012 – Jun 12, 2012

Subsystems (4)

Network drivers Arm (32-bit) Arm i.MX and Layerscape Block layer

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Stefano Babic

author

2012-02-22 10:24 UTC #0 lore raw

PATCH 1/9 Define UART4 and UART5 base addresses

Signed-off-by Stefano Babic <[email protected]>

---
 arch/arm/include/asm/arch-mx5/imx-regs.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

arch/arm/include/asm/arch-mx5/imx-regs.h +5 -0

index 4fa6658..07296b5 100644
@@ -93,6 +93,7 @@
 #define GPIO5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000DC000)
 #define GPIO6_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E0000)
 #define GPIO7_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000E4000)
+#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000F0000)
 #endif
 /*
  * AIPS 2

@@ -133,6 +134,10 @@
 #define VPU_BASE_ADDR		(AIPS2_BASE_ADDR + 0x000F4000)
 #define SAHARA_BASE_ADDR	(AIPS2_BASE_ADDR + 0x000F8000)
 
+#if defined(CONFIG_MX53)
+#define UART5_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00090000)
+#endif
+
 /*
  * WEIM CSnGCR1
  */

Signature · 1 line

1.7.5.4

Stefano Babic

author

2012-02-22 10:24 UTC #1 lore raw

PATCH 2/9 NET: fec_mxc.c: Add support for MII for MX5 SOCs

Signed-off-by Stefano Babic <[email protected]>

CC Fabio Estevam <[email protected]>

---
 drivers/net/fec_mxc.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

drivers/net/fec_mxc.c +5 -0

index 1fdd071..201e5d2 100644
@@ -419,8 +419,13 @@ static int fec_open(struct eth_device *edev)
 	while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
 		udelay(2);
 
+#if !defined(CONFIG_MII)
 	/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
 	writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
+#else
+	/* configure gasket for MII, no loopback, and no echo */
+	writew(MIIGSK_CFGR_IF_MODE_MII, &fec->eth->miigsk_cfgr);
+#endif
 
 	/* re-enable the gasket */
 	writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);

Signature · 1 line

1.7.5.4

Dirk Behme

2012-05-15 12:39 UTC #2 lore raw

PATCH 2/9 NET: fec_mxc.c: Add support for MII for MX5 SOCs

Quoted 14 lines · Stefano Babic

Signed-off-by Stefano Babic <[email protected]>

CC Fabio Estevam <[email protected]>

---
 drivers/net/fec_mxc.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

drivers/net/fec_mxc.c +0 -0

index 1fdd071..201e5d2 100644
@@ -419,8 +419,13 @@ static int fec_open(struct eth_device *edev)
 	while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
 		udelay(2);

drivers/net/fec_mxc.c static int fec_open(struct eth_device *edev) · line 431

Quoted 10 lines

drivers/net/fec_mxc.c +5 -0

+#if !defined(CONFIG_MII)
 	/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
 	writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
+#else
+	/* configure gasket for MII, no loopback, and no echo */
+	writew(MIIGSK_CFGR_IF_MODE_MII, &fec->eth->miigsk_cfgr);
+#endif
 
 	/* re-enable the gasket */
 	writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);

I have this patch on my list of pending patches.

What's the status of this?

Best regards

Dirk

Stefano Babic

author

2012-06-12 17:02 UTC #3 lore raw

PATCH 2/9 NET: fec_mxc.c: Add support for MII for MX5 SOCs

Quoted 4 lines · Dirk Behme

Quoted 3 lines · Stefano Babic
Signed-off-by Stefano Babic <[email protected]>
CC Fabio Estevam <[email protected]>
---

Hi Dirk,

Quoted 19 lines

 drivers/net/fec_mxc.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

drivers/net/fec_mxc.c +5 -0

index 1fdd071..201e5d2 100644
@@ -419,8 +419,13 @@ static int fec_open(struct eth_device *edev)
     while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
         udelay(2);
 
+#if !defined(CONFIG_MII)
     /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
     writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
+#else
+    /* configure gasket for MII, no loopback, and no echo */
+    writew(MIIGSK_CFGR_IF_MODE_MII, &fec->eth->miigsk_cfgr);
+#endif

Quoted 6 lines

drivers/net/fec_mxc.c static int fec_open(struct eth_device *edev) · line 431
Quoted 2 lines
drivers/net/fec_mxc.c +0 -0
     /* re-enable the gasket */
     writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
I have this patch on my list of pending patches.
What's the status of this?

This patch must be reworked. See also the discussion about Timo's patch on http://patchwork.ozlabs.org/patch/153695/

There is some confusion about how to set the interface type. At the beginning, CONFIG_MII or CONFIG_RMII was used, but after the introduction of the MX28, CONFIG_FEC_XCV_TYPE is used. This should be unified, and I tend to use CONFIG_FEC_XCV_TYPE for all i.MX

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

author

2012-02-22 10:24 UTC #4 lore raw

PATCH 3/9 NET: fec_mxc.c: Add a way to disable auto negotiation

In reply to Stefano Babic

Signed-off-by Stefano Babic <[email protected]>

CC Fabio Estevam <[email protected]>

---
 drivers/net/fec_mxc.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

drivers/net/fec_mxc.c +3 -1

index 201e5d2..a45ac3f 100644
@@ -175,9 +175,10 @@ int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, int regAddr,
 #ifndef CONFIG_PHYLIB
 static int miiphy_restart_aneg(struct eth_device *dev)
 {
+	int ret = 0;
+#if !defined(CONFIG_FEC_MXC_NO_ANEG)
 	struct fec_priv *fec = (struct fec_priv *)dev->priv;
 	struct ethernet_regs *eth = fec->bus->priv;
-	int ret = 0;
 
 	/*
 	 * Wake up from sleep if necessary

@@ -201,6 +202,7 @@ static int miiphy_restart_aneg(struct eth_device *dev)
 	if (fec->mii_postcall)
 		ret = fec->mii_postcall(fec->phy_id);
 
+#endif
 	return ret;
 }

Signature · 1 line

1.7.5.4

Stefano Babic

author

2012-02-22 10:24 UTC #5 lore raw

PATCH 4/9 MX5: Add definitions for SATA controller

In reply to Stefano Babic

Add base address and MXC_SATA_CLK to return the clock used for the SATA controller.

Signed-off-by Stefano Babic <[email protected]>

CC Fabio Estevam <[email protected]>

CC Dirk Behme <[email protected]>

---
 arch/arm/cpu/armv7/mx5/clock.c           |    2 ++
 arch/arm/include/asm/arch-mx5/clock.h    |    1 +
 arch/arm/include/asm/arch-mx5/imx-regs.h |    1 +
 3 files changed, 4 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/mx5/clock.c +2 -0

index e92f106..8f8d01c 100644
@@ -380,6 +380,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_FEC_CLK:
 		return decode_pll(mxc_plls[PLL1_CLOCK],
 				    CONFIG_SYS_MX5_HCLK);
+	case MXC_SATA_CLK:
+		return get_ahb_clk();
 	default:
 		break;
 	}

arch/arm/include/asm/arch-mx5/clock.h +1 -0

index ea972a3..f9f82f3 100644
@@ -32,6 +32,7 @@ enum mxc_clock {
 	MXC_UART_CLK,
 	MXC_CSPI_CLK,
 	MXC_FEC_CLK,
+	MXC_SATA_CLK,
 };
 
 unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref);

arch/arm/include/asm/arch-mx5/imx-regs.h +1 -0

index 07296b5..a4245a3 100644
@@ -43,6 +43,7 @@
 #define NFC_BASE_ADDR_AXI       0xF7FF0000
 #define IRAM_BASE_ADDR          0xF8000000
 #define CS1_BASE_ADDR           0xF4000000
+#define SATA_BASE_ADDR		0x10000000
 #else
 #error "CPU_TYPE not defined"
 #endif

Signature · 1 line

1.7.5.4

Stefano Babic

author

2012-02-22 10:24 UTC #6 lore raw

PATCH 5/9 SATA: check for return value from sata functions

In reply to Stefano Babic

sata functions are called even if previous functions failed because return value is not checked.

Signed-off-by Stefano Babic <[email protected]>

CC Dirk Behme <[email protected]>

CC Fabio Estevam <[email protected]>

---
 common/cmd_sata.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

common/cmd_sata.c +6 -3

index f62c0cb..dfa5300 100644
@@ -48,9 +48,12 @@ int __sata_initialize(void)
 		sata_dev_desc[i].block_write = sata_write;
 
 		rc = init_sata(i);
-		rc = scan_sata(i);
-		if ((sata_dev_desc[i].lba > 0) && (sata_dev_desc[i].blksz > 0))
-			init_part(&sata_dev_desc[i]);
+		if (!rc) {
+			rc = scan_sata(i);
+			if (!rc && (sata_dev_desc[i].lba > 0) &&
+				(sata_dev_desc[i].blksz > 0))
+				init_part(&sata_dev_desc[i]);
+		}
 	}
 	sata_curr_device = 0;
 	return rc;

Signature · 1 line

1.7.5.4

Stefano Babic

author

2012-02-22 10:24 UTC #7 lore raw

PATCH 6/9 MX53: add function to set SATA clock to internal

In reply to Stefano Babic

The MX53 SATA interface can use an internal clock (USB PHY1) instead of an external clock. This is an undocumented feature, but used on most Freescale's evaluation boards, such as MX53-loco.

As stated by Freescale's support:

Fuses (but not pins) may be used to configure SATA clocks. Particularly the i.MX53 Fuse_Map contains the next information about configuring SATA clocks :

	SATA_ALT_REF_CLK[1:0] (offset 0x180C)

'00' - 100MHz (External)
'01' - 50MHz (External)
'10' - 120MHz, internal (USB PHY)
'11' - Reserved

Signed-off-by Stefano Babic <[email protected]>

CC Fabio Estevam <[email protected]>

---
 arch/arm/cpu/armv7/mx5/clock.c        |   24 ++++++++++++++++++++++++
 arch/arm/include/asm/arch-mx5/clock.h |    1 +
 2 files changed, 25 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/mx5/clock.c +24 -0

index 8f8d01c..d769a4d 100644
@@ -399,6 +399,30 @@ u32 imx_get_fecclk(void)
 	return mxc_get_clock(MXC_IPG_CLK);
 }
 
+#ifdef CONFIG_MX53
+/*
+ * The clock for the external interface can be set to use internal clock
+ * if fuse bank 4, row 3, bit 2 is set.
+ * This is an undocumented feature and it was confirmed by Freescale's support:
+ * Fuses (but not pins) may be used to configure SATA clocks.
+ * Particularly the i.MX53 Fuse_Map contains the next information
+ * about configuring SATA clocks :  SATA_ALT_REF_CLK[1:0] (offset 0x180C)
+ * '00' - 100MHz (External)
+ * '01' - 50MHz (External)
+ * '10' - 120MHz, internal (USB PHY)
+ * '11' - Reserved
+*/
+void mxc_set_sata_internal_clock(void)
+{
+	u32 *tmp_base =
+		(u32 *)(IIM_BASE_ADDR + 0x180c);
+
+	set_usb_phy1_clk();
+
+	writel((readl(tmp_base) & (~0x7)) | 0x4, tmp_base);
+}
+#endif
+
 /*
  * Dump some core clockes.
  */

arch/arm/include/asm/arch-mx5/clock.h +1 -0

index f9f82f3..e822809 100644
@@ -45,5 +45,6 @@ void set_usb_phy2_clk(void);
 void enable_usb_phy2_clk(unsigned char enable);
 void set_usboh3_clk(void);
 void enable_usboh3_clk(unsigned char enable);
+void mxc_set_sata_internal_clock(void);
 
 #endif /* __ASM_ARCH_CLOCK_H */

Signature · 1 line

1.7.5.4

Stefano Babic

author

2012-02-22 10:24 UTC #8 lore raw

PATCH 7/9 SATA: add driver for MX5 / MX6 SOCs

In reply to Stefano Babic

This driver is part of Freescale's LTIB for
MX5 / MX6.

Signed-off-by Stefano Babic <[email protected]>

Signed-off-by Terry Lv <[email protected]>

CC Fabio Estevam <[email protected]>

CC Dirk Behme <[email protected]>

---
 drivers/block/Makefile     |    1 +
 drivers/block/dwc_ahsata.c |  969 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/block/dwc_ahsata.h |  335 +++++++++++++++
 include/ahci.h             |    5 +-
 4 files changed, 1308 insertions(+), 2 deletions(-)
 create mode 100644 drivers/block/dwc_ahsata.c
 create mode 100644 drivers/block/dwc_ahsata.h

drivers/block/Makefile +1 -0

index 98560ef..b9c2047 100644
@@ -27,6 +27,7 @@ LIB	:= $(obj)libblock.o
 
 COBJS-$(CONFIG_SCSI_AHCI) += ahci.o
 COBJS-$(CONFIG_ATA_PIIX) += ata_piix.o
+COBJS-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
 COBJS-$(CONFIG_FSL_SATA) += fsl_sata.o
 COBJS-$(CONFIG_IDE_FTIDE020) += ftide020.o
 COBJS-$(CONFIG_LIBATA) += libata.o

drivers/block/dwc_ahsata.c new file +969 -0

969 lines not on this page · raw message

drivers/block/dwc_ahsata.h new file +335 -0

335 lines not on this page · raw message

include/ahci.h +3 -2

index 465ea7f..c4fb9e7 100644
@@ -30,12 +30,13 @@
 #define AHCI_PCI_BAR		0x24
 #define AHCI_MAX_SG		56 /* hardware max is 64K */
 #define AHCI_CMD_SLOT_SZ	32
+#define AHCI_MAX_CMD_SLOT	32
 #define AHCI_RX_FIS_SZ		256
 #define AHCI_CMD_TBL_HDR	0x80
 #define AHCI_CMD_TBL_CDB	0x40
 #define AHCI_CMD_TBL_SZ		AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
-#define AHCI_PORT_PRIV_DMA_SZ	AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ	\
-				+ AHCI_RX_FIS_SZ
+#define AHCI_PORT_PRIV_DMA_SZ	(AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
+				AHCI_CMD_TBL_SZ	+ AHCI_RX_FIS_SZ)
 #define AHCI_CMD_ATAPI		(1 << 5)
 #define AHCI_CMD_WRITE		(1 << 6)
 #define AHCI_CMD_PREFETCH	(1 << 7)

Signature · 1 line

1.7.5.4

Stefano Babic

author

2012-02-22 10:24 UTC #9 lore raw

PATCH 8/9 MX53: Add support to ESG ima3 board

In reply to Stefano Babic

The ESG ima3-mx53 board is based on the Freescale
i.MX53 SOC. It boots from NOR (128 MB) and
supports Ethernet (FEC), SATA.

Signed-off-by Stefano Babic <[email protected]>

---
 board/esg/ima3-mx53/Makefile     |   41 +++++
 board/esg/ima3-mx53/ima3-mx53.c  |  302 ++++++++++++++++++++++++++++++++++++++
 board/esg/ima3-mx53/imximage.cfg |  108 ++++++++++++++
 boards.cfg                       |    1 +
 include/configs/ima3-mx53.h      |  269 +++++++++++++++++++++++++++++++++
 5 files changed, 721 insertions(+), 0 deletions(-)
 create mode 100644 board/esg/ima3-mx53/Makefile
 create mode 100644 board/esg/ima3-mx53/ima3-mx53.c
 create mode 100644 board/esg/ima3-mx53/imximage.cfg
 create mode 100644 include/configs/ima3-mx53.h

board/esg/ima3-mx53/Makefile new file +41 -0

new file mode 100644
index 0000000..f3b13bc
@@ -0,0 +1,41 @@
+#
+# Copyright (C) 2012, Stefano Babic <[email protected]>
+#
+# Based on ti/evm/Makefile
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= ima3-mx53.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/esg/ima3-mx53/ima3-mx53.c new file +302 -0

302 lines not on this page · raw message

board/esg/ima3-mx53/imximage.cfg new file +108 -0

108 lines not on this page · raw message

boards.cfg +1 -0

index bf71a66..b9fc69a 100644
@@ -197,6 +197,7 @@ mx53ard                      arm         armv7       mx53ard             freesca
 mx53evk                      arm         armv7       mx53evk             freescale      mx5		mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg
 mx53loco                     arm         armv7       mx53loco            freescale      mx5		mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg
 mx53smd                      arm         armv7       mx53smd             freescale      mx5		mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
+ima3-mx53                    arm         armv7       ima3-mx53           esg            mx5		ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
 vision2                      arm         armv7       vision2             ttcontrol      mx5		vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6		mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
 mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg

include/configs/ima3-mx53.h new file +269 -0

269 lines not on this page · raw message

Signature · 1 line

1.7.5.4

Dirk Behme

2012-02-22 10:30 UTC #10 lore raw

PATCH 8/9 MX53: Add support to ESG ima3 board

On 22.02.2012 11:24, Stefano Babic wrote:
...

Quoted 1 line

It boots from NOR (128 MB)

Ah. I wonder why I was under the impression that I was the only guy fighting with the imximage NOR header pain, then ;)

Quoted 5 lines

board/esg/ima3-mx53/imximage.cfg new file +0 -0
new file mode 100644
index 0000000..fa6b42d

...

board/esg/ima3-mx53/imximage.cfg line 33

Quoted 2 lines

board/esg/ima3-mx53/imximage.cfg new file +2 -0
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)

Maybe the above comment should be updated for nor? ;)

Quoted 1 line

+BOOT_FROM nor

I assume that you have tested this and it works with the imximage?

Best regards

Dirk

Stefano Babic

author

2012-02-22 10:46 UTC #11 lore raw

PATCH 8/9 MX53: Add support to ESG ima3 board

Quoted 6 lines · Dirk Behme

On 22.02.2012 11:24, Stefano Babic wrote:
...
Quoted 1 line
It boots from NOR (128 MB)
Ah. I wonder why I was under the impression that I was the only guy fighting with the imximage NOR header pain, then ;)

When something goes wrong, it does for everybody...

Quoted 8 lines

Quoted 7 lines
board/esg/ima3-mx53/imximage.cfg new file +0 -0
new file mode 100644
index 0000000..fa6b42d
...

Quoted 4 lines

board/esg/ima3-mx53/imximage.cfg line 33
Quoted 2 lines
board/esg/ima3-mx53/imximage.cfg new file +2 -0
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
Maybe the above comment should be updated for nor? ;)

Yes, I'll do

Quoted 4 lines

Quoted 2 lines
+BOOT_FROM nor
I assume that you have tested this and it works with the imximage?

I have not any problem with the current imximage, so I am quite confused. Agree that you are fixing a bug, but I have not understood why I have not seen any issue on my board, a MX53 using V2 image header.

My board boots flawlessly from the NOR interface. I will try to investigate why and, of course, I will be able to test your patch on my board.

Can you confirm that your board does not boot ? Or are there other symptoms ?

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Dirk Behme

2012-02-22 11:46 UTC #12 lore raw

PATCH 8/9 MX53: Add support to ESG ima3 board

Quoted 8 lines · Stefano Babic

Quoted 4 lines · Dirk Behme
On 22.02.2012 11:24, Stefano Babic wrote:
...
Quoted 1 line
+BOOT_FROM nor
I assume that you have tested this and it works with the imximage?
I have not any problem with the current imximage, so I am quite confused.

Hmm, yes, this is quite confusing :(

Quoted 8 lines

Agree that you are fixing a bug, but I have not understood why I have not seen any issue on my board, a MX53 using V2 image header.
My board boots flawlessly from the NOR interface. I will try to investigate why and, of course, I will be able to test your patch on my board.
Can you confirm that your board does not boot ?

Yes, removing the imximage fix stops the board from booting. Unfortunately it's hard to debug how the boot ROM deals with the header information. So either it works, or not, but there is little chance to debug :(

For testing, taking the SabreLite (mx6qsabrelite), switching it to NOR
[1] and then compiling it without and with my imximage fix, results in the following difference in the header (disassembly of u-boot.imx):

-      20:      177ff800
+      20:      177fec00

At offset 0x20 in the header, this is the target address in the destination memory. Having a header with the size of 0x400 (like here) the destination address should be TEXT_BASE - 0x400 (header size) - 0x1000 (NOR offset), i.e. 0x17800000 - 0x1400. So my understanding is that 0x177fec00 is correct for NOR, while 0x177ff800 is valid for all FLASH_OFFSET_STANDARD devices.

Best regards

Dirk

[1]

board/freescale/mx6qsabrelite/imximage.cfg
BOOT_FROM nor

Stefano Babic

author

2012-02-22 10:24 UTC #13 lore raw

PATCH 9/9 MX53: mx53loco: Add SATA support

In reply to Stefano Babic

Signed-off-by Stefano Babic <[email protected]>

CC Jason Liu <[email protected]>

---
 board/freescale/mx53loco/mx53loco.c |    3 +++
 include/configs/mx53loco.h          |   11 +++++++++++
 2 files changed, 14 insertions(+), 0 deletions(-)

board/freescale/mx53loco/mx53loco.c +3 -0

index d736141..7ea9f6e 100644
@@ -27,6 +27,7 @@
 #include <asm/arch/mx5x_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/clock.h>
 #include <asm/errno.h>

@@ -302,6 +303,8 @@ int board_init(void)
 {
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	mxc_set_sata_internal_clock();
+
 	return 0;
 }

include/configs/mx53loco.h +11 -0

index 34a4edd..af59307 100644
@@ -56,6 +56,7 @@
 #define CONFIG_CMD_MMC
 #define CONFIG_GENERIC_MMC
 #define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
 #define CONFIG_DOS_PARTITION
 
 /* Eth Configs */

@@ -193,4 +194,14 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+	#define CONFIG_DWC_AHSATA
+	#define CONFIG_SYS_SATA_MAX_DEVICE      1
+	#define CONFIG_DWC_AHSATA_PORT_ID       0
+	#define CONFIG_DWC_AHSATA_BASE_ADDR     SATA_BASE_ADDR
+	#define CONFIG_LBA48
+	#define CONFIG_LIBATA
+#endif
+
 #endif				/* __CONFIG_H */

Signature · 1 line

1.7.5.4

Jason Hui

2012-02-23 15:40 UTC #14 lore raw

PATCH 9/9 MX53: mx53loco: Add SATA support

Quoted 54 lines · Stefano Babic

Signed-off-by Stefano Babic <[email protected]>
CC Jason Liu <[email protected]>
---
?board/freescale/mx53loco/mx53loco.c | ? ?3 +++ ?include/configs/mx53loco.h ? ? ? ? ?| ? 11 +++++++++++ ?2 files changed, 14 insertions(+), 0 deletions(-)
board/freescale/mx53loco/mx53loco.c +0 -0
index d736141..7ea9f6e 100644
@@ -27,6 +27,7 @@
?#include <asm/arch/mx5x_pins.h>
?#include <asm/arch/sys_proto.h>
?#include <asm/arch/crm_regs.h>
+#include <asm/arch/clock.h>
?#include <asm/arch/iomux.h>
?#include <asm/arch/clock.h>
?#include <asm/errno.h>
board/freescale/mx53loco/mx53loco.c +2 -0
@@ -302,6 +303,8 @@ int board_init(void)
 ?{
 ? ? ? ?gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+ ? ? ? mxc_set_sata_internal_clock();
+
 ? ? ? ?return 0;
 ?}
 
include/configs/mx53loco.h +0 -0
index 34a4edd..af59307 100644
@@ -56,6 +56,7 @@
?#define CONFIG_CMD_MMC
?#define CONFIG_GENERIC_MMC
?#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
?#define CONFIG_DOS_PARTITION
?/* Eth Configs */
include/configs/mx53loco.h +0 -0
@@ -193,4 +194,14 @@
 
?#define CONFIG_OF_LIBFDT
include/configs/mx53loco.h +10 -0
+#define CONFIG_CMD_SATA
+#ifdef CONFIG_CMD_SATA
+ ? ? ? #define CONFIG_DWC_AHSATA
+ ? ? ? #define CONFIG_SYS_SATA_MAX_DEVICE ? ? ?1
+ ? ? ? #define CONFIG_DWC_AHSATA_PORT_ID ? ? ? 0
+ ? ? ? #define CONFIG_DWC_AHSATA_BASE_ADDR ? ? SATA_BASE_ADDR
+ ? ? ? #define CONFIG_LBA48
+ ? ? ? #define CONFIG_LIBATA
+#endif
+

Quoted 4 lines

?#endif ? ? ? ? ? ? ? ? ? ? ? ? /* __CONFIG_H */
--
1.7.5.4

Acked-by Jason Liu <[email protected]>