ARM: davinci: add support for the am1808 based enbw_cmc board

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+* TI Davinci Interrupt Controller
+
+davinci are using a TI interrupt controller that can support several
+configurable number of interrupts.
+
+Main node required properties:
+
+- compatible : should be:
+	"ti,davinci-intc"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The type shall be a <u32> and the value shall be 1.
+
+  The cell contains the interrupt number in the range [0-128].
+- ti,intc-size: Number of interrupts handled by the interrupt controller.
+- reg: physical base address and size of the intc registers map.
+
+Example:
+
+	intc: interrupt-controller at 1 {
+		compatible = "ti,davinci-intc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		ti,intc-size = <101>;
+		reg = <0xfffee000 0x2000>;
+	};

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+* Texas Instruments Davinci AEMIF
+
+This file provides information, what the device node for the
+davinci aemif interface contain.
+
+Required properties:
+- compatible: "ti,davinci-aemif";
+- #address-cells : Should be either two or three.  The first cell is the
+                   chipselect number, and the remaining cells are the
+                   offset into the chipselect.
+- #size-cells : Either one or two, depending on how large each chipselect
+                can be.
+- ranges : Each range corresponds to a single chipselect, and cover
+           the entire access window as configured.
+
+Optional properties:
+- none
+
+Optional subnodes:
+- Chipselect setup:
+	- compatible: "ti,davinci-cs";
+	- #address-cells = <1>;
+	- #size-cells = <1>;
+
+    Timing setup, all timings in nanoseconds
+	- cs:		chipselect (value 2,3,4 or 5)
+	- asize:	Asynchronous Data Bus Width.
+			value:
+			0: 8 bit
+			1: 16 bit
+	- ta:		Minimum Turn-Around time.
+	- rhold:	Read hold width
+	- rstrobe:	Read strobe width
+	- rsetup:	Read setup width
+	- whold:	Write hold width
+	- wstrobe:	Write strobe width
+	- wsetup:	Write setup width
+	- ew:		Extend Wait bit
+			value:
+			0: Extended wait cycles disabled.
+			1: Extended wait cycles enabled.
+	- ss:		Select Strobe bit.
+			value:
+			0: Normal Mode enabled.
+			1: Select Strobe Mode enabled.
+- CFI driver:
+  see: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+
+Example (enbw_cmc board):
+	aemif at 60000000 {
+		compatible = "ti,davinci-aemif";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0x68000000 0x80000>;
+		ranges = <2 0 0x60000000 0x02000000
+			  3 0 0x62000000 0x02000000
+			  4 0 0x64000000 0x02000000
+			  5 0 0x66000000 0x02000000
+			  6 0 0x68000000 0x02000000>;
+		cs2 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <2>;
+			asize = <1>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <14>;
+			whold = <7>;
+			wstrobe = <42>;
+			wsetup = <14>;
+			ew = <0>;
+			ss = <0>;
+		};
+		flash at 2,0 {
+			compatible = "cfi-flash";
+			reg = <2 0x0 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+			device-width = <2>;
+		};
+		nand_cs: cs3 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <3>;
+			asize = <0>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <7>;
+			whold = <7>;
+			wstrobe = <14>;
+			wsetup = <7>;
+			ew = <0>;
+			ss = <0>;
+		};
+		nandflash at 3,0 {
+			compatible = "ti,davinci-nand";
+			reg = <3 0x0 0x807ff
+				6 0x0 0x8000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			mask_ale = <0>;
+			mask_cle = <0>;
+			mask_chipsel = <0>;
+			ecc_mode = <2>;
+			ecc_bits = <4>;
+			options = <0>;
+			bbt_options = <0x20000>;
+			pinmux-handle = <&nand_pins>;
+			timing-handle = <&nand_cs>;
+		};
+
+	};

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+* Texas Instruments Davinci pinmux
+
+This file provides information, what the device node for the
+davinci pinmux interface contain.
+
+Required properties:
+- compatible: "ti,davinci-pinmux";
+- pins : contains a table with the following colums:
+   mux register: pinmux register
+   register offset: offset in register, which to change
+   mode mask: mode mask
+   mode value: mode value
+
+Optional properties:
+- none
+
+Example (enbw_cmc board):
+	emac_pins: pinmux at 1c14120 {
+		compatible = "ti,davinci-pinmux";
+		reg = <0x14120 0x1000>;
+		pins = < /*	muxreg	maskoff	modemsk muxmode */
+				2	4	15	8 /* MII TXEN */
+				2	8	15	8 /* MII TXCLK */
+				2	12	15	8 /* MII COL */
+				2	16	15	8 /* MII TXD_3 */
+				2	20	15	8 /* MII TXD_2 */
+				2	24	15	8 /* MII TXD_1 */
+				2	28	15	8 /* MII TXD_0 */
+				3	8	15	8 /* MII RXER */
+				3	12	15	8 /* MII CRS */
+				3	0	15	8 /* MII RXCLK */
+				3	4	15	8 /* MII RXDV */
+				3	16	15	8 /* MII RXD_3 */
+				3	20	15	8 /* MII RXD_2 */
+				3	24	15	8 /* MII RXD_1 */
+				3	28	15	8 /* MII RXD_0 */
+				4	0	15	8 /* MDIO CLK */
+				4	4	15	8 /* MDIO D */
+			>;
+	};

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+* Texas Instruments Davinci EMAC
+
+This file provides information, what the device node
+for the davinci_emac interface contain.
+
+Required properties:
+- compatible: "ti,davinci-dm6460-emac";
+- reg: Offset and length of the register set for the device
+- ti,davinci-ctrl-reg-offset: offset to control register
+- ti,davinci-ctrl-mod-reg-offset: offset to control module register
+- ti,davinci-ctrl-ram-offset: offset to control module ram
+- ti,davinci-ctrl-ram-size: size of control module ram
+- ti,davinci-rmii-en: use RMII
+- ti,davinci-no-bd-ram: has the emac controller BD RAM
+- phy-handle: Contains a phandle to an Ethernet PHY.
+              if not, davinci_emac driver defaults to 100/FULL
+- interrupts: interrupt mapping for the davinci emac interrupts sources:
+              4 sources: <Receive Threshold Interrupt
+			  Receive Interrupt
+			  Transmit Interrupt
+			  Miscellaneous Interrupt>
+- pinmux-handle: Contains a handle to configure the pinmux settings.
+
+Optional properties:
+- local-mac-address : 6 bytes, mac address
+
+Example (enbw_cmc board):
+	eth0: emac at 1e20000 {
+		compatible = "ti,davinci-dm6460-emac";
+		reg = <0x220000 0x4000>;
+		ti,davinci-ctrl-reg-offset = <0x3000>;
+		ti,davinci-ctrl-mod-reg-offset = <0x2000>;
+		ti,davinci-ctrl-ram-offset = <0>;
+		ti,davinci-ctrl-ram-size = <0x2000>;
+		local-mac-address = [ 00 00 00 00 00 00 ];
+		interrupts = <33
+				34
+				35
+				36
+				>;
+		interrupt-parent = <&intc>;
+		pinmux-handle = <&emac_pins>;
+	};

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+* Texas Instruments Davinci I2C
+
+This file provides information, what the device node for the
+davinci i2c interface contain.
+
+Required properties:
+- compatible: "ti,davinci-i2c";
+- reg : Offset and length of the register set for the device
+
+Recommended properties :
+- interrupts : <a> standard interrupt property.
+- clock-frequency : desired I2C bus clock frequency in Hz.
+
+Optional properties:
+- bus-delay: bus delay in usec
+- pinmux-handle: Contains a handle to configure the pinmux settings.
+
+Example (enbw_cmc board):
+	i2c at 1c22000 {
+		compatible = "ti,davinci-i2c";
+		reg = <0x22000 0x1000>;
+		clock-frequency = <100000>;
+		interrupts = <15>;
+		interrupt-parent = <&intc>;
+		pinmux-handle = <&i2c1_pins>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dtt at 48 {
+				compatible = "national,lm75";
+				reg = <0x48>;
+			};
+	};

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+* Texas Instruments Davinci NAND
+
+This file provides information, what the device node for the
+davinci nand interface contain.
+
+Required properties:
+- compatible: "ti,davinci-nand";
+- reg : contain 2 offset/length values:
+        - offset and length for the access window
+        - offset and length for accessing the aemif control registers
+- ti,davinci-chipselect: Indicates on the davinci_nand driver which
+                         chipselect is used for accessing the nand.
+
+Recommended properties :
+- ti,davinci-mask-ale: mask for ale
+- ti,davinci-mask-cle: mask for cle
+- ti,davinci-mask-chipsel: mask for chipselect
+- ti,davinci-ecc-mode: ECC mode valid values for davinci driver:
+		- "none"
+		- "soft"
+		- "hw"
+- ti,davinci-ecc-bits: used ECC bits, currently supported 1 or 4.
+- ti,davinci-nand-buswidth: buswidth 8 or 16
+- ti,davinci-nand-use-bbt: use flash based bad block table support.
+
+Optional properties:
+- pinmux-handle: contains a handle to configure the pinmux settings.
+- timing-handle: contains a handle to setup aemif timing.
+
+Example (enbw_cmc board):
+aemif at 60000000 {
+	compatible = "ti,davinci-aemif";
+	#address-cells = <2>;
+	#size-cells = <1>;
+	reg = <0x68000000 0x80000>;
+	ranges = <2 0 0x60000000 0x02000000
+		  3 0 0x62000000 0x02000000
+		  4 0 0x64000000 0x02000000
+		  5 0 0x66000000 0x02000000
+		  6 0 0x68000000 0x02000000>;
+	nand_cs: cs3 at 68000000 {
+		compatible = "ti,davinci-cs";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		/* all timings in nanoseconds */
+		cs = <3>;
+		asize = <0>;
+		ta = <0>;
+		rhold = <7>;
+		rstrobe = <42>;
+		rsetup = <7>;
+		whold = <7>;
+		wstrobe = <14>;
+		wsetup = <7>;
+		ew = <0>;
+		ss = <0>;
+	};
+	nand at 3,0 {
+		compatible = "ti,davinci-nand";
+		reg = <3 0x0 0x807ff
+			6 0x0 0x8000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ti,davinci-chipselect = <1>;
+		ti,davinci-mask-ale = <0>;
+		ti,davinci-mask-cle = <0>;
+		ti,davinci-mask-chipsel = <0>;
+		ti,davinci-ecc-mode = "hw";
+		ti,davinci-ecc-bits = <4>;
+		ti,davinci-nand-use-bbt;
+		pinmux-handle = <&nand_pins>;
+		timing-handle = <&nand_cs>;
+	};
+};

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+/*
+ * Device Tree for the EnBW CMC plattform
+ *
+ * Copyright 2011 DENX Software Engineering GmbH
+ * Heiko Schocher <[email protected]>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+/dts-v1/;
+/include/ "skeleton.dtsi"
+
+/ {
+	model = "EnBW CMC";
+	compatible = "enbw,cmc";
+
+	aliases {
+		ethernet0 = &eth0;
+	};
+
+	arm {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0xfffee000 0x00020000>;
+		intc: interrupt-controller at 1 {
+			compatible = "ti,davinci-intc";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			ti,intc-size = <101>;
+			reg = <0x0 0x2000>;
+		};
+	};
+	soc at 1c00000 {
+		compatible = "ti,da850";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x01c00000 0x400000>;
+
+		serial0: serial at 1c42000 {
+			compatible = "ti,da850", "ns16550a";
+			reg = <0x42000 0x100>;
+			clock-frequency = <150000000>;
+			reg-shift = <2>;
+			interrupts = <25>;
+			interrupt-parent = <&intc>;
+		};
+		serial1: serial at 1d0c000 {
+			compatible = "ti,da850", "ns16550a";
+			reg = <0x10c000 0x100>;
+			clock-frequency = <150000000>;
+			reg-shift = <2>;
+			interrupts = <53>;
+			interrupt-parent = <&intc>;
+		};
+		serial2: serial at 1d0d000 {
+			compatible = "ti,da850", "ns16550a";
+			reg = <0x10d000 0x100>;
+			clock-frequency = <150000000>;
+			reg-shift = <2>;
+			interrupts = <61>;
+			interrupt-parent = <&intc>;
+		};
+
+		nor_pins: nor_pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					5	24	15	1 /* EMA_BA_1 */
+					6	0	15	1 /* EMA CLK */
+					6	24	15	1 /* EMA_WAIT_1 */
+					7	0	15	1 /* NEMA_CS_2 */
+					7	16	15	1 /* NEMA_WE */
+					7	20	15	1 /* NEMA_OE */
+					9	28	15	1 /* EMA_D_0 */
+					9	24	15	1 /* EMA_D_1 */
+					9	20	15	1 /* EMA_D_2 */
+					9	16	15	1 /* EMA_D_3 */
+					9	12	15	1 /* EMA_D_4 */
+					9	8	15	1 /* EMA_D_5 */
+					9	4	15	1 /* EMA_D_6 */
+					9	0	15	1 /* EMA_D_7 */
+					8	28	15	1 /* EMA_D_8 */
+					8	24	15	1 /* EMA_D_9 */
+					8	20	15	1 /* EMA_D_10 */
+					8	16	15	1 /* EMA_D_11 */
+					8	12	15	1 /* EMA_D_12 */
+					8	8	15	1 /* EMA_D_13 */
+					8	4	15	1 /* EMA_D_14 */
+					8	0	15	1 /* EMA_D_15 */
+					12	28	15	1 /* EMA_A_0 */
+					12	24	15	1 /* EMA_A_1 */
+					12	20	15	1 /* EMA_A_2 */
+					12	16	15	1 /* EMA_A_3 */
+					12	12	15	1 /* EMA_A_4 */
+					12	8	15	1 /* EMA_A_5 */
+					12	4	15	1 /* EMA_A_6 */
+					12	0	15	1 /* EMA_A_7 */
+					11	28	15	1 /* EMA_A_8 */
+					11	24	15	1 /* EMA_A_9 */
+					11	20	15	1 /* EMA_A_10 */
+					11	16	15	1 /* EMA_A_11 */
+					11	12	15	1 /* EMA_A_12 */
+					11	8	15	1 /* EMA_A_13 */
+					11	4	15	1 /* EMA_A_14 */
+					11	0	15	1 /* EMA_A_15 */
+					10	28	15	1 /* EMA_A_16 */
+					10	24	15	1 /* EMA_A_17 */
+					10	20	15	1 /* EMA_A_18 */
+					10	16	15	1 /* EMA_A_19 */
+					10	12	15	1 /* EMA_A_20 */
+					10	8	15	1 /* EMA_A_21 */
+					10	4	15	1 /* EMA_A_22 */
+					10	0	15	1 /* EMA_A_23 */
+				>;
+		};
+		nand_pins: nand_pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					7	4	15	1 /* NEMA_CS_3 */
+				>;
+		};
+
+		emac_pins: pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					2	4	15	8 /* MII TXEN */
+					2	8	15	8 /* MII TXCLK */
+					2	12	15	8 /* MII COL */
+					2	16	15	8 /* MII TXD_3 */
+					2	20	15	8 /* MII TXD_2 */
+					2	24	15	8 /* MII TXD_1 */
+					2	28	15	8 /* MII TXD_0 */
+					3	8	15	8 /* MII RXER */
+					3	12	15	8 /* MII CRS */
+					3	0	15	8 /* MII RXCLK */
+					3	4	15	8 /* MII RXDV */
+					3	16	15	8 /* MII RXD_3 */
+					3	20	15	8 /* MII RXD_2 */
+					3	24	15	8 /* MII RXD_1 */
+					3	28	15	8 /* MII RXD_0 */
+					4	0	15	8 /* MDIO CLK */
+					4	4	15	8 /* MDIO D */
+				>;
+		};
+
+		i2c1_pins: i2c_pinmux at 1c14120 {
+			compatible = "ti,davinci-pinmux";
+			reg = <0x14120 0x1000>;
+			pins = < /*	muxreg	maskoff	modemsk muxmode */
+					4	12	15	2 /* I2C0 SDA */
+					4	8	15	2 /* I2C0 SCL */
+				>;
+		};
+
+		eth0: emac at 1e20000 {
+			compatible = "ti,davinci-dm6460-emac";
+			reg = <0x220000 0x4000>;
+			ti,davinci-ctrl-reg-offset = <0x3000>;
+			ti,davinci-ctrl-mod-reg-offset = <0x2000>;
+			ti,davinci-ctrl-ram-offset = <0>;
+			ti,davinci-ctrl-ram-size = <0x2000>;
+			local-mac-address = [ 00 00 00 00 00 00 ];
+			interrupts = <33
+					34
+					35
+					36
+					>;
+			interrupt-parent = <&intc>;
+			pinmux-handle = <&emac_pins>;
+		};
+
+		i2c at 1c22000 {
+			compatible = "ti,davinci-i2c";
+			reg = <0x22000 0x1000>;
+			clock-frequency = <100000>;
+			interrupts = <15>;
+			interrupt-parent = <&intc>;
+			pinmux-handle = <&i2c1_pins>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dtt at 48 {
+				compatible = "national,lm75";
+				reg = <0x48>;
+			};
+		};
+	};
+	onchipram at 8000000 {
+		compatible = "ti,davinci-onchipram";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x80000000 0x20000>;
+	};
+	aemif at 60000000 {
+		compatible = "ti,davinci-aemif";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		reg = <0x68000000 0x80000>;
+		ranges = <2 0 0x60000000 0x02000000
+			  3 0 0x62000000 0x02000000
+			  4 0 0x64000000 0x02000000
+			  5 0 0x66000000 0x02000000
+			  6 0 0x68000000 0x02000000>;
+		cs2 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <2>;
+			asize = <1>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <14>;
+			whold = <7>;
+			wstrobe = <42>;
+			wsetup = <14>;
+			ew = <0>;
+			ss = <0>;
+		};
+		flash at 2,0 {
+			compatible = "cfi-flash";
+			reg = <2 0x0 0x400000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bank-width = <2>;
+			device-width = <2>;
+		};
+		nand_cs: cs3 at 68000000 {
+			compatible = "ti,davinci-cs";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			/* all timings in nanoseconds */
+			cs = <3>;
+			asize = <0>;
+			ta = <0>;
+			rhold = <7>;
+			rstrobe = <42>;
+			rsetup = <7>;
+			whold = <7>;
+			wstrobe = <14>;
+			wsetup = <7>;
+			ew = <0>;
+			ss = <0>;
+		};
+		nand at 3,0 {
+			compatible = "ti,davinci-nand";
+			reg = <3 0x0 0x807ff
+				6 0x0 0x8000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ti,davinci-chipselect = <1>;
+			ti,davinci-mask-ale = <0>;
+			ti,davinci-mask-cle = <0>;
+			ti,davinci-mask-chipsel = <0>;
+			ti,davinci-ecc-mode = "hw";
+			ti,davinci-ecc-bits = <4>;
+			ti,davinci-nand-use-bbt;
+			pinmux-handle = <&nand_pins>;
+			timing-handle = <&nand_cs>;
+		};
+
+	};
+};

123 lines not on this page · raw message

index 32d837d..4cb0469 100644
@@ -202,6 +202,15 @@ config DA850_WL12XX
 	  Say Y if you want to use a wl1271 expansion card connected to the
 	  AM18x EVM.
 
+config MACH_ENBW_CMC
+	bool "EnBW Communication Module Compact"
+	default ARCH_DAVINCI_DA850
+	depends on ARCH_DAVINCI_DA850
+	select OF
+	help
+	  Say Y here to select the EnBW Communication Module Compact
+	  board.
+
 config GPIO_PCA953X
 	default MACH_DAVINCI_DA850_EVM
 

index 2db78bd..12f3166 100644
@@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
 obj-$(CONFIG_MACH_TNETV107X)		+= board-tnetv107x-evm.o
 obj-$(CONFIG_MACH_MITYOMAPL138)		+= board-mityomapl138.o
 obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)	+= board-omapl138-hawk.o
+obj-$(CONFIG_MACH_ENBW_CMC)		+= board-enbw-cmc.o
 
 # Power Management
 obj-$(CONFIG_CPU_FREQ)			+= cpufreq.o