Sampling instruction pointer on PPC
I am trying to sample instruction pointer along time on a Power7 system. I know that there are accurate mechanisms to do so in Intel processors (e.g., PEBS and Branch Trace Store).
Is it possible to do something similar in Power7? Will the samples be accurate? I am worried that significant delays (skids) may appear.
Thank you,
Victor
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Quoted 26 lines · Victor Jimenez
I am trying to sample instruction pointer along time on a Power7 system. I know that there are accurate mechanisms to do so in Intel processors (e.g., PEBS and Branch Trace Store).
Is it possible to do something similar in Power7? Will the samples be accurate? I am worried that significant delays (skids) may appear.
Thank you,
VictorWARNING / LEGAL TEXT: This message is intended only for the use of the individual or entity to which it is addressed and may contain information which is privileged, confidential, proprietary, or exempt from disclosure under applicable law. If you are not the intended recipient or the person responsible for delivering the message to the intended recipient, you are strictly prohibited from disclosing, distributing, copying, or in any way using this message. If you have received this communication in error, please notify the sender and destroy and delete any copies you may have received.
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Quoted 6 lines · Victor Jimenez
I am trying to sample instruction pointer along time on a Power7 system. I know that there are accurate mechanisms to do so in Intel processors (e.g., PEBS and Branch Trace Store).
Is it possible to do something similar in Power7? Will the samples be accurate? I am worried that significant delays (skids) may appear.
Victor,
There's a subset of events that have a prefix of "PM_MRK_". These are referred to as "marked events". When profiling with such events, the PMU will randomly select (mark) an instruction in a group and follow it through the pipeline. By profiling on marked events, it's possible to uniquely identify which instruction caused a particular event.
This technique results in fewer samples being recorded than for non-marked events, but those that are recorded are almost always precise (no skid). Because you will get fewer than the normal number of samples, you should either profile at a higher sampling rate than normal or make sure your application runs long enough to give you statistically valid results. My rule of thumb is to use a sampling rate of 100x what I would normally use for the non-marked event.
-Maynard
Quoted 20 lines
Thank you,
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Hello Carl,
Quoted 12 lines · Carl E. Love
Victor:
The performance counter tools perf and OProfile capture the value of the instruction pointer at the time an interrupt occurs. The file
arch/powerpc/oprofile/op_model_power4.ccontains the OProfile interrupt handler used for Power 4, 5, 6, and 7. When the performance counters overflow, the instruction pointer (Program Counter) is stored in the SIAR register. The perf and OProfile interrupt handlers store the instruction address in their samples. These tools then use the addresses to create a histogram of where the processor was at the time of the interrupt.
Quoted 2 lines
I am guessing you are hoping to collect something more like an raw sequence of addresses trying to trace where the processor was in time.
That is exactly what I want to do. Basically I want to use IP sampling for detecting and keeping application phase changes.
Quoted 11 lines
I am not aware of a way to read the value of the instruction pointer directly on the fly. But you could possibly emulate it by setting a program counter count value to 2^31 -1, enable the counter to count cycles, then read the SIAR value. You could do this each time you want to take a sample. It would require a couple reads/writes to registers. Note, the counter generates the interrupt to store the instruction pointer into the SIAR register when the most significant bit of the 32 bit HW count value changes from 0 to 1. You will need to then clear the interrupt, actually I would have to double check but I think the default interrupt handler that is enabled with Perf and OProfile are not running will do that quietly for you.
Indeed this seems like it may do the trick. Just one question; from your description I assume that there is no support in the current implementation of perf (e.g., I know perf_event_read_value() is used to read the value of an event, but I cannot find any equivalent function that can write to a counter). I guess that means I need to implement that in the kernel myself, right?
Quoted 4 lines
Not sure that helps.
Carl Love
Thank you!
Victor
Quoted 31 lines · Victor Jimenez
Quoted 26 lines
I am trying to sample instruction pointer along time on a Power7 system. I know that there are accurate mechanisms to do so in Intel processors (e.g., PEBS and Branch Trace Store).
Is it possible to do something similar in Power7? Will the samples be accurate? I am worried that significant delays (skids) may appear.
Thank you,
VictorWARNING / LEGAL TEXT: This message is intended only for the use of the individual or entity to which it is addressed and may contain information which is privileged, confidential, proprietary, or exempt from disclosure under applicable law. If you are not the intended recipient or the person responsible for delivering the message to the intended recipient, you are strictly prohibited from disclosing, distributing, copying, or in any way using this message. If you have received this communication in error, please notify the sender and destroy and delete any copies you may have received.
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Victor Jimenez Perez
Barcelona Supercomputing Center
Centro Nacional de Supercomputacion
WWW: http://www.bsc.es Tel: +34-934137167
e-mail: [email protected]
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