i.MX6: mx6q_sabrelite: add SATA bindings
Subsystems (2)
PATCH 1/1 i.MX6: mx6q_sabrelite: add SATA bindings
This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.html
--- arch/arm/include/asm/arch-mx6/imx-regs.h | 11 +++++ board/freescale/mx6qsabrelite/mx6qsabrelite.c | 54 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 ++++++ 3 files changed, 78 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx6/imx-regs.h +11 -0
@@ -165,6 +165,17 @@#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +/* +* ANATOP register definitions +*/ +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_ENABLE_MASK 0x00002000 +#define ANATOP_PLL_BYPASS_MASK 0x00010000 +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_PWDN_MASK 0x00001000 +#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800 +#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000 +#define CHIP_REV_1_0 0x10#define IRAM_SIZE 0x00040000#define IMX_IIM_BASE OCOTP_BASE_ADDR
board/freescale/mx6qsabrelite/mx6qsabrelite.c +54 -0
64 lines not on this page · raw message
include/configs/mx6qsabrelite.h +13 -0
@@ -69,6 +69,19 @@#define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_SATA +/* +* SATA Configs +*/ +#ifdef CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA +#endif +#define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII
Signature · 1 line
1.7.9
PATCH 1/1 i.MX6: mx6q_sabrelite: add SATA bindings
Quoted 2 lines · Eric Nelson
This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.html
This is helpful, but should be not part of the commit message that is stored in git. Move all additional info after the "---" line.
Quoted 16 lines
Signed-off-by Eric Nelson <[email protected]>--- arch/arm/include/asm/arch-mx6/imx-regs.h | 11 +++++ board/freescale/mx6qsabrelite/mx6qsabrelite.c | 54 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 ++++++ 3 files changed, 78 insertions(+), 0 deletions(-)arch/arm/include/asm/arch-mx6/imx-regs.h +0
-0@@ -165,6 +165,17 @@#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
arch/arm/include/asm/arch-mx6/imx-regs.h line 177
Quoted 10 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +10
-0+/* +* ANATOP register definitions +*/ +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_ENABLE_MASK 0x00002000 +#define ANATOP_PLL_BYPASS_MASK 0x00010000 +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_PWDN_MASK 0x00001000 +#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800 +#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000
There is already a thread initiated by Wolfgang regarding the ANATOP registers:
http://lists.denx.de/pipermail/u-boot/2012-February/117942.html
I think we need in any case a way to consolitate this stuff, even if decided to postpone this activity
Quoted 13 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +1
-0+#define CHIP_REV_1_0 0x10#define IRAM_SIZE 0x00040000#define IMX_IIM_BASE OCOTP_BASE_ADDRboard/freescale/mx6qsabrelite/mx6qsabrelite.c +1
-0@@ -273,10 +273,64 @@ int board_eth_init(bd_t *bis)return 0 ; } +#ifdef CONFIG_CMD_SATA
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 286
Quoted 10 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +10
-0+ +int setup_sata (void ) +{ +u32 reg =0 ; +s32 timeout =100000 ; + +/* Enable sata clock */ + reg =readl (CCM_BASE_ADDR +0x7c );/* CCGR5 */ + reg |=0x30 ; +writel (reg,CCM_BASE_ADDR +0x7c );
We have not the Reference Manual, and using hexadecimal values makes things ready for the Obfuscated C Code Contest:
Do not use offsets. Instead of that, provide structures to access the internal register. This must be fixed globally.
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 296
Quoted 10 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +10
-0+ +/* Enable PLLs */ + reg =readl (ANATOP_BASE_ADDR +0xe0 );/* ENET PLL */ + reg &= ~ANATOP_PLL_PWDN_MASK ; +writel (reg,ANATOP_BASE_ADDR +0xe0 ); + reg |=ANATOP_PLL_ENABLE_MASK ; +while (timeout--) { +if (readl (ANATOP_BASE_ADDR +0xe0 ) &ANATOP_PLL_LOCK ) +break ; + }
Ditto
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 305
Quoted 9 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +9
-0+if (timeout <=0 ) +return -1 ; + reg &= ~ANATOP_PLL_BYPASS_MASK ; +writel (reg,ANATOP_BASE_ADDR +0xe0 ); + reg |=ANATOP_SATA_CLK_ENABLE_MASK ; +writel (reg,ANATOP_BASE_ADDR +0xe0 ); + +/* Enable sata phy */ + reg =readl (IOMUXC_BASE_ADDR +0x34 );/* GPR13 */
We have functions to manage pinmux, use them
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 331
Quoted 6 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +2
-0int board_early_init_f (void ) {setup_iomux_uart (); +#ifdef CONFIG_CMD_SATA +setup_sata ();
Why do we need in early ? Is it really needed before relocation ?
Best regards,
Stefano Babic
Signature · 5 lines
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PATCH 1/1 i.MX6: mx6q_sabrelite: add SATA bindings
Quoted 37 lines · Stefano Babic
Quoted 2 lines · Eric Nelson
This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.htmlThis is helpful, but should be not part of the commit message that is stored in git. Move all additional info after the "---" line.
Quoted 16 lines
Signed-off-by Eric Nelson<[email protected]>--- arch/arm/include/asm/arch-mx6/imx-regs.h | 11 +++++ board/freescale/mx6qsabrelite/mx6qsabrelite.c | 54 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 ++++++ 3 files changed, 78 insertions(+), 0 deletions(-)arch/arm/include/asm/arch-mx6/imx-regs.h +0
-0@@ -165,6 +165,17 @@#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)arch/arm/include/asm/arch-mx6/imx-regs.h line 177
Quoted 10 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +10
-0+/* +* ANATOP register definitions +*/ +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_ENABLE_MASK 0x00002000 +#define ANATOP_PLL_BYPASS_MASK 0x00010000 +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_PWDN_MASK 0x00001000 +#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800 +#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000There is already a thread initiated by Wolfgang regarding the ANATOP registers:
Quoted 5 lines
http://lists.denx.de/pipermail/u-boot/2012-February/117942.html
I think we need in any case a way to consolitate this stuff, even if decided to postpone this activity
Thanks. I saw that but seem to have forgotten it.
Quoted 27 lines
Quoted 13 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +1
-0+#define CHIP_REV_1_0 0x10#define IRAM_SIZE 0x00040000#define IMX_IIM_BASE OCOTP_BASE_ADDRboard/freescale/mx6qsabrelite/mx6qsabrelite.c +1
-0@@ -273,10 +273,64 @@ int board_eth_init(bd_t *bis)return 0 ; } +#ifdef CONFIG_CMD_SATA board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 286
Quoted 10 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +10
-0+ +int setup_sata (void ) +{ +u32 reg =0 ; +s32 timeout =100000 ; + +/* Enable sata clock */ + reg =readl (CCM_BASE_ADDR +0x7c );/* CCGR5 */ + reg |=0x30 ; +writel (reg,CCM_BASE_ADDR +0x7c );We have not the Reference Manual, and using hexadecimal values makes things ready for the Obfuscated C Code Contest:
Quoted 2 lines
I'll try to obfuscate more in a V2. We can win this thing! ;)
Quoted 18 lines
Do not use offsets. Instead of that, provide structures to access the internal register. This must be fixed globally.
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 296
Quoted 10 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +10
-0+ +/* Enable PLLs */ + reg =readl (ANATOP_BASE_ADDR +0xe0 );/* ENET PLL */ + reg&= ~ANATOP_PLL_PWDN_MASK ; +writel (reg,ANATOP_BASE_ADDR +0xe0 ); + reg |=ANATOP_PLL_ENABLE_MASK ; +while (timeout--) { +if (readl (ANATOP_BASE_ADDR +0xe0 )&ANATOP_PLL_LOCK ) +break ; + }Ditto
Quoted 13 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 305
Quoted 9 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +9
-0+if (timeout<=0 ) +return -1 ; + reg&= ~ANATOP_PLL_BYPASS_MASK ; +writel (reg,ANATOP_BASE_ADDR +0xe0 ); + reg |=ANATOP_SATA_CLK_ENABLE_MASK ; +writel (reg,ANATOP_BASE_ADDR +0xe0 ); + +/* Enable sata phy */ + reg =readl (IOMUXC_BASE_ADDR +0x34 );/* GPR13 */ We have functions to manage pinmux, use them
Right.
Quoted 9 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 331
Quoted 6 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +2
-0int board_early_init_f (void ) {setup_iomux_uart (); +#ifdef CONFIG_CMD_SATA +setup_sata ();Why do we need in early ? Is it really needed before relocation ?
Nope. Not needed in early.
Quoted 3 lines
Best regards,
Stefano Babic
PATCH 1/1 i.MX6: mx6q_sabrelite: add SATA bindings
Quoted 40 lines · Eric Nelson
Quoted 39 lines · Stefano Babic
Quoted 2 lines · Eric Nelson
This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.htmlThis is helpful, but should be not part of the commit message that is stored in git. Move all additional info after the "---" line.
Quoted 18 lines
Signed-off-by Eric Nelson<[email protected]>--- arch/arm/include/asm/arch-mx6/imx-regs.h | 11 +++++ board/freescale/mx6qsabrelite/mx6qsabrelite.c | 54 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 ++++++ 3 files changed, 78 insertions(+), 0 deletions(-)arch/arm/include/asm/arch-mx6/imx-regs.h +0
-0@@ -165,6 +165,17 @@#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)arch/arm/include/asm/arch-mx6/imx-regs.h line 177
Quoted 10 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +10
-0+/* +* ANATOP register definitions +*/ +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_ENABLE_MASK 0x00002000 +#define ANATOP_PLL_BYPASS_MASK 0x00010000 +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_PWDN_MASK 0x00001000 +#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800 +#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000There is already a thread initiated by Wolfgang regarding the ANATOP registers:
Quoted 7 lines
Quoted 5 lines
http://lists.denx.de/pipermail/u-boot/2012-February/117942.html
I think we need in any case a way to consolitate this stuff, even if decided to postpone this activity
Thanks. I saw that but seem to have forgotten it.
Most, if not all, definitions above are already defined in arch/arm/include/asm/arch-mx6/ccm_regs.h including a struct member. Therefore there's also no need for magic offsets.
Wolfgang.
PATCH 1/1 i.MX6: mx6q_sabrelite: add SATA bindings
Quoted 47 lines · Wolfgang Grandegger
Quoted 46 lines · Eric Nelson
Quoted 44 lines · Stefano Babic
Quoted 2 lines · Eric Nelson
This patch requires Stefano's driver for MX5/MX6.
http://lists.denx.de/pipermail/u-boot/2012-February/118530.htmlThis is helpful, but should be not part of the commit message that is stored in git. Move all additional info after the "---" line.
Quoted 18 lines
Signed-off-by Eric Nelson<[email protected]>--- arch/arm/include/asm/arch-mx6/imx-regs.h | 11 +++++ board/freescale/mx6qsabrelite/mx6qsabrelite.c | 54 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 ++++++ 3 files changed, 78 insertions(+), 0 deletions(-)arch/arm/include/asm/arch-mx6/imx-regs.h +0
-0@@ -165,6 +165,17 @@#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)arch/arm/include/asm/arch-mx6/imx-regs.h line 177
Quoted 10 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +10
-0+/* +* ANATOP register definitions +*/ +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_ENABLE_MASK 0x00002000 +#define ANATOP_PLL_BYPASS_MASK 0x00010000 +#define ANATOP_PLL_LOCK 0x80000000 +#define ANATOP_PLL_PWDN_MASK 0x00001000 +#define ANATOP_PLL_HOLD_RING_OFF_MASK 0x00000800 +#define ANATOP_SATA_CLK_ENABLE_MASK 0x00100000There is already a thread initiated by Wolfgang regarding the ANATOP registers:
http://lists.denx.de/pipermail/u-boot/2012-February/117942.html
I think we need in any case a way to consolitate this stuff, even if decided to postpone this activity
Quoted 8 lines
Quoted 1 line
Thanks. I saw that but seem to have forgotten it.
Most, if not all, definitions above are already defined in
arch/arm/include/asm/arch-mx6/ccm_regs.hincluding a struct member. Therefore there's also no need for magic offsets.Wolfgang.
Thanks Wolfgang.