i.MX6: Add preliminary cache support

PATCH New Eric Nelson 2 participants 14 messages Mar 4, 2012 – Apr 1, 2012 1 message not in the archive

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Eric Nelson

author

2012-03-04 21:47 UTC #1 lore raw

v2 cover i.MX6: Add preliminary cache support

This series of patches defines the prerequisites for cache support on i.MX6 to allow further driver development to occur.

It does not enable the use of the data cache by default. To enable data cache, comment out this line in mx6qsabrelite.h or mx6qarm2.h:

#define CONFIG_SYS_DCACHE_OFF

V2 of this patch set removes the ethernet driver (fec_mxc) from the patch set because the changes in that driver require additional attention.

Eric Nelson (3):
i.MX6: define CACHELINE_SIZE
i.MX6: implement enable_caches()
i.MX6: mx6qsabrelite: add cache commands if cache is enabled

 arch/arm/cpu/armv7/mx6/soc.c             |    8 ++++++++
 arch/arm/include/asm/arch-mx6/imx-regs.h |    2 ++
 include/configs/mx6qarm2.h               |    2 ++
 include/configs/mx6qsabrelite.h          |    6 ++++++
 4 files changed, 18 insertions(+), 0 deletions(-)

Signature · 1 line

1.7.9

Eric Nelson

author

2012-03-04 21:47 UTC #2 lore raw

PATCH v2 1/3 i.MX6: define CACHELINE_SIZE

Signed-off-by Eric Nelson <[email protected]>

Acked-by Marek Vasut <[email protected]>

---
 arch/arm/include/asm/arch-mx6/imx-regs.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

arch/arm/include/asm/arch-mx6/imx-regs.h +2 -0

index 6a200bb..3e5c4c2 100644
@@ -19,6 +19,8 @@
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
 #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
 #define CAAM_ARB_BASE_ADDR              0x00100000

Signature · 1 line

1.7.9

Eric Nelson

author

2012-03-13 01:08 UTC #3 lore raw

PATCH v2 1/3 i.MX6: define CACHELINE_SIZE

Quoted 12 lines · Eric Nelson

Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  arch/arm/include/asm/arch-mx6/imx-regs.h |    2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx6/imx-regs.h +0 -0
index 6a200bb..3e5c4c2 100644

arch/arm/include/asm/arch-mx6/imx-regs.h line 26

Quoted 8 lines

arch/arm/include/asm/arch-mx6/imx-regs.h +2 -0

@@ -19,6 +19,8 @@
  #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
  #define ROMCP_ARB_BASE_ADDR             0x00000000
  #define ROMCP_ARB_END_ADDR              0x000FFFFF
  #define CAAM_ARB_BASE_ADDR              0x00100000

Hi Stefano,

Any word on this patch?

Please advise,

Eric

Stefano Babic

2012-03-13 08:20 UTC #4 lore raw

PATCH v2 1/3 i.MX6: define CACHELINE_SIZE

Quoted 25 lines · Eric Nelson

Quoted 13 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  arch/arm/include/asm/arch-mx6/imx-regs.h |    2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx6/imx-regs.h +0 -0
index 6a200bb..3e5c4c2 100644
arch/arm/include/asm/arch-mx6/imx-regs.h line 26
Quoted 8 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +2 -0
@@ -19,6 +19,8 @@
  #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define CONFIG_SYS_CACHELINE_SIZE    32
+
  #define ROMCP_ARB_BASE_ADDR             0x00000000
  #define ROMCP_ARB_END_ADDR              0x000FFFFF
  #define CAAM_ARB_BASE_ADDR              0x00100000
Hi Stefano,

Quoted 1 line

Any word on this patch?

No, but the patch is at the moment not useful until the FEC driver works with enabled cache.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Eric Nelson

author

2012-03-13 13:29 UTC #5 lore raw

PATCH v2 1/3 i.MX6: define CACHELINE_SIZE

Quoted 26 lines · Stefano Babic

Quoted 25 lines · Eric Nelson
Quoted 13 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
   arch/arm/include/asm/arch-mx6/imx-regs.h |    2 ++
   1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx6/imx-regs.h +0 -0
index 6a200bb..3e5c4c2 100644
arch/arm/include/asm/arch-mx6/imx-regs.h line 26
Quoted 8 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +2 -0
@@ -19,6 +19,8 @@
   #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
   #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define CONFIG_SYS_CACHELINE_SIZE    32
+
   #define ROMCP_ARB_BASE_ADDR             0x00000000
   #define ROMCP_ARB_END_ADDR              0x000FFFFF
   #define CAAM_ARB_BASE_ADDR              0x00100000
Hi Stefano,

Quoted 8 lines

Quoted 1 line
Any word on this patch?
No, but the patch is at the moment not useful until the FEC driver works with enabled cache.
Best regards,
Stefano Babic

Hi Stefano,

This is used by arch/arm/include/asm/cache.h to set ARCH_DMA_MINALIGN so any driver or subsystem that uses ALLOC_CACHE_ALIGN_BUFFER will be affected.

On that topic, it appears that this patch to support cache in the SD card driver was overlooked:

	http://lists.denx.de/pipermail/u-boot/2012-March/119312.html

Regards,

Eric

Stefano Babic

2012-03-19 15:38 UTC #6 lore raw

PATCH v2 1/3 i.MX6: define CACHELINE_SIZE

In reply to Eric Nelson

Quoted 17 lines · Eric Nelson

Quoted 16 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  arch/arm/include/asm/arch-mx6/imx-regs.h |    2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/include/asm/arch-mx6/imx-regs.h +0 -0
index 6a200bb..3e5c4c2 100644
@@ -19,6 +19,8 @@
  #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  #define __ASM_ARCH_MX6_IMX_REGS_H__
 

Quoted 6 lines

arch/arm/include/asm/arch-mx6/imx-regs.h line 26

Quoted 5 lines

arch/arm/include/asm/arch-mx6/imx-regs.h +2 -0

+#define CONFIG_SYS_CACHELINE_SIZE    32
+
  #define ROMCP_ARB_BASE_ADDR             0x00000000
  #define ROMCP_ARB_END_ADDR              0x000FFFFF
  #define CAAM_ARB_BASE_ADDR              0x00100000

Applied to u-boot-imx, next branch.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Stefano Babic

2012-04-01 13:28 UTC #7 lore raw

PATCH v2 1/3 i.MX6: define CACHELINE_SIZE

In reply to Eric Nelson

Quoted 5 lines · Eric Nelson

Quoted 4 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Eric Nelson

author

2012-03-04 21:47 UTC #8 lore raw

PATCH v2 2/3 i.MX6: implement enable_caches()

In reply to Eric Nelson

disabled by default until drivers are fixed

Signed-off-by Eric Nelson <[email protected]>

Acked-by Marek Vasut <[email protected]>

---
 arch/arm/cpu/armv7/mx6/soc.c    |    8 ++++++++
 include/configs/mx6qarm2.h      |    2 ++
 include/configs/mx6qsabrelite.h |    2 ++
 3 files changed, 12 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/mx6/soc.c +8 -0

index 2ac74b5..eb418eb 100644
@@ -79,6 +79,14 @@ int arch_cpu_init(void)
 }
 #endif
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
+
 #if defined(CONFIG_FEC_MXC)
 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 {

include/configs/mx6qarm2.h +2 -0

index 0962d3c..e83aec6 100644
@@ -169,4 +169,6 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_DCACHE_OFF
+
 #endif				/* __CONFIG_H */

include/configs/mx6qsabrelite.h +2 -0

index 8bc8a83..d3b31fe 100644
@@ -212,4 +212,6 @@
 
 #define CONFIG_OF_LIBFDT
 
+#define CONFIG_SYS_DCACHE_OFF
+
 #endif                         /* __CONFIG_H */

Signature · 1 line

1.7.9

Eric Nelson

author

2012-03-13 01:11 UTC #9 lore raw

PATCH v2 2/3 i.MX6: implement enable_caches()

Quoted 10 lines · Eric Nelson

disabled by default until drivers are fixed
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  arch/arm/cpu/armv7/mx6/soc.c    |    8 ++++++++
  include/configs/mx6qarm2.h      |    2 ++
  include/configs/mx6qsabrelite.h |    2 ++
  3 files changed, 12 insertions(+), 0 deletions(-)

Hi Stefano,

Can you tell that I'm doing some house-cleaning?

Let me know if there's something you'd like changed in this patch.

Regards,

Eric

Stefano Babic

2012-03-19 15:39 UTC #10 lore raw

PATCH v2 2/3 i.MX6: implement enable_caches()

Quoted 11 lines · Eric Nelson

Quoted 10 lines · Eric Nelson
disabled by default until drivers are fixed
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  arch/arm/cpu/armv7/mx6/soc.c    |    8 ++++++++
  include/configs/mx6qarm2.h      |    2 ++
  include/configs/mx6qsabrelite.h |    2 ++
  3 files changed, 12 insertions(+), 0 deletions(-)

Applied to u-boot-imx, next branch.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Stefano Babic

2012-04-01 13:29 UTC #11 lore raw

PATCH v2 2/3 i.MX6: implement enable_caches()

Quoted 13 lines · Stefano Babic

Quoted 11 lines · Eric Nelson
Quoted 10 lines · Eric Nelson
disabled by default until drivers are fixed
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  arch/arm/cpu/armv7/mx6/soc.c    |    8 ++++++++
  include/configs/mx6qarm2.h      |    2 ++
  include/configs/mx6qsabrelite.h |    2 ++
  3 files changed, 12 insertions(+), 0 deletions(-)

Quoted 1 line

Applied to u-boot-imx, next branch.

Wrong - merge into u-boot-imx, master. It goes in this release.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Eric Nelson

author

2012-03-04 21:47 UTC #12 lore raw

PATCH v2 3/3 i.MX6: mx6qsabrelite: add cache commands if cache is enabled

In reply to Eric Nelson

Signed-off-by Eric Nelson <[email protected]>

Acked-by Marek Vasut <[email protected]>

---
 include/configs/mx6qsabrelite.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

include/configs/mx6qsabrelite.h +4 -0

index d3b31fe..c851559 100644
@@ -214,4 +214,8 @@
 
 #define CONFIG_SYS_DCACHE_OFF
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
 #endif                         /* __CONFIG_H */

Signature · 1 line

1.7.9

Eric Nelson

author

2012-03-13 01:14 UTC #13 lore raw

PATCH v2 3/3 i.MX6: mx6qsabrelite: add cache commands if cache is enabled

Quoted 11 lines · Eric Nelson

Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  include/configs/mx6qsabrelite.h |    4 ++++
  1 files changed, 4 insertions(+), 0 deletions(-)
include/configs/mx6qsabrelite.h +0 -0
index d3b31fe..c851559 100644

include/configs/mx6qsabrelite.h line 221

Quoted 8 lines

include/configs/mx6qsabrelite.h +4 -0

@@ -214,4 +214,8 @@
 
  #define CONFIG_SYS_DCACHE_OFF
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
  #endif                         /* __CONFIG_H */

Hi Stefano,

Okay, this is the last outstanding patch in the cache series.

I'm rebasing to your latest tree in preparation for V3 of the fec_mxc patch.

Regards,

Eric

Stefano Babic

2012-03-19 15:40 UTC #14 lore raw

PATCH v2 3/3 i.MX6: mx6qsabrelite: add cache commands if cache is enabled

Quoted 14 lines · Eric Nelson

Quoted 13 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>
Acked-by Marek Vasut<[email protected]>
---
  include/configs/mx6qsabrelite.h |    4 ++++
  1 files changed, 4 insertions(+), 0 deletions(-)
include/configs/mx6qsabrelite.h +0 -0
index d3b31fe..c851559 100644
@@ -214,4 +214,8 @@
 

Quoted 8 lines

include/configs/mx6qsabrelite.h line 221

Quoted 7 lines

include/configs/mx6qsabrelite.h +4 -0

  #define CONFIG_SYS_DCACHE_OFF
 
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
  #endif                         /* __CONFIG_H */

Applied to u-boot-imx, next branch, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================