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mx6: Read silicon revision from register

PATCH Superseded Fabio Estevam 4 participants 5 messages Mar 14, 2012

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Arm (32-bit) Arm i.MX and Layerscape

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Fabio Estevam

author reviewer
#0 lore raw

PATCH v3 1/1 mx6: Read silicon revision from register

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version also print the mx6 variant type: quad, dual/solo or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- Read both chip variant and chip silicon version from anatop
- Create a struct for accessing the anatop registers Changes since v1:
- Fix typo on Subject

 arch/arm/cpu/armv7/imx-common/cpu.c      |   19 +++++++++++++++++--
 arch/arm/cpu/armv7/mx6/soc.c             |    8 +++++++-
 arch/arm/include/asm/arch-mx6/imx-regs.h |    5 +++++
 3 files changed, 29 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/imx-common/cpu.c +17 -2
index 6d7486b..6ced943 100644
@@ -64,13 +64,28 @@ static char *get_reset_cause(void)
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
+
+static char *get_mx6_type(u32 mx6type)
+{
+	switch (mx6type) {
+	case 0x63:
+		return "Q";	/* Quad-core version of the mx6 */
+	case 0x61:
+		return "DS";	/* Dual/Solo version of the mx6 */
+	case 0x60:
+		return "SL";	/* Solo-Lite version of the mx6 */
+	default:
+		return "unknown";
+	}
+}
+
 int print_cpuinfo(void)
 {
 	u32 cpurev;
 
 	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
-		(cpurev & 0xFF000) >> 12,
+	printf("CPU:   Freescale i.MX6%s rev%d.%d at %d MHz\n",
+		get_mx6_type((cpurev & 0xFF000) >> 12),
 		(cpurev & 0x000F0) >> 4,
 		(cpurev & 0x0000F) >> 0,
 		mxc_get_clock(MXC_ARM_CLK) / 1000000);
arch/arm/cpu/armv7/mx6/soc.c +7 -1
index 2ac74b5..a9772ca 100644
@@ -32,7 +32,13 @@
 
 u32 get_cpu_rev(void)
 {
-	int system_rev = 0x61000 | CHIP_REV_1_0;
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg = readl(&anatop->siliconid);
+
+	/* Read mx6 variant: quad, dual or solo */
+	int system_rev = (reg >> 4) & 0xFF000;
+	/* Read mx6 silicon revision */
+	system_rev |= (reg & 0xFF) + 0x10;
 
 	return system_rev;
 }
arch/arm/include/asm/arch-mx6/imx-regs.h +5 -0
index 5ba5f39..9644807 100644
@@ -294,5 +294,10 @@ struct aipstz_regs {
 	u32	opacr4;
 };
 
+struct anatop_regs {
+	u8	rsvd[0x260]; /* To be completed as needed */
+	u32	siliconid;
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
Signature · 1 line
1.7.1
#1 lore raw

PATCH v3 1/1 mx6: Read silicon revision from register

Quoted 27 lines

-----Original Message-----
From: Fabio Estevam [mailto:festevam at gmail.com]
Sent: Wednesday, March 14, 2012 10:57 AM
To: u-boot at lists.denx.de
Cc: sbabic at denx.de; eric.nelson at boundarydevices.com; dirk.behme at de.bosch.com; Liu Hui-R64343; Estevam Fabio-R49496
Subject: [PATCH v3] mx6: Read silicon revision from register

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version also print the mx6 variant type: quad, dual/solo or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v2:
- Read both chip variant and chip silicon version from anatop
- Create a struct for accessing the anatop registers Changes since v1:
- Fix typo on Subject

arch/arm/cpu/armv7/imx-common/cpu.c      |   19 +++++++++++++++++--
arch/arm/cpu/armv7/mx6/soc.c             |    8 +++++++-
arch/arm/include/asm/arch-mx6/imx-regs.h |    5 +++++
3 files changed, 29 insertions(+), 3 deletions(-)

[...]

arch/arm/include/asm/arch-mx6/imx-regs.h struct aipstz_regs { · line 300

Quoted 13 lines
arch/arm/include/asm/arch-mx6/imx-regs.h +4 -0
index 5ba5f39..9644807 100644
@@ -294,5 +294,10 @@ struct aipstz_regs {
 	u32	opacr4;
 };
 
+struct anatop_regs {
+	u8	rsvd[0x260]; /* To be completed as needed */
+	u32	siliconid;
+};

I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg.

ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts:

ANADIG in CCM: for example: PLL/PFD,
ANAREG in power: internal analog regulator, power tree. ANAUSB in usb: for usb vbus dection, charge, etc.
ANAMISC: misc feature, only one register now for the Chip Silicon Version

So the siliconid is in the last register.

Jason Liu

author reviewer
#2 lore raw

PATCH v3 1/1 mx6: Read silicon revision from register

Quoted 10 lines · On Wed, Mar 14, 2012 at 3:09 AM, Liu Hui-R64343 <[email protected]> wrote:

I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg.

ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts:

ANADIG in CCM: for example: PLL/PFD,
ANAREG in power: internal analog regulator, power tree. ANAUSB in usb: for usb vbus dection, charge, etc.
ANAMISC: misc feature, only one register now for the Chip Silicon Version

So the siliconid is in the last register.

In the mx6 reference manual version I have I cannot find all the fields you mentioned.

Can you send me offline the anatop register layout so that I can complete this structure?

#3 lore raw

PATCH v3 1/1 mx6: Read silicon revision from register

Hi Fabio,

Quoted 11 lines · Fabio Estevam
Quoted 9 lines · On Wed, Mar 14, 2012 at 3:09 AM, Liu Hui-R64343 <[email protected]> wrote:

I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg.

ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts:

ANADIG in CCM: for example: PLL/PFD,
ANAREG in power: internal analog regulator, power tree. ANAUSB in usb: for usb vbus dection, charge, etc.
ANAMISC: misc feature, only one register now for the Chip Silicon Version

Quoted 7 lines
Quoted 1 line

So the siliconid is in the last register.

In the mx6 reference manual version I have I cannot find all the fields you mentioned.

Can you send me offline the anatop register layout so that I can complete this structure?

I think "arch/arm/mach-mx6/regs-anadig.h" from Freescale's 2.6.38 kernel tree does define the register layout. Do you have that file?

Wolfgang.

#4 lore raw

PATCH v3 1/1 mx6: Read silicon revision from register

Quoted 16 lines · Wolfgang Grandegger

Hi Fabio,

Quoted 13 lines · Fabio Estevam
Quoted 10 lines · On Wed, Mar 14, 2012 at 3:09 AM, Liu Hui-R64343<[email protected]> wrote:

I'm afraid whether this is correct to add it here since some registers of anatop was included into the ccm_reg.

ANATOP is a collection of analog and anadig. So, ANATOP register mostly is consist of 4 parts:

ANADIG in CCM: for example: PLL/PFD,
ANAREG in power: internal analog regulator, power tree. ANAUSB in usb: for usb vbus dection, charge, etc.
ANAMISC: misc feature, only one register now for the Chip Silicon Version

So the siliconid is in the last register.

Quoted 9 lines
Quoted 5 lines

In the mx6 reference manual version I have I cannot find all the fields you mentioned.

Can you send me offline the anatop register layout so that I can complete this structure?

I think "arch/arm/mach-mx6/regs-anadig.h" from Freescale's 2.6.38 kernel tree does define the register layout. Do you have that file?

If not, you can grab it from here:

	http://opensource.freescale.com/git?p=imx/uboot-imx.git;a=blob;f=include/asm-arm/arch-mx6/regs-anadig.h;h=581064b876244c65b3a0c82bf14a2f3639864b9f;hb=imx_v2009.08_11.11.01