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mx6: Fix reset cause for Power On Reset case

PATCH New Fabio Estevam 2 participants 4 messages Mar 13, 2012 – Mar 19, 2012

Subsystems (2)
Arm (32-bit) Arm i.MX and Layerscape
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Fabio Estevam

author
#0 lore raw

PATCH 1/2 mx6: Fix reset cause for Power On Reset case

After booting mx6qsabrelite from POR the following is reported:

CPU: Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset

This is because both the POR and WDOG bits are set after reset.

Fix this by also checking both bits in the POR case.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/armv7/imx-common/cpu.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/imx-common/cpu.c +1 -0
index 1e30ae5..6d7486b 100644
@@ -44,6 +44,7 @@ static char *get_reset_cause(void)
 
 	switch (cause) {
 	case 0x00001:
+	case 0x00011:
 		return "POR";
 	case 0x00004:
 		return "CSU";
Signature · 1 line
1.7.1
author
#1 lore raw

PATCH 2/2 mx6: Remove duplicate definition of ANATOP_BASE_ADDR

Remove duplicate definition of ANATOP_BASE_ADDR.

Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/include/asm/arch-mx6/imx-regs.h |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)
arch/arm/include/asm/arch-mx6/imx-regs.h +0 -1
index 6a200bb..5ba5f39 100644
@@ -115,7 +115,6 @@
 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
-#define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
Signature · 1 line
1.7.1
#2 lore raw

PATCH 2/2 mx6: Remove duplicate definition of ANATOP_BASE_ADDR

Quoted 4 lines · Fabio Estevam

Remove duplicate definition of ANATOP_BASE_ADDR.

Signed-off-by Fabio Estevam <[email protected]>

---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================
#3 lore raw

PATCH 1/2 mx6: Fix reset cause for Power On Reset case

In reply to Fabio Estevam
Quoted 10 lines · Fabio Estevam

After booting mx6qsabrelite from POR the following is reported:

CPU: Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset

This is because both the POR and WDOG bits are set after reset.

Fix this by also checking both bits in the POR case.

Signed-off-by Fabio Estevam <[email protected]>

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================