mx6: Read silicon revision from register

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam<[email protected]>

---
Changes since v5:
- Avoid duplication of code. Also tested on a mx51evk board. Changes since v4:
- Distinguish the the CPU print depending on the SoC type (MX5 or MX6) Changes since v3:
- Provide a complete struct for anatop registers
Changes since v2:
- Read both chip variant and chip silicon version from anatop
- Create a struct for accessing the anatop registers Changes since v1:
- Fix typo on Subject

  arch/arm/cpu/armv7/imx-common/cpu.c      |   24 +++++-
  arch/arm/cpu/armv7/mx6/soc.c             |    8 ++-
  arch/arm/include/asm/arch-mx6/imx-regs.h |  142 ++++++++++++++++++++++++++++++
  3 files changed, 171 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/imx-common/cpu.c +22 -2

index 6d7486b..3d58d8a 100644
@@ -64,13 +64,33 @@ static char *get_reset_cause(void)
  }
 
  #if defined(CONFIG_DISPLAY_CPUINFO)
+
+static char *get_imx_type(u32 imxtype)
+{
+	switch (imxtype) {
+	case 0x63:
+		return "6Q";	/* Quad-core version of the mx6 */
+	case 0x61:
+		return "6DS";	/* Dual/Solo version of the mx6 */
+	case 0x60:
+		return "6SL";	/* Solo-Lite version of the mx6 */
+	case 0x51:
+		return "51";
+	case 0x53:
+		return "53";
+	default:
+		return "unknown";
+	}
+}
+
  int print_cpuinfo(void)
  {
  	u32 cpurev;
 
  	cpurev = get_cpu_rev();
-	printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
-		(cpurev&  0xFF000)>>  12,
+
+	printf("CPU:   Freescale i.MX%s rev%d.%d at %d MHz\n",
+		get_imx_type((cpurev&  0xFF000)>>  12),
  		(cpurev&  0x000F0)>>  4,
  		(cpurev&  0x0000F)>>  0,
  		mxc_get_clock(MXC_ARM_CLK) / 1000000);

arch/arm/cpu/armv7/mx6/soc.c +7 -1

index 2ac74b5..a81e2bc 100644
@@ -32,7 +32,13 @@
 
  u32 get_cpu_rev(void)
  {
-	int system_rev = 0x61000 | CHIP_REV_1_0;
+	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	int reg = readl(&anatop->digprog);
+
+	/* Read mx6 variant: quad, dual or solo */
+	int system_rev = (reg>>  4)&  0xFF000;
+	/* Read mx6 silicon revision */
+	system_rev |= (reg&  0xFF) + 0x10;
 
  	return system_rev;
  }

arch/arm/include/asm/arch-mx6/imx-regs.h +134 -0

index 5ba5f39..cad957a 100644
@@ -294,5 +294,147 @@ struct aipstz_regs {
  	u32	opacr4;
  };
 
+struct anatop_regs {
+	u32	pll_sys;		/* 0x000 */
+	u32	pll_sys_set;		/* 0x004 */
+	u32	pll_sys_clr;		/* 0x008 */
+	u32	pll_sys_tog;		/* 0x00c */
+	u32	usb1_pll_480_ctrl;	/* 0x010 */
+	u32	usb1_pll_480_ctrl_set;	/* 0x014 */
+	u32	usb1_pll_480_ctrl_clr;	/* 0x018 */
+	u32	usb1_pll_480_ctrl_tog;	/* 0x01c */
+	u32	usb2_pll_480_ctrl;	/* 0x020 */
+	u32	usb2_pll_480_ctrl_set;	/* 0x024 */
+	u32	usb2_pll_480_ctrl_clr;	/* 0x028 */
+	u32	usb2_pll_480_ctrl_tog;	/* 0x02c */
+	u32	pll_528;		/* 0x030 */
+	u32	pll_528_set;		/* 0x034 */
+	u32	pll_528_clr;		/* 0x038 */
+	u32	pll_528_tog;		/* 0x03c */
+	u32	pll_528_ss;		/* 0x040 */
+	u32	rsvd0[3];
+	u32	pll_528_num;		/* 0x050 */
+	u32	rsvd1[3];
+	u32	pll_528_denom;		/* 0x060 */
+	u32	rsvd2[3];
+	u32	pll_audio;		/* 0x070 */
+	u32	pll_audio_set;		/* 0x074 */
+	u32	pll_audio_clr;		/* 0x078 */
+	u32	pll_audio_tog;		/* 0x07c */
+	u32	pll_audio_num;		/* 0x080 */
+	u32	rsvd3[3];
+	u32	pll_audio_denom;	/* 0x090 */
+	u32	rsvd4[3];
+	u32	pll_video;		/* 0x0a0 */
+	u32	pll_video_set;		/* 0x0a4 */
+	u32	pll_video_clr;		/* 0x0a8 */
+	u32	pll_video_tog;		/* 0x0ac */
+	u32	pll_video_num;		/* 0x0b0 */
+	u32	rsvd5[3];
+	u32	pll_video_denom;	/* 0x0c0 */
+	u32	rsvd6[3];
+	u32	pll_mlb;		/* 0x0d0 */
+	u32	pll_mlb_set;		/* 0x0d4 */
+	u32	pll_mlb_clr;		/* 0x0d8 */
+	u32	pll_mlb_tog;		/* 0x0dc */
+	u32	pll_enet;		/* 0x0e0 */
+	u32	pll_enet_set;		/* 0x0e4 */
+	u32	pll_enet_clr;		/* 0x0e8 */
+	u32	pll_enet_tog;		/* 0x0ec */
+	u32	pfd_480;		/* 0x0f0 */
+	u32	pfd_480_set;		/* 0x0f4 */
+	u32	pfd_480_clr;		/* 0x0f8 */
+	u32	pfd_480_tog;		/* 0x0fc */
+	u32	pfd_528;		/* 0x100 */
+	u32	pfd_528_set;		/* 0x104 */
+	u32	pfd_528_clr;		/* 0x108 */
+	u32	pfd_528_tog;		/* 0x10c */
+	u32	reg_1p1;		/* 0x110 */
+	u32	reg_1p1_set;		/* 0x114 */
+	u32	reg_1p1_clr;		/* 0x118 */
+	u32	reg_1p1_tog;		/* 0x11c */
+	u32	reg_3p0;		/* 0x120 */
+	u32	reg_3p0_set;		/* 0x124 */
+	u32	reg_3p0_clr;		/* 0x128 */
+	u32	reg_3p0_tog;		/* 0x12c */
+	u32	reg_2p5;		/* 0x130 */
+	u32	reg_2p5_set;		/* 0x134 */
+	u32	reg_2p5_clr;		/* 0x138 */
+	u32	reg_2p5_tog;		/* 0x13c */
+	u32	reg_core;		/* 0x140 */
+	u32	reg_core_set;		/* 0x144 */
+	u32	reg_core_clr;		/* 0x148 */
+	u32	reg_core_tog;		/* 0x14c */
+	u32	ana_misc0;		/* 0x150 */
+	u32	ana_misc0_set;		/* 0x154 */
+	u32	ana_misc0_clr;		/* 0x158 */
+	u32	ana_misc0_tog;		/* 0x15c */
+	u32	ana_misc1;		/* 0x160 */
+	u32	ana_misc1_set;		/* 0x164 */
+	u32	ana_misc1_clr;		/* 0x168 */
+	u32	ana_misc1_tog;		/* 0x16c */
+	u32	ana_misc2;		/* 0x170 */
+	u32	ana_misc2_set;		/* 0x174 */
+	u32	ana_misc2_clr;		/* 0x178 */
+	u32	ana_misc2_tog;		/* 0x17c */
+	u32	tempsense0;		/* 0x180 */
+	u32	tempsense0_set;		/* 0x184 */
+	u32	tempsense0_clr;		/* 0x188 */
+	u32	tempsense0_tog;		/* 0x18c */
+	u32	tempsense1;		/* 0x190 */
+	u32	tempsense1_set;		/* 0x194 */
+	u32	tempsense1_clr;		/* 0x198 */
+	u32	tempsense1_tog;		/* 0x19c */
+	u32	usb1_vbus_detect;	/* 0x1a0 */
+	u32	usb1_vbus_detect_set;	/* 0x1a4 */
+	u32	usb1_vbus_detect_clr;	/* 0x1a8 */
+	u32	usb1_vbus_detect_tog;	/* 0x1ac */
+	u32	usb1_chrg_detect;	/* 0x1b0 */
+	u32	usb1_chrg_detect_set;	/* 0x1b4 */
+	u32	usb1_chrg_detect_clr;	/* 0x1b8 */
+	u32	usb1_chrg_detect_tog;	/* 0x1bc */
+	u32	usb1_vbus_det_stat;	/* 0x1c0 */
+	u32	usb1_vbus_det_stat_set;	/* 0x1c4 */
+	u32	usb1_vbus_det_stat_clr;	/* 0x1c8 */
+	u32	usb1_vbus_det_stat_tog;	/* 0x1cc */
+	u32	usb1_chrg_det_stat;	/* 0x1d0 */
+	u32	usb1_chrg_det_stat_set;	/* 0x1d4 */
+	u32	usb1_chrg_det_stat_clr;	/* 0x1d8 */
+	u32	usb1_chrg_det_stat_tog;	/* 0x1dc */
+	u32	usb1_loopback;		/* 0x1e0 */
+	u32	usb1_loopback_set;	/* 0x1e4 */
+	u32	usb1_loopback_clr;	/* 0x1e8 */
+	u32	usb1_loopback_tog;	/* 0x1ec */
+	u32	usb1_misc;		/* 0x1f0 */
+	u32	usb1_misc_set;		/* 0x1f4 */
+	u32	usb1_misc_clr;		/* 0x1f8 */
+	u32	usb1_misc_tog;		/* 0x1fc */
+	u32	usb2_vbus_detect;	/* 0x200 */
+	u32	usb2_vbus_detect_set;	/* 0x204 */
+	u32	usb2_vbus_detect_clr;	/* 0x208 */
+	u32	usb2_vbus_detect_tog;	/* 0x20c */
+	u32	usb2_chrg_detect;	/* 0x210 */
+	u32	usb2_chrg_detect_set;	/* 0x214 */
+	u32	usb2_chrg_detect_clr;	/* 0x218 */
+	u32	usb2_chrg_detect_tog;	/* 0x21c */
+	u32	usb2_vbus_det_stat;	/* 0x220 */
+	u32	usb2_vbus_det_stat_set;	/* 0x224 */
+	u32	usb2_vbus_det_stat_clr;	/* 0x228 */
+	u32	usb2_vbus_det_stat_tog;	/* 0x22c */
+	u32	usb2_chrg_det_stat;	/* 0x230 */
+	u32	usb2_chrg_det_stat_set;	/* 0x234 */
+	u32	usb2_chrg_det_stat_clr;	/* 0x238 */
+	u32	usb2_chrg_det_stat_tog;	/* 0x23c */
+	u32	usb2_loopback;		/* 0x240 */
+	u32	usb2_loopback_set;	/* 0x244 */
+	u32	usb2_loopback_clr;	/* 0x248 */

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v5:
- Avoid duplication of code. Also tested on a mx51evk board. Changes since v4:
- Distinguish the the CPU print depending on the SoC type (MX5 or MX6) Changes since v3:
- Provide a complete struct for anatop registers
Changes since v2:
- Read both chip variant and chip silicon version from anatop
- Create a struct for accessing the anatop registers Changes since v1:
- Fix typo on Subject

 arch/arm/cpu/armv7/imx-common/cpu.c      |   24 +++++-
 arch/arm/cpu/armv7/mx6/soc.c             |    8 ++-
 arch/arm/include/asm/arch-mx6/imx-regs.h |  142 ++++++++++++++++++++++++++++++
 3 files changed, 171 insertions(+), 3 deletions(-)

-----Original Message-----
From: Stefano Babic [mailto:sbabic at denx.de]
Sent: Tuesday, March 20, 2012 10:35 PM
To: Estevam Fabio-R49496
Cc: u-boot at lists.denx.de; sbabic at denx.de;
eric.nelson at boundarydevices.com; dirk.behme at de.bosch.com; Liu Hui- R64343
Subject: Re: [PATCH v6] mx6: Read silicon revision from register

Quoted 20 lines · Fabio Estevam

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type:
quad,dual/solo or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

---
Changes since v5:
- Avoid duplication of code. Also tested on a mx51evk board. Changes since v4:
- Distinguish the the CPU print depending on the SoC type (MX5 or MX6) Changes since v3:
- Provide a complete struct for anatop registers Changes since v2:
- Read both chip variant and chip silicon version from anatop
- Create a struct for accessing the anatop registers Changes since v1:
- Fix typo on Subject

Quoted 6 lines

 arch/arm/cpu/armv7/imx-common/cpu.c      |   24 +++++-
 arch/arm/cpu/armv7/mx6/soc.c             |    8 ++-
 arch/arm/include/asm/arch-mx6/imx-regs.h |  142
++++++++++++++++++++++++++++++
 3 files changed, 171 insertions(+), 3 deletions(-)

Acked-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

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Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

---

Quoted 5 lines · Fabio Estevam

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type: quad,dual/solo or solo-lite.

Quoted 6 lines

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

---

Applied to u-boot-imx, thanks.

Quoted 12 lines · Stefano Babic

Quoted 10 lines · Fabio Estevam

Instead of hardcoding the mx6 silicon revision, read it in run-time.

Also, besides the silicon version print the mx6 variant type:
quad,dual/solo or solo-lite.

Tested on a mx6qsabrelite, where it shows:

CPU: Freescale i.MX6Q rev1.0 at 792 MHz

Signed-off-by Fabio Estevam <[email protected]>

---

Quoted 1 line

Applied to u-boot-imx, thanks.

Thanks!

Sounds like this

http://patchwork.ozlabs.org/patch/147669/