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MX53: DDR: Fix ZQHWCTRL field TZQ_CS

PATCH New Troy Kisky 3 participants 9 messages Mar 22, 2012 – Mar 28, 2012 Arm i.MX and Layerscape

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Troy Kisky

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#0 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x04 - 128 cycles.

Signed-off-by Troy Kisky <[email protected]>
---
 board/freescale/mx53ard/imximage_dd3.cfg |    2 +-
 board/freescale/mx53evk/imximage.cfg     |    2 +-
 board/freescale/mx53loco/imximage.cfg    |    2 +-
 board/freescale/mx53smd/imximage.cfg     |    2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

I've tested on an mx53, but this needs much more testing before being applied.

board/freescale/mx53ard/imximage_dd3.cfg +1 -1
index 50e05af..614d29e 100644
@@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039
 DATA 4 0x63fd901c 0x05208138
 DATA 4 0x63fd901c 0x04008048
 DATA 4 0x63fd9020 0x00005800
-DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9040 0x05380003
 DATA 4 0x63fd9058 0x00022227
 DATA 4 0x63fd901C 0x00000000
board/freescale/mx53evk/imximage.cfg +1 -1
index dd7528c..915fb2c 100644
@@ -108,5 +108,5 @@ DATA 4 0x63fd901c 0x00448039
 DATA 4 0x63fd9020 0x00005800
 DATA 4 0x63fd9058 0x00033335
 DATA 4 0x63fd901c 0x00000000
-DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9040 0x05380003
 DATA 4 0x53fa8004 0x00194005
board/freescale/mx53loco/imximage.cfg +1 -1
index f30258e..2ce5f8d 100644
@@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039
 DATA 4 0x63fd901c 0x05208138
 DATA 4 0x63fd901c 0x04008048
 DATA 4 0x63fd9020 0x00005800
-DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9040 0x05380003
 DATA 4 0x63fd9058 0x00022227
 DATA 4 0x63fd901c 0x00000000
board/freescale/mx53smd/imximage.cfg +1 -1
index 50e05af..614d29e 100644
@@ -91,6 +91,6 @@ DATA 4 0x63fd901c 0x00028039
 DATA 4 0x63fd901c 0x05208138
 DATA 4 0x63fd901c 0x04008048
 DATA 4 0x63fd9020 0x00005800
-DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9040 0x05380003
 DATA 4 0x63fd9058 0x00022227
 DATA 4 0x63fd901C 0x00000000
Signature · 1 line
1.7.5.4
author
#1 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Quoted 3 lines · Troy Kisky

Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x04 - 128 cycles.

Typo, should say default of 0x02 - 128 cycles

Quoted 16 lines
Signed-off-by Troy Kisky<[email protected]>
---
  board/freescale/mx53ard/imximage_dd3.cfg |    2 +-
  board/freescale/mx53evk/imximage.cfg     |    2 +-
  board/freescale/mx53loco/imximage.cfg    |    2 +-
  board/freescale/mx53smd/imximage.cfg     |    2 +-
  4 files changed, 4 insertions(+), 4 deletions(-)

I've tested on an mx53, but this needs much more testing before being applied.

author
#2 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Quoted 6 lines · Troy Kisky
Quoted 3 lines · Troy Kisky

Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x04 - 128 cycles.

Typo, should say default of 0x02 - 128 cycles

Possibly the manual is wrong, and the value of 0x01 corresponds to 64 cycles? My testing was on a DDR2 device where this field is not relevant.

Quoted 17 lines
Quoted 16 lines
Signed-off-by Troy Kisky<[email protected]>
---
  board/freescale/mx53ard/imximage_dd3.cfg |    2 +-
  board/freescale/mx53evk/imximage.cfg     |    2 +-
  board/freescale/mx53loco/imximage.cfg    |    2 +-
  board/freescale/mx53smd/imximage.cfg     |    2 +-
  4 files changed, 4 insertions(+), 4 deletions(-)

I've tested on an mx53, but this needs much more testing before being applied.

#3 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Quoted 10 lines · Troy Kisky
Quoted 6 lines · Troy Kisky
Quoted 3 lines · Troy Kisky

Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x04 - 128 cycles.

Typo, should say default of 0x02 - 128 cycles

Possibly the manual is wrong, and the value of 0x01 corresponds to 64 cycles? My testing was on a DDR2 device where this field is not relevant.

Is there someone who can answer to this question ? This patch fixes the value according to the manual, without doubts. But if the manual is wrong...

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
reviewer
#4 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Hi Stefano,

Quoted 2 lines · Stefano Babic

Is there someone who can answer to this question ? This patch fixes the value according to the manual, without doubts. But if the manual is wrong...

We are checking this internally at Freescale and will keep the list updated.

Thanks,

Fabio Estevam

#6 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

In reply to Troy Kisky
Quoted 6 lines · Troy Kisky

Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x04 - 128 cycles.

Signed-off-by Troy Kisky <[email protected]>

---

Thanks everybody to fix / explain this issue.

Applied to u-boot-imx(fix), thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
reviewer
#7 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Quoted 11 lines · Stefano Babic
Quoted 6 lines · Troy Kisky

Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x04 - 128 cycles.

Signed-off-by Troy Kisky <[email protected]>

---

Thanks everybody to fix / explain this issue.

Applied to u-boot-imx(fix), thanks.

Just noticed in this thread that Troy reported a typo in his commit
log: it should have said
"default of 0x02 - 128 cycles"

#8 lore raw

PATCH 1/1 MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Quoted 9 lines · Fabio Estevam
Quoted 8 lines · Stefano Babic
Quoted 6 lines · Troy Kisky

Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x04 - 128 cycles.

Signed-off-by Troy Kisky <[email protected]>

---

Quoted 7 lines
Quoted 3 lines

Thanks everybody to fix / explain this issue.

Applied to u-boot-imx(fix), thanks.

Just noticed in this thread that Troy reported a typo in his commit
log: it should have said
"default of 0x02 - 128 cycles"

Right - I have fixed it myself on the tree, thanks.

Stefano

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================