mx53: Make PLL2 to be the parent of UART clock
Subsystems (2)
PATCH 1/1 mx53: Make PLL2 to be the parent of UART clock
Change the parent UART clock to be PLL2, so that U-boot can also boot a Freescale 2.6.35 kernel for mx53.
FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid conflicts with IPU clocks, so that the video resolution can be changed without affecting the UART clock.
On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem.
Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.
--- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 20 +++++++++++++++++--- 1 files changed, 17 insertions(+), 3 deletions(-)
arch/arm/cpu/armv7/mx5/lowlevel_init.S +17 -3
@@ -284,10 +284,24 @@ ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] #elif defined(CONFIG_MX53) + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00808145 + orr r1, r1, #(2 << 10) + orr r1, r1, #(0 << 16) + orr r1, r1, #(1 << 19) + str r1, [r0, #CLKCTL_CBCDR] + + ldr r1, =0x00016154 + str r1, [r0, #CLKCTL_CBCMR] + /* Change uart clk parent to pll2*/ + ldr r1, [r0, #CLKCTL_CSCMR1] + and r1, r1, #0xfcffffff + orr r1, r1, #0x01000000 + str r1, [r0, #CLKCTL_CSCMR1] ldr r1, [r0, #CLKCTL_CSCDR1] - orr r1, r1, #0x3f - eor r1, r1, #0x3f - orr r1, r1, #0x21 + and r1, r1, #0xffffffc0 + orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] #endif /* make sure divider effective */
Signature · 1 line
1.7.1
PATCH 1/1 mx53: Make PLL2 to be the parent of UART clock
On Wed, Mar 21, 2012 at 12:42, Fabio Estevam <[email protected]> wrote:
...
Quoted 2 lines
On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem.
...
I tested it on my imx53qsb and it does fix the issue.
Signature · 3 lines
Otavio Salvador? ? ? ? ? ? ? ? ? ? ? ? ? ? ?O.S. Systems E-mail: otavio at ossystems.com.br? http://www.ossystems.com.br Mobile: +55 53 9981-7854? ? ? ?? ? ? ?http://projetos.ossystems.com.br
PATCH 1/1 mx53: Make PLL2 to be the parent of UART clock
In reply to Fabio EstevamQuoted 7 lines · Fabio Estevam
Change the parent UART clock to be PLL2, so that U-boot can also boot a Freescale 2.6.35 kernel for mx53.
FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid conflicts with IPU clocks, so that the video resolution can be changed without affecting the UART clock.
Quoted 8 lines
On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem.
Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.
Reported-by Otavio Salvador <[email protected]>Signed-off-by Fabio Estevam <[email protected]>---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
Signature · 5 lines
===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de =====================================================================