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ARM: VIC: Create common infrastructure for vic DT bindings

PATCH In review Viresh Kumar 5 participants 7 messages Mar 23, 2012 – Mar 26, 2012 1 message not in the archive

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#0 lore raw

PATCH 1/2 ARM: VIC: Create common infrastructure for vic DT bindings

Few platforms define there own struct of_device_id[] for vic pl19*. They don't do anything specific in init_irq() other than of_irq_init().

This patch creates this struct array in vic.c and make other platforms use it.

---
 arch/arm/common/vic.c               |   14 +++++++++++++-
 arch/arm/include/asm/hardware/vic.h |    3 ++-
 arch/arm/mach-picoxcell/common.c    |   12 +-----------
 arch/arm/mach-spear6xx/spear6xx.c   |   12 +-----------
 4 files changed, 17 insertions(+), 24 deletions(-)
arch/arm/common/vic.c +13 -1
index 7a66311..190813e 100644
@@ -398,7 +398,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 }
 
 #ifdef CONFIG_OF
-int __init vic_of_init(struct device_node *node, struct device_node *parent)
+static int __init vic_of_init(struct device_node *node, struct device_node
+		*parent)
 {
 	void __iomem *regs;
 	int irq_base;
@@ -423,6 +424,17 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
 
 	return -EIO;
 }
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+void __init vic_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
 #endif /* CONFIG OF */
 
 /*
arch/arm/include/asm/hardware/vic.h +2 -1
index e14af1a..02056a8 100644
@@ -42,6 +42,7 @@
 
 #ifndef __ASSEMBLY__
 #include <linux/compiler.h>
+#include <linux/init.h>
 #include <linux/types.h>
 
 struct device_node;
@@ -50,7 +51,7 @@ struct pt_regs;
 void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
 		u32 resume_sources, struct device_node *node);
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-int vic_of_init(struct device_node *node, struct device_node *parent);
+void __init vic_init_irq(void);
 void vic_handle_irq(struct pt_regs *regs);
 
 #endif /* __ASSEMBLY__ */
arch/arm/mach-picoxcell/common.c +1 -11
index a2e8ae8..fa0d7e9 100644
@@ -68,16 +68,6 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static const struct of_device_id vic_of_match[] __initconst = {
-	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
-	{ /* Sentinel */ }
-};
-
-static void __init picoxcell_init_irq(void)
-{
-	of_irq_init(vic_of_match);
-}
-
 static void picoxcell_wdt_restart(char mode, const char *cmd)
 {
 	/*
@@ -95,7 +85,7 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
 	.map_io		= picoxcell_map_io,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= picoxcell_init_irq,
+	.init_irq	= vic_init_irq,
 	.handle_irq	= vic_handle_irq,
 	.timer		= &picoxcell_timer,
 	.init_machine	= picoxcell_init_machine,
arch/arm/mach-spear6xx/spear6xx.c +1 -11
index 2ed8b14..d436118 100644
@@ -102,19 +102,9 @@ static const char *spear600_dt_board_compat[] = {
 	NULL
 };
 
-static const struct of_device_id vic_of_match[] __initconst = {
-	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
-	{ /* Sentinel */ }
-};
-
-static void __init spear6xx_dt_init_irq(void)
-{
-	of_irq_init(vic_of_match);
-}
-
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
 	.map_io		=	spear6xx_map_io,
-	.init_irq	=	spear6xx_dt_init_irq,
+	.init_irq	=	vic_init_irq,
 	.handle_irq	=	vic_handle_irq,
 	.timer		=	&spear6xx_timer,
 	.init_machine	=	spear600_dt_init,
Signature · 1 line
1.7.8.110.g4cb5d
#1 lore raw

PATCH 2/2 ARM: GIC: Create common infrastructure for GIC DT bindings

Few platforms define there own struct of_device_id[] for GIC. They don't do anything specific in init_irq() other than of_irq_init().

This patch creates this struct array in gic.c and make other platforms use it.

---
 arch/arm/common/gic.c               |   10 ++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 arch/arm/mach-exynos/common.c       |    9 +--------
 arch/arm/mach-highbank/highbank.c   |    7 +------
 arch/arm/mach-imx/mach-imx6q.c      |    2 +-
 arch/arm/mach-tegra/common.c        |    7 +------
 arch/arm/mach-ux500/cpu.c           |    7 +------
 arch/arm/mach-vexpress/v2m.c        |   12 +-----------
 8 files changed, 17 insertions(+), 38 deletions(-)
arch/arm/common/gic.c +10 -0
index aa52699..77afdae 100644
@@ -781,4 +781,14 @@ int __init gic_of_init(struct device_node *node, struct device_node *parent)
 	gic_cnt++;
 	return 0;
 }
+
+static const struct of_device_id gic_of_match[] __initconst = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ /* Sentinel */ }
+};
+
+void __init gic_init_irq(void)
+{
+	of_irq_init(gic_of_match);
+}
 #endif
arch/arm/include/asm/hardware/gic.h +1 -0
index 4b1ce6c..7bce4bd 100644
@@ -42,6 +42,7 @@ void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
 		    u32 offset, struct device_node *);
 int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init(unsigned int);
+void __init gic_init_irq(void);
 void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
arch/arm/mach-exynos/common.c +1 -8
index 85ed8b5..76f6079 100644
@@ -502,13 +502,6 @@ static void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 	}
 }
 
-#ifdef CONFIG_OF
-static const struct of_device_id exynos4_dt_irq_match[] = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{},
-};
-#endif
-
 void __init exynos4_init_irq(void)
 {
 	int irq;
@@ -520,7 +513,7 @@ void __init exynos4_init_irq(void)
 		gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 #ifdef CONFIG_OF
 	else
-		of_irq_init(exynos4_dt_irq_match);
+		gic_init_irq();
 #endif
 
 	for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
arch/arm/mach-highbank/highbank.c +1 -6
index 410a112..42b30c6 100644
@@ -80,14 +80,9 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
 			  HB_JUMP_TABLE_PHYS(cpu) + 15);
 }
 
-const static struct of_device_id irq_match[] = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{}
-};
-
 static void __init highbank_init_irq(void)
 {
-	of_irq_init(irq_match);
+	gic_init_irq();
 	l2x0_of_init(0, ~0UL);
 }
 
arch/arm/mach-imx/mach-imx6q.c +1 -1
index 7696dfa..ebaf6c5 100644
@@ -105,7 +105,6 @@ static int __init imx6q_gpio_add_irq_domain(struct device_node *np,
 }
 
 static const struct of_device_id imx6q_irq_match[] __initconst = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
 	{ .compatible = "fsl,imx6q-gpio", .data = imx6q_gpio_add_irq_domain, },
 	{ /* sentinel */ }
 };
@@ -115,6 +114,7 @@ static void __init imx6q_init_irq(void)
 	l2x0_of_init(0, ~0UL);
 	imx_src_init();
 	imx_gpc_init();
+	gic_init_irq();
 	of_irq_init(imx6q_irq_match);
 }
 
arch/arm/mach-tegra/common.c +1 -6
index 22df10f..c8d6208 100644
@@ -52,15 +52,10 @@ u32 tegra_uart_config[3] = {
 };
 
 #ifdef CONFIG_OF
-static const struct of_device_id tegra_dt_irq_match[] __initconst = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
-	{ }
-};
-
 void __init tegra_dt_init_irq(void)
 {
 	tegra_init_irq();
-	of_irq_init(tegra_dt_irq_match);
+	gic_init_irq();
 }
 #endif
 
arch/arm/mach-ux500/cpu.c +1 -6
index d11f389..3bb6f13 100644
@@ -30,11 +30,6 @@
 
 void __iomem *_PRCMU_BASE;
 
-static const struct of_device_id ux500_dt_irq_match[] = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{},
-};
-
 void __init ux500_init_irq(void)
 {
 	void __iomem *dist_base;
@@ -51,7 +46,7 @@ void __init ux500_init_irq(void)
 
 #ifdef CONFIG_OF
 	if (of_have_populated_dt())
-		of_irq_init(ux500_dt_irq_match);
+		gic_init_irq();
 	else
 #endif
 		gic_init(0, 29, dist_base, cpu_base);
arch/arm/mach-vexpress/v2m.c +1 -11
index 47cdcca..3d875f2 100644
@@ -619,16 +619,6 @@ void __init v2m_dt_init_early(void)
 	versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
-static  struct of_device_id vexpress_irq_match[] __initdata = {
-	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-	{}
-};
-
-static void __init v2m_dt_init_irq(void)
-{
-	of_irq_init(vexpress_irq_match);
-}
-
 static void __init v2m_dt_timer_init(void)
 {
 	struct device_node *node;
@@ -677,7 +667,7 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
 	.dt_compat	= v2m_dt_match,
 	.map_io		= v2m_dt_map_io,
 	.init_early	= v2m_dt_init_early,
-	.init_irq	= v2m_dt_init_irq,
+	.init_irq	= gic_init_irq,
 	.timer		= &v2m_dt_timer,
 	.init_machine	= v2m_dt_init,
 	.handle_irq	= gic_handle_irq,
Signature · 1 line
1.7.8.110.g4cb5d

A message that is not in the archive (sent off-list or not yet received): 23b4d2ea357a7a785b6c42d0fa7ae9478bad552b.1332488625.git.viresh.kumar-qxv4g6HH51o@public.gmane.org

Acked-by
#3 lore raw

Re: [PATCH 2/2] ARM: GIC: Create common infrastructure for GIC DT bindings

Quoted 194 lines · Viresh Kumar

Few platforms define there own struct of_device_id[] for GIC. They don't do anything specific in init_irq() other than of_irq_init().

This patch creates this struct array in gic.c and make other platforms use it.

---
 arch/arm/common/gic.c               |   10 ++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 arch/arm/mach-exynos/common.c       |    9 +--------
 arch/arm/mach-highbank/highbank.c   |    7 +------
 arch/arm/mach-imx/mach-imx6q.c      |    2 +-
 arch/arm/mach-tegra/common.c        |    7 +------
 arch/arm/mach-ux500/cpu.c           |    7 +------
 arch/arm/mach-vexpress/v2m.c        |   12 +-----------
 8 files changed, 17 insertions(+), 38 deletions(-)
arch/arm/common/gic.c +10 -0
index aa52699..77afdae 100644
@@ -781,4 +781,14 @@ int __init gic_of_init(struct device_node *node,
 struct device_node *parent)
       gic_cnt++;
       return 0;
 }
+
+static const struct of_device_id gic_of_match[] __initconst = {
+       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+       { /* Sentinel */ }
+};
+
+void __init gic_init_irq(void)
+{
+       of_irq_init(gic_of_match);
+}

#endif

arch/arm/include/asm/hardware/gic.h +1 -0
index 4b1ce6c..7bce4bd 100644
@@ -42,6 +42,7 @@ void gic_init_bases(unsigned int, int, void __iomem *,
 void __iomem *,
                   u32 offset, struct device_node *);
 int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init(unsigned int);
+void __init gic_init_irq(void);
 void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);

void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);

arch/arm/mach-exynos/common.c +0 -7
index 85ed8b5..76f6079 100644
@@ -502,13 +502,6 @@ static void __init combiner_init(unsigned int
 combiner_nr, void __iomem *base,
       }
 }
 
-#ifdef CONFIG_OF
-static const struct of_device_id exynos4_dt_irq_match[] = {
-       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-       {},
-};
-#endif
-
 void __init exynos4_init_irq(void)
 {
       int irq;
arch/arm/mach-exynos/common.c +1 -1
@@ -520,7 +513,7 @@ void __init exynos4_init_irq(void)
               gic_init_bases(0, IRQ_PPI(0), S5P_VA_GIC_DIST,
 S5P_VA_GIC_CPU, gic_bank_offset, NULL);
 #ifdef CONFIG_OF
       else
-               of_irq_init(exynos4_dt_irq_match);
+               gic_init_irq();
 #endif
 
       for (irq = 0; irq < EXYNOS4_MAX_COMBINER_NR; irq++) {
arch/arm/mach-highbank/highbank.c +1 -6
index 410a112..42b30c6 100644
@@ -80,14 +80,9 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
                         HB_JUMP_TABLE_PHYS(cpu) + 15);
 }
 
-const static struct of_device_id irq_match[] = {
-       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-       {}
-};
-
 static void __init highbank_init_irq(void)
 {
-       of_irq_init(irq_match);
+       gic_init_irq();
       l2x0_of_init(0, ~0UL);
 }
 
arch/arm/mach-imx/mach-imx6q.c +0 -1
index 7696dfa..ebaf6c5 100644
@@ -105,7 +105,6 @@ static int __init imx6q_gpio_add_irq_domain(struct
 device_node *np,
 }
 
 static const struct of_device_id imx6q_irq_match[] __initconst = {
-       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
       { .compatible = "fsl,imx6q-gpio", .data =
 imx6q_gpio_add_irq_domain, },
       { /* sentinel */ }

};

arch/arm/mach-imx/mach-imx6q.c +1 -0
@@ -115,6 +114,7 @@ static void __init imx6q_init_irq(void)
       l2x0_of_init(0, ~0UL);
       imx_src_init();
       imx_gpc_init();
+       gic_init_irq();
       of_irq_init(imx6q_irq_match);
 }
 
arch/arm/mach-tegra/common.c +1 -6
index 22df10f..c8d6208 100644
@@ -52,15 +52,10 @@ u32 tegra_uart_config[3] = {
 };
 
 #ifdef CONFIG_OF
-static const struct of_device_id tegra_dt_irq_match[] __initconst = {
-       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init },
-       { }
-};
-
 void __init tegra_dt_init_irq(void)
 {
       tegra_init_irq();
-       of_irq_init(tegra_dt_irq_match);
+       gic_init_irq();
 }
 #endif
 
arch/arm/mach-ux500/cpu.c +1 -6
index d11f389..3bb6f13 100644
@@ -30,11 +30,6 @@
 
 void __iomem *_PRCMU_BASE;
 
-static const struct of_device_id ux500_dt_irq_match[] = {
-       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-       {},
-};
-
 void __init ux500_init_irq(void)
 {
       void __iomem *dist_base;
@@ -51,7 +46,7 @@ void __init ux500_init_irq(void)
 
 #ifdef CONFIG_OF
       if (of_have_populated_dt())
-               of_irq_init(ux500_dt_irq_match);
+               gic_init_irq();
       else
 #endif
               gic_init(0, 29, dist_base, cpu_base);
arch/arm/mach-vexpress/v2m.c +0 -10
index 47cdcca..3d875f2 100644
@@ -619,16 +619,6 @@ void __init v2m_dt_init_early(void)
       versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ,
 24000000);
 }
 
-static  struct of_device_id vexpress_irq_match[] __initdata = {
-       { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
-       {}
-};
-
-static void __init v2m_dt_init_irq(void)
-{
-       of_irq_init(vexpress_irq_match);
-}
-
 static void __init v2m_dt_timer_init(void)
 {
       struct device_node *node;

arch/arm/mach-vexpress/v2m.c DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express") · line 673

Quoted 8 lines
arch/arm/mach-vexpress/v2m.c +1 -1
@@ -677,7 +667,7 @@ DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
       .dt_compat      = v2m_dt_match,
       .map_io         = v2m_dt_map_io,
       .init_early     = v2m_dt_init_early,
-       .init_irq       = v2m_dt_init_irq,
+       .init_irq       = gic_init_irq,
       .timer          = &v2m_dt_timer,
       .init_machine   = v2m_dt_init,
       .handle_irq     = gic_handle_irq,

Looks sensible.

For the ux500 stuff:

Quoted 1 line

_______________________________________________
devicetree-discuss mailing list devicetree-discuss-uLR06cmDAlY/[email protected]
https://lists.ozlabs.org/listinfo/devicetree-discuss

#5 lore raw

PATCH 1/2 ARM: VIC: Create common infrastructure for vic DT bindings

In reply to Viresh Kumar
Quoted 5 lines · Viresh Kumar

Few platforms define there own struct of_device_id[] for vic pl19*. They don't do anything specific in init_irq() other than of_irq_init().

This patch creates this struct array in vic.c and make other platforms use it.

Quoted 8 lines
---
 arch/arm/common/vic.c               |   14 +++++++++++++-
 arch/arm/include/asm/hardware/vic.h |    3 ++-
 arch/arm/mach-picoxcell/common.c    |   12 +-----------
 arch/arm/mach-spear6xx/spear6xx.c   |   12 +-----------
 4 files changed, 17 insertions(+), 24 deletions(-)

NAK

None of these platforms have gpio interrupts or any other board interrupt controllers which need to be initialized early? I don't think DT conversions are complete enough to tell.

We could do something like this, but there only needs to be a single match list of all controllers and function. We should consolidate the irqchips to drivers/irqchip first though. I have that action from Connect...

Rob

Quoted 108 lines
arch/arm/common/vic.c +13 -1
index 7a66311..190813e 100644
@@ -398,7 +398,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 }
 
 #ifdef CONFIG_OF
-int __init vic_of_init(struct device_node *node, struct device_node *parent)
+static int __init vic_of_init(struct device_node *node, struct device_node
+		*parent)
 {
 	void __iomem *regs;
 	int irq_base;
@@ -423,6 +424,17 @@ int __init vic_of_init(struct device_node *node, struct device_node *parent)
 
 	return -EIO;
 }
+
+static const struct of_device_id vic_of_match[] __initconst = {
+	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
+	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
+	{ /* Sentinel */ }
+};
+
+void __init vic_init_irq(void)
+{
+	of_irq_init(vic_of_match);
+}
 #endif /* CONFIG OF */
 
 /*
arch/arm/include/asm/hardware/vic.h +2 -1
index e14af1a..02056a8 100644
@@ -42,6 +42,7 @@
 
 #ifndef __ASSEMBLY__
 #include <linux/compiler.h>
+#include <linux/init.h>
 #include <linux/types.h>
 
 struct device_node;
@@ -50,7 +51,7 @@ struct pt_regs;
 void __vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources,
 		u32 resume_sources, struct device_node *node);
 void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
-int vic_of_init(struct device_node *node, struct device_node *parent);
+void __init vic_init_irq(void);
 void vic_handle_irq(struct pt_regs *regs);
 
 #endif /* __ASSEMBLY__ */
arch/arm/mach-picoxcell/common.c +1 -11
index a2e8ae8..fa0d7e9 100644
@@ -68,16 +68,6 @@ static const char *picoxcell_dt_match[] = {
 	NULL
 };
 
-static const struct of_device_id vic_of_match[] __initconst = {
-	{ .compatible = "arm,pl192-vic", .data = vic_of_init, },
-	{ /* Sentinel */ }
-};
-
-static void __init picoxcell_init_irq(void)
-{
-	of_irq_init(vic_of_match);
-}
-
 static void picoxcell_wdt_restart(char mode, const char *cmd)
 {
 	/*
@@ -95,7 +85,7 @@ static void picoxcell_wdt_restart(char mode, const char *cmd)
 DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
 	.map_io		= picoxcell_map_io,
 	.nr_irqs	= NR_IRQS_LEGACY,
-	.init_irq	= picoxcell_init_irq,
+	.init_irq	= vic_init_irq,
 	.handle_irq	= vic_handle_irq,
 	.timer		= &picoxcell_timer,
 	.init_machine	= picoxcell_init_machine,
arch/arm/mach-spear6xx/spear6xx.c +1 -11
index 2ed8b14..d436118 100644
@@ -102,19 +102,9 @@ static const char *spear600_dt_board_compat[] = {
 	NULL
 };
 
-static const struct of_device_id vic_of_match[] __initconst = {
-	{ .compatible = "arm,pl190-vic", .data = vic_of_init, },
-	{ /* Sentinel */ }
-};
-
-static void __init spear6xx_dt_init_irq(void)
-{
-	of_irq_init(vic_of_match);
-}
-
 DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
 	.map_io		=	spear6xx_map_io,
-	.init_irq	=	spear6xx_dt_init_irq,
+	.init_irq	=	vic_init_irq,
 	.handle_irq	=	vic_handle_irq,
 	.timer		=	&spear6xx_timer,
 	.init_machine	=	spear600_dt_init,
#6 lore raw

PATCH 1/2 ARM: VIC: Create common infrastructure for vic DT bindings

Quoted 4 lines · Rob Herring

NAK

None of these platforms have gpio interrupts or any other board interrupt controllers which need to be initialized early?

Atleast SPEAr600 have GPIO interrupts.

Quoted 1 line

I don't think DT conversions are complete enough to tell.

Couldn't get your comment, sorry.

Quoted 3 lines

We could do something like this, but there only needs to be a single match list of all controllers and function. We should consolidate the irqchips to drivers/irqchip first though. I have that action from Connect...

That would be good.
I am updating DT support for SPEAr3xx, where i need to use VIC OF support. So i would still like to get this patch going and you can consilidate code at irqchips level later. What do you say?

--
viresh

#7 lore raw

PATCH 1/2 ARM: VIC: Create common infrastructure for vic DT bindings

Quoted 11 lines · viresh kumar
Quoted 4 lines · Rob Herring

NAK

None of these platforms have gpio interrupts or any other board interrupt controllers which need to be initialized early?

Atleast SPEAr600 have GPIO interrupts.

Quoted 1 line

I don't think DT conversions are complete enough to tell.

Couldn't get your comment, sorry.

Some DT enabled platforms may only have the gic or vic included in their match list currently because other interrupt controllers aren't yet converted to DT. I believe Exynos is one such example.

Quoted 9 lines
Quoted 4 lines

We could do something like this, but there only needs to be a single match list of all controllers and function. We should consolidate the irqchips to drivers/irqchip first though. I have that action from Connect...

That would be good.
I am updating DT support for SPEAr3xx, where i need to use VIC OF support. So i would still like to get this patch going and you can consilidate code at irqchips level later. What do you say?

No. I don't think moving this into the gic and vic code just to move it back out later is a good idea. Just looking at the diffstat, the net number of lines removed is not very compelling either.

Rob

Quoted 3 lines

--
viresh