ARM: EXYNOS: support EXYNOS display driver

PATCH Superseded Donghwa Lee 2 participants 2 messages Apr 2, 2012

Subsystems (3)

Arm (32-bit) Framebuffer layer Arm Samsung Exynos

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Donghwa Lee

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2012-04-02 02:22 UTC #0 lore raw

PATCH v2 4/4 ARM: EXYNOS: support EXYNOS display driver

This patch is for EXYNOS Display driver.

Signed-off-by Donghwa Lee <[email protected]>

Signed-off-by Inki Dae <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 arch/arm/include/asm/arch-exynos/fb.h |  446 +++++++++++++++++++++++++++++++++
 drivers/video/Makefile                |    1 +
 drivers/video/exynos_fb.c             |  219 ++++++++++++++++
 drivers/video/exynos_fb.h             |   51 ++++
 drivers/video/exynos_fimd.c           |  357 ++++++++++++++++++++++++++
 5 files changed, 1074 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-exynos/fb.h
 create mode 100644 drivers/video/exynos_fb.c
 create mode 100644 drivers/video/exynos_fb.h
 create mode 100644 drivers/video/exynos_fimd.c

arch/arm/include/asm/arch-exynos/fb.h new file +446 -0

new file mode 100644
index 0000000..b10b0da
@@ -0,0 +1,446 @@
+/*
+ * (C) Copyright 2012 Samsung Electronics
+ * Donghwa Lee <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * aint with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_FB_H_
+#define __ASM_ARM_ARCH_FB_H_
+
+#ifndef __ASSEMBLY__
+struct exynos4_fb {
+	unsigned int vidcon0;
+	unsigned int vidcon1;
+	unsigned int vidcon2;
+	unsigned int vidcon3;
+	unsigned int vidtcon0;
+	unsigned int vidtcon1;
+	unsigned int vidtcon2;
+	unsigned int vidtcon3;
+	unsigned int wincon0;
+	unsigned int wincon1;
+	unsigned int wincon2;
+	unsigned int wincon3;
+	unsigned int wincon4;
+
+	unsigned int winshmap;
+	unsigned int res1;
+
+	unsigned int winchmap2;
+	unsigned int vidosd0a;
+	unsigned int vidosd0b;
+	unsigned int vidosd0c;
+	unsigned int res2;
+
+	unsigned int vidosd1a;
+	unsigned int vidosd1b;
+	unsigned int vidosd1c;
+	unsigned int vidosd1d;
+
+	unsigned int vidosd2a;
+	unsigned int vidosd2b;
+	unsigned int vidosd2c;
+	unsigned int vidosd2d;
+
+	unsigned int vidosd3a;
+	unsigned int vidosd3b;
+	unsigned int vidosd3c;
+	unsigned int res3;
+
+	unsigned int vidosd4a;
+	unsigned int vidosd4b;
+	unsigned int vidosd4c;
+	unsigned int res4[5];
+
+	unsigned int vidw00add0b0;
+	unsigned int vidw00add0b1;
+	unsigned int vidw01add0b0;
+	unsigned int vidw01add0b1;
+
+	unsigned int vidw02add0b0;
+	unsigned int vidw02add0b1;
+	unsigned int vidw03add0b0;
+	unsigned int vidw03add0b1;
+	unsigned int vidw04add0b0;
+	unsigned int vidw04add0b1;
+	unsigned int res5[2];
+
+	unsigned int vidw00add1b0;
+	unsigned int vidw00add1b1;
+	unsigned int vidw01add1b0;
+	unsigned int vidw01add1b1;
+
+	unsigned int vidw02add1b0;
+	unsigned int vidw02add1b1;
+	unsigned int vidw03add1b0;
+	unsigned int vidw03add1b1;
+
+	unsigned int vidw04add1b0;
+	unsigned int vidw04add1b1;
+	unsigned int res7[2];
+
+	unsigned int vidw00add2;
+	unsigned int vidw01add2;
+	unsigned int vidw02add2;
+	unsigned int vidw03add2;
+	unsigned int vidw04add2;
+	unsigned int res8[7];
+
+	unsigned int vidintcon0;
+	unsigned int vidintcon1;
+	unsigned int res9[1];
+
+	unsigned int w1keycon0;
+	unsigned int w1keycon1;
+	unsigned int w2keycon0;
+	unsigned int w2keycon1;
+	unsigned int w3keycon0;
+	unsigned int w3keycon1;
+	unsigned int w4keycon0;
+	unsigned int w4keycon1;
+
+	unsigned int w1keyalpha;
+	unsigned int w2keyalpha;
+	unsigned int w3keyalpha;
+	unsigned int w4keyalpha;
+
+	unsigned int dithmode;
+	unsigned int res10[2];
+
+	unsigned int win0map;
+	unsigned int win1map;
+	unsigned int win2map;
+	unsigned int win3map;
+	unsigned int win4map;
+	unsigned int res11[1];
+
+	unsigned int wpalcon_h;
+	unsigned int wpalcon_l;
+
+	unsigned int trigcon;
+	unsigned int res12[2];
+
+	unsigned int i80ifcona0;
+	unsigned int i80ifcona1;
+	unsigned int i80ifconb0;
+	unsigned int i80ifconb1;
+
+	unsigned int colorgaincon;
+	unsigned int res13[2];
+
+	unsigned int ldi_cmdcon0;
+	unsigned int ldi_cmdcon1;
+	unsigned int res14[1];
+
+	/* To be updated */
+
+	unsigned char res15[156];
+	unsigned int dualrgb;
+};
+#endif
+
+/*
+ *  Register offsets
+*/
+#define EXYNOS_WINCON(x)				(x * 0x04)
+#define EXYNOS_VIDOSD(x)				(x * 0x10)
+#define EXYNOS_BUFFER_OFFSET(x)				(x * 0x08)
+#define EXYNOS_BUFFER_SIZE(x)				(x * 0x04)
+
+/*
+ * Bit Definitions
+*/
+
+/* VIDCON0 */
+#define EXYNOS_VIDCON0_DSI_DISABLE			(0 << 30)
+#define EXYNOS_VIDCON0_DSI_ENABLE			(1 << 30)
+#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE			(0 << 29)
+#define EXYNOS_VIDCON0_SCAN_INTERLACE			(1 << 29)
+#define EXYNOS_VIDCON0_SCAN_MASK			(1 << 29)
+#define EXYNOS_VIDCON0_VIDOUT_RGB			(0 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_ITU			(1 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI0			(2 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_I80LDI1			(3 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_RGB			(4 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0		(6 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1		(7 << 26)
+#define EXYNOS_VIDCON0_VIDOUT_MASK			(7 << 26)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_P			(0 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_P			(1 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_RGB_S			(2 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_BGR_S			(3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_MASK			(3 << 17)
+#define EXYNOS_VIDCON0_PNRMODE_SHIFT			(17)
+#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS			(0 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME		(1 << 16)
+#define EXYNOS_VIDCON0_CLKVALUP_MASK			(1 << 16)
+#define EXYNOS_VIDCON0_CLKVAL_F(x)			(((x) & 0xff) << 6)
+#define EXYNOS_VIDCON0_VCLKEN_NORMAL			(0 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_FREERUN			(1 << 5)
+#define EXYNOS_VIDCON0_VCLKEN_MASK			(1 << 5)
+#define EXYNOS_VIDCON0_CLKDIR_DIRECTED			(0 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_DIVIDED			(1 << 4)
+#define EXYNOS_VIDCON0_CLKDIR_MASK			(1 << 4)
+#define EXYNOS_VIDCON0_CLKSEL_HCLK			(0 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_SCLK			(1 << 2)
+#define EXYNOS_VIDCON0_CLKSEL_MASK			(1 << 2)
+#define EXYNOS_VIDCON0_ENVID_ENABLE			(1 << 1)
+#define EXYNOS_VIDCON0_ENVID_DISABLE			(0 << 1)
+#define EXYNOS_VIDCON0_ENVID_F_ENABLE			(1 << 0)
+#define EXYNOS_VIDCON0_ENVID_F_DISABLE			(0 << 0)
+
+/* VIDCON1 */
+#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE		(0 << 7)
+#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE		(1 << 7)
+#define EXYNOS_VIDCON1_IHSYNC_NORMAL			(0 << 6)
+#define EXYNOS_VIDCON1_IHSYNC_INVERT			(1 << 6)
+#define EXYNOS_VIDCON1_IVSYNC_NORMAL			(0 << 5)
+#define EXYNOS_VIDCON1_IVSYNC_INVERT			(1 << 5)
+#define EXYNOS_VIDCON1_IVDEN_NORMAL			(0 << 4)
+#define EXYNOS_VIDCON1_IVDEN_INVERT			(1 << 4)
+
+/* VIDCON2 */
+#define EXYNOS_VIDCON2_EN601_DISABLE			(0 << 23)
+#define EXYNOS_VIDCON2_EN601_ENABLE			(1 << 23)
+#define EXYNOS_VIDCON2_EN601_MASK			(1 << 23)
+#define EXYNOS_VIDCON2_WB_DISABLE			(0 << 15)
+#define EXYNOS_VIDCON2_WB_ENABLE			(1 << 15)
+#define EXYNOS_VIDCON2_WB_MASK				(1 << 15)
+#define EXYNOS_VIDCON2_TVFORMATSEL_HW			(0 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_SW			(1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_MASK			(1 << 14)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422		(1 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444		(2 << 12)
+#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK		(3 << 12)
+#define EXYNOS_VIDCON2_ORGYUV_YCBCR			(0 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_CBCRY			(1 << 8)
+#define EXYNOS_VIDCON2_ORGYUV_MASK			(1 << 8)
+#define EXYNOS_VIDCON2_YUVORD_CBCR			(0 << 7)
+#define EXYNOS_VIDCON2_YUVORD_CRCB			(1 << 7)
+#define EXYNOS_VIDCON2_YUVORD_MASK			(1 << 7)
+
+/* PRTCON */
+#define EXYNOS_PRTCON_UPDATABLE				(0 << 11)
+#define EXYNOS_PRTCON_PROTECT				(1 << 11)
+
+/* VIDTCON0 */
+#define EXYNOS_VIDTCON0_VBPDE(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON0_VBPD(x)				(((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON0_VFPD(x)				(((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON0_VSPW(x)				(((x) & 0xff) << 0)
+
+/* VIDTCON1 */
+#define EXYNOS_VIDTCON1_VFPDE(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDTCON1_HBPD(x)				(((x) & 0xff) << 16)
+#define EXYNOS_VIDTCON1_HFPD(x)				(((x) & 0xff) << 8)
+#define EXYNOS_VIDTCON1_HSPW(x)				(((x) & 0xff) << 0)
+
+/* VIDTCON2 */
+#define EXYNOS_VIDTCON2_LINEVAL(x)			(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDTCON2_HOZVAL(x)			(((x) & 0x7ff) << 0)
+
+/* Window 0~4 Control - WINCONx */
+#define EXYNOS_WINCON_DATAPATH_DMA			(0 << 22)
+#define EXYNOS_WINCON_DATAPATH_LOCAL			(1 << 22)
+#define EXYNOS_WINCON_DATAPATH_MASK			(1 << 22)
+#define EXYNOS_WINCON_BUFSEL_0				(0 << 20)
+#define EXYNOS_WINCON_BUFSEL_1				(1 << 20)
+#define EXYNOS_WINCON_BUFSEL_MASK			(1 << 20)
+#define EXYNOS_WINCON_BUFSEL_SHIFT			(20)
+#define EXYNOS_WINCON_BUFAUTO_DISABLE			(0 << 19)
+#define EXYNOS_WINCON_BUFAUTO_ENABLE			(1 << 19)
+#define EXYNOS_WINCON_BUFAUTO_MASK			(1 << 19)
+#define EXYNOS_WINCON_BITSWP_DISABLE			(0 << 18)
+#define EXYNOS_WINCON_BITSWP_ENABLE			(1 << 18)
+#define EXYNOS_WINCON_BITSWP_SHIFT			(18)
+#define EXYNOS_WINCON_BYTESWP_DISABLE			(0 << 17)
+#define EXYNOS_WINCON_BYTESWP_ENABLE			(1 << 17)
+#define EXYNOS_WINCON_BYTESWP_SHIFT			(17)
+#define EXYNOS_WINCON_HAWSWP_DISABLE			(0 << 16)
+#define EXYNOS_WINCON_HAWSWP_ENABLE			(1 << 16)
+#define EXYNOS_WINCON_HAWSWP_SHIFT			(16)
+#define EXYNOS_WINCON_WSWP_DISABLE			(0 << 15)
+#define EXYNOS_WINCON_WSWP_ENABLE			(1 << 15)
+#define EXYNOS_WINCON_WSWP_SHIFT			(15)
+#define EXYNOS_WINCON_INRGB_RGB				(0 << 13)
+#define EXYNOS_WINCON_INRGB_YUV				(1 << 13)
+#define EXYNOS_WINCON_INRGB_MASK			(1 << 13)
+#define EXYNOS_WINCON_BURSTLEN_16WORD			(0 << 9)
+#define EXYNOS_WINCON_BURSTLEN_8WORD			(1 << 9)
+#define EXYNOS_WINCON_BURSTLEN_4WORD			(2 << 9)
+#define EXYNOS_WINCON_BURSTLEN_MASK			(3 << 9)
+#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE		(0 << 7)
+#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE		(1 << 7)
+#define EXYNOS_WINCON_BLD_PLANE				(0 << 6)
+#define EXYNOS_WINCON_BLD_PIXEL				(1 << 6)
+#define EXYNOS_WINCON_BLD_MASK				(1 << 6)
+#define EXYNOS_WINCON_BPPMODE_1BPP			(0 << 2)
+#define EXYNOS_WINCON_BPPMODE_2BPP			(1 << 2)
+#define EXYNOS_WINCON_BPPMODE_4BPP			(2 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP_PAL			(3 << 2)
+#define EXYNOS_WINCON_BPPMODE_8BPP			(4 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_565			(5 << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A555		(6 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_666			(8 << 2)
+#define EXYNOS_WINCON_BPPMODE_18BPP_A665		(9 << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_888			(0xb << 2)
+#define EXYNOS_WINCON_BPPMODE_24BPP_A887		(0xc << 2)
+#define EXYNOS_WINCON_BPPMODE_32BPP			(0xd << 2)
+#define EXYNOS_WINCON_BPPMODE_16BPP_A444		(0xe << 2)
+#define EXYNOS_WINCON_BPPMODE_15BPP_555			(0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_MASK			(0xf << 2)
+#define EXYNOS_WINCON_BPPMODE_SHIFT			(2)
+#define EXYNOS_WINCON_ALPHA0_SEL			(0 << 1)
+#define EXYNOS_WINCON_ALPHA1_SEL			(1 << 1)
+#define EXYNOS_WINCON_ALPHA_SEL_MASK			(1 << 1)
+#define EXYNOS_WINCON_ENWIN_DISABLE			(0 << 0)
+#define EXYNOS_WINCON_ENWIN_ENABLE			(1 << 0)
+
+/* WINCON1 special */
+#define EXYNOS_WINCON1_VP_DISABLE			(0 << 24)
+#define EXYNOS_WINCON1_VP_ENABLE			(1 << 24)
+#define EXYNOS_WINCON1_LOCALSEL_FIMC1			(0 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_VP			(1 << 23)
+#define EXYNOS_WINCON1_LOCALSEL_MASK			(1 << 23)
+
+/* WINSHMAP */
+#define EXYNOS_WINSHMAP_PROTECT(x)			(((x) & 0x1f) << 10)
+#define EXYNOS_WINSHMAP_CH_ENABLE(x)			(1 << (x))
+#define EXYNOS_WINSHMAP_CH_DISABLE(x)			(1 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x)			(0x20 << (x))
+#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x)		(0x20 << (x))
+
+/* VIDOSDxA, VIDOSDxB */
+#define EXYNOS_VIDOSD_LEFT_X(x)				(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_TOP_Y(x)				(((x) & 0x7ff) << 0)
+#define EXYNOS_VIDOSD_RIGHT_X(x)			(((x) & 0x7ff) << 11)
+#define EXYNOS_VIDOSD_BOTTOM_Y(x)			(((x) & 0x7ff) << 0)
+
+/* VIDOSD0C, VIDOSDxD */
+#define EXYNOS_VIDOSD_SIZE(x)				(((x) & 0xffffff) << 0)
+
+/* VIDOSDxC (1~4) */
+#define EXYNOS_VIDOSD_ALPHA0_R(x)			(((x) & 0xf) << 20)
+#define EXYNOS_VIDOSD_ALPHA0_G(x)			(((x) & 0xf) << 16)
+#define EXYNOS_VIDOSD_ALPHA0_B(x)			(((x) & 0xf) << 12)
+#define EXYNOS_VIDOSD_ALPHA1_R(x)			(((x) & 0xf) << 8)
+#define EXYNOS_VIDOSD_ALPHA1_G(x)			(((x) & 0xf) << 4)
+#define EXYNOS_VIDOSD_ALPHA1_B(x)			(((x) & 0xf) << 0)
+#define EXYNOS_VIDOSD_ALPHA0_SHIFT			(12)
+#define EXYNOS_VIDOSD_ALPHA1_SHIFT			(0)
+
+/* Start Address */
+#define EXYNOS_VIDADDR_START_VBANK(x)			(((x) & 0xff) << 24)
+#define EXYNOS_VIDADDR_START_VBASEU(x)			(((x) & 0xffffff) << 0)
+
+/* End Address */
+#define EXYNOS_VIDADDR_END_VBASEL(x)			(((x) & 0xffffff) << 0)
+
+/* Buffer Size */
+#define EXYNOS_VIDADDR_OFFSIZE(x)			(((x) & 0x1fff) << 13)
+#define EXYNOS_VIDADDR_PAGEWIDTH(x)			(((x) & 0x1fff) << 0)
+
+/* WIN Color Map */
+#define EXYNOS_WINMAP_COLOR(x)				((x) & 0xffffff)
+
+/* VIDINTCON0 */
+#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE		(0 << 19)
+#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE		(1 << 19)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE		(0 << 18)
+#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE		(1 << 18)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE		(0 << 17)
+#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE		(1 << 17)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK		(0 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC		(1 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE		(2 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT		(3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK		(3 << 15)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE		(0 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK		(1 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC		(2 << 13)
+#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT		(3 << 13)
+#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE		(0 << 12)
+#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE		(1 << 12)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4			(1 << 11)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3			(1 << 10)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2			(1 << 9)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1			(1 << 6)
+#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0			(1 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_ALL			(0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOSEL_MASK			(0x73 << 5)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_25			(0 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_50			(1 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_75			(2 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY		(3 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL		(4 << 2)
+#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK		(7 << 2)
+#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE		(0 << 1)
+#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE		(1 << 1)
+#define EXYNOS_VIDINTCON0_INT_DISABLE			(0 << 0)
+#define EXYNOS_VIDINTCON0_INT_ENABLE			(1 << 0)
+#define EXYNOS_VIDINTCON0_INT_MASK			(1 << 0)
+
+/* VIDINTCON1 */
+#define EXYNOS_VIDINTCON1_INTVPPEND			(1 << 5)
+#define EXYNOS_VIDINTCON1_INTI80PEND			(1 << 2)
+#define EXYNOS_VIDINTCON1_INTFRMPEND			(1 << 1)
+#define EXYNOS_VIDINTCON1_INTFIFOPEND			(1 << 0)
+
+/* WINMAP */
+#define EXYNOS_WINMAP_ENABLE				(1 << 24)
+
+/* WxKEYCON0 (1~4) */
+#define EXYNOS_KEYCON0_KEYBLEN_DISABLE			(0 << 26)
+#define EXYNOS_KEYCON0_KEYBLEN_ENABLE			(1 << 26)
+#define EXYNOS_KEYCON0_KEY_DISABLE			(0 << 25)
+#define EXYNOS_KEYCON0_KEY_ENABLE			(1 << 25)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_FG			(0 << 24)
+#define EXYNOS_KEYCON0_DIRCON_MATCH_BG			(1 << 24)
+#define EXYNOS_KEYCON0_COMPKEY(x)			(((x) & 0xffffff) << 0)
+
+/* WxKEYCON1 (1~4) */
+#define EXYNOS_KEYCON1_COLVAL(x)			(((x) & 0xffffff) << 0)
+
+/* DUALRGB */
+#define EXYNOS_DUALRGB_BYPASS_SINGLE			(0x00 << 0)
+#define EXYNOS_DUALRGB_BYPASS_DUAL			(0x01 << 0)
+#define EXYNOS_DUALRGB_MIE_DUAL				(0x10 << 0)
+#define EXYNOS_DUALRGB_MIE_SINGLE			(0x11 << 0)
+#define EXYNOS_DUALRGB_LINESPLIT			(0x0 << 2)
+#define EXYNOS_DUALRGB_FRAMESPLIT			(0x1 << 2)
+#define EXYNOS_DUALRGB_SUB_CNT(x)			((x & 0xfff) << 4)
+#define EXYNOS_DUALRGB_VDEN_EN_DISABLE			(0x0 << 16)
+#define EXYNOS_DUALRGB_VDEN_EN_ENABLE			(0x1 << 16)
+#define EXYNOS_DUALRGB_MAIN_CNT(x)			((x & 0xfff) << 18)
+
+/* I80IFCONA0 and I80IFCONA1 */
+#define EXYNOS_LCD_CS_SETUP(x)				(((x) & 0xf) << 16)
+#define EXYNOS_LCD_WR_SETUP(x)				(((x) & 0xf) << 12)
+#define EXYNOS_LCD_WR_ACT(x)				(((x) & 0xf) << 8)
+#define EXYNOS_LCD_WR_HOLD(x)				(((x) & 0xf) << 4)
+#define EXYNOS_RSPOL_LOW				(0 << 2)
+#define EXYNOS_RSPOL_HIGH				(1 << 2)
+#define EXYNOS_I80IFEN_DISABLE				(0 << 0)
+#define EXYNOS_I80IFEN_ENABLE				(1 << 0)
+
+/* TRIGCON */
+#define EXYNOS_I80SOFT_TRIG_EN				(1 << 0)
+#define EXYNOS_I80START_TRIG				(1 << 1)
+#define EXYNOS_I80STATUS_TRIG_DONE			(1 << 2)
+
+#endif /* _REGS_FB_H */

drivers/video/Makefile +1 -0

index 6252f6a..8896abe 100644
@@ -28,6 +28,7 @@ LIB	:= $(obj)libvideo.o
 COBJS-$(CONFIG_ATI_RADEON_FB) += ati_radeon_fb.o videomodes.o
 COBJS-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
 COBJS-$(CONFIG_CFB_CONSOLE) += cfb_console.o
+COBJS-$(CONFIG_EXYNOS_FB) += exynos_fb.o exynos_fimd.o
 COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
 COBJS-$(CONFIG_S6E63D6) += s6e63d6.o
 COBJS-$(CONFIG_SED156X) += sed156x.o

drivers/video/exynos_fb.c new file +219 -0

219 lines not on this page · raw message

drivers/video/exynos_fb.h new file +51 -0

51 lines not on this page · raw message

drivers/video/exynos_fimd.c new file +357 -0

357 lines not on this page · raw message

Signature · 1 line

1.7.4.1

Minkyu Kang

2012-04-02 04:49 UTC #1 lore raw

PATCH v2 4/4 ARM: EXYNOS: support EXYNOS display driver

Quoted 24 lines · Donghwa Lee

This patch is for EXYNOS Display driver.
Signed-off-by Donghwa Lee <[email protected]>
Signed-off-by Inki Dae <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
?arch/arm/include/asm/arch-exynos/fb.h | ?446 +++++++++++++++++++++++++++++++++
?drivers/video/Makefile ? ? ? ? ? ? ? ?| ? ?1 +
?drivers/video/exynos_fb.c ? ? ? ? ? ? | ?219 ++++++++++++++++
?drivers/video/exynos_fb.h ? ? ? ? ? ? | ? 51 ++++
?drivers/video/exynos_fimd.c ? ? ? ? ? | ?357 ++++++++++++++++++++++++++
?5 files changed, 1074 insertions(+), 0 deletions(-) ?create mode 100644 arch/arm/include/asm/arch-exynos/fb.h ?create mode 100644 drivers/video/exynos_fb.c ?create mode 100644 drivers/video/exynos_fb.h ?create mode 100644 drivers/video/exynos_fimd.c
drivers/video/exynos_fb.c new file +0 -0
new file mode 100644
index 0000000..43210dc

drivers/video/exynos_fb.c line 3

Quoted 3 lines

drivers/video/exynos_fb.c new file +3 -0
@@ -0,0 +1,219 @@
+void lcd_ctrl_init(void *lcdbase)
+{
+

dead space

Quoted 81 lines

drivers/video/exynos_fb.c new file +34 -0

+ ? ? ? set_system_display_ctrl();
+ ? ? ? set_lcd_clk();
+
+ ? ? ? /* initialize parameters which is specific to panel. */
+ ? ? ? init_panel_info(&panel_info);
+
+ ? ? ? panel_width = panel_info.vl_width;
+ ? ? ? panel_height = panel_info.vl_height;
+
+ ? ? ? exynos_lcd_init_mem(lcdbase, &panel_info);
+
+ ? ? ? memset(lcdbase, 0, panel_width * panel_height * (32 >> 3));
+
+ ? ? ? draw_samsung_logo(lcdbase);
+
+ ? ? ? exynos_lcd_init(&panel_info);
+}
+
+void lcd_enable(void)
+{
+ ? ? ? lcd_panel_on(&panel_info);
+}
+
+ulong calc_fbsize(void)
+{
+ ? ? ? return exynos_fimd_calc_fbsize();
+}
+
+/* dummy function */
+void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
+{
+ ? ? ? return;
+}
+

drivers/video/exynos_fb.h new file +41 -0

new file mode 100644
index 0000000..e513f7a
@@ -0,0 +1,51 @@
+/*
+ * drivers/video/exynos_fb.h
+ *
+ * Copyright (C) 2012 Donghwa Lee <[email protected]>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. ?See the file COPYING in the main directory of this archive for
+ * more details.
+ *
+ * ? ? EXYNOS Frame Buffer Driver
+ * ? ? based on skeletonfb.c, sa1100fb.h, s3c2410fb.c
+ */
+
+#ifndef _EXYNOS_FB_H_
+#define _EXYNOS_FB_H_
+
+#define MAX_CLOCK ? ? ?(86 * 1000000)
+
+enum exynos_fb_rgb_mode_t {
+ ? ? ? MODE_RGB_P = 0,
+ ? ? ? MODE_BGR_P = 1,
+ ? ? ? MODE_RGB_S = 2,
+ ? ? ? MODE_BGR_S = 3,
+};
+
+enum exynos_cpu_auto_cmd_rate {
+ ? ? ? DISABLE_AUTO_FRM,
+ ? ? ? PER_TWO_FRM,
+ ? ? ? PER_FOUR_FRM,
+ ? ? ? PER_SIX_FRM,
+ ? ? ? PER_EIGHT_FRM,
+ ? ? ? PER_TEN_FRM,
+ ? ? ? PER_TWELVE_FRM,
+ ? ? ? PER_FOURTEEN_FRM,
+ ? ? ? PER_SIXTEEN_FRM,
+ ? ? ? PER_EIGHTEEN_FRM,
+ ? ? ? PER_TWENTY_FRM,
+ ? ? ? PER_TWENTY_TWO_FRM,
+ ? ? ? PER_TWENTY_FOUR_FRM,
+ ? ? ? PER_TWENTY_SIX_FRM,
+ ? ? ? PER_TWENTY_EIGHT_FRM,

drivers/video/exynos_fb.h line 51

Quoted 10 lines

drivers/video/exynos_fb.h new file +10 -0

+ ? ? ? PER_THIRTY_FRM,
+};
+
+void exynos_fimd_lcd_init_mem(unsigned long screen_base, unsigned long fb_size,
+ ? ? ? unsigned long palette_size);
+void exynos_fimd_lcd_init(vidinfo_t *vid);
+unsigned long exynos_fimd_calc_fbsize(void);
+
+#endif
+

dead space.

Quoted 42 lines

drivers/video/exynos_fimd.c new file +36 -0

new file mode 100644
index 0000000..cfe5940
@@ -0,0 +1,357 @@
+/*
+ * exynos LCD Controller Specific driver.
+ *
+ * Author: InKi Dae <[email protected]>
+ * Author: Donghwa Lee <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ? ? ? ? See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <common.h>
+#include <stdarg.h>
+#include <linux/types.h>
+#include <asm/io.h>
+#include <lcd.h>
+#include <div64.h>
+
+#include <asm/arch/clk.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/fb.h>
+#include <asm/arch/gpio.h>
+#include "exynos_fb.h"

drivers/video/exynos_fimd.c line 46

Quoted 10 lines

drivers/video/exynos_fimd.c new file +10 -0

+
+static unsigned long *lcd_base_addr;
+static vidinfo_t *pvid;
+
+void exynos_fimd_lcd_init_mem(u_long screen_base, u_long fb_size,
+ ? ? ? ? ? ? ? u_long palette_size)
+{
+ ? ? ? lcd_base_addr = (unsigned long *)screen_base;
+
+ ? ? ? return;

no need return.

Quoted 82 lines

drivers/video/exynos_fimd.c new file +82 -0

+}
+
+static void exynos_fimd_set_dualrgb(unsigned int enabled)
+{
+ ? ? ? struct exynos4_fb *fimd_ctrl =
+ ? ? ? ? ? ? ? (struct exynos4_fb *)samsung_get_base_fimd();
+ ? ? ? unsigned int cfg = 0;
+
+ ? ? ? if (enabled) {
+ ? ? ? ? ? ? ? cfg = EXYNOS_DUALRGB_BYPASS_DUAL | EXYNOS_DUALRGB_LINESPLIT |
+ ? ? ? ? ? ? ? ? ? ? ? EXYNOS_DUALRGB_VDEN_EN_ENABLE;
+
+ ? ? ? ? ? ? ? /* in case of Line Split mode, MAIN_CNT doesn't neet to set. */
+ ? ? ? ? ? ? ? cfg |= EXYNOS_DUALRGB_SUB_CNT(pvid->vl_col / 2) |
+ ? ? ? ? ? ? ? ? ? ? ? EXYNOS_DUALRGB_MAIN_CNT(0);
+ ? ? ? }
+
+ ? ? ? writel(cfg, &fimd_ctrl->dualrgb);
+}
+
+static void exynos_fimd_set_par(unsigned int win_id)
+{
+ ? ? ? unsigned int cfg = 0;
+ ? ? ? struct exynos4_fb *fimd_ctrl =
+ ? ? ? ? ? ? ? (struct exynos4_fb *)samsung_get_base_fimd();
+ ? ? ? unsigned long temp = win_id * 4;
+
+ ? ? ? /* set window control */
+ ? ? ? cfg = readl((unsigned int)&fimd_ctrl->wincon0 + EXYNOS_WINCON(win_id));
+
+ ? ? ? cfg &= ~(EXYNOS_WINCON_BITSWP_ENABLE | EXYNOS_WINCON_BYTESWP_ENABLE |
+ ? ? ? ? ? ? ? EXYNOS_WINCON_HAWSWP_ENABLE | EXYNOS_WINCON_WSWP_ENABLE |
+ ? ? ? ? ? ? ? EXYNOS_WINCON_BURSTLEN_MASK | EXYNOS_WINCON_BPPMODE_MASK |
+ ? ? ? ? ? ? ? EXYNOS_WINCON_INRGB_MASK | EXYNOS_WINCON_DATAPATH_MASK);
+
+ ? ? ? /* DATAPATH is DMA */
+ ? ? ? cfg |= EXYNOS_WINCON_DATAPATH_DMA;
+
+ ? ? ? /* bpp is 32 */
+ ? ? ? cfg |= EXYNOS_WINCON_WSWP_ENABLE;
+
+ ? ? ? /* dma burst is 16 */
+ ? ? ? cfg |= EXYNOS_WINCON_BURSTLEN_16WORD;
+
+ ? ? ? /* pixel format is unpacked RGB888 */
+ ? ? ? cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888;
+
+ ? ? ? writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + EXYNOS_WINCON(win_id));
+
+ ? ? ? /* set window position to x=0, y=0*/
+ ? ? ? cfg = EXYNOS_VIDOSD_LEFT_X(0) | EXYNOS_VIDOSD_TOP_Y(0);
+ ? ? ? writel(cfg, (unsigned int)&fimd_ctrl->vidosd0a + EXYNOS_VIDOSD(win_id));
+
+ ? ? ? cfg = EXYNOS_VIDOSD_RIGHT_X(pvid->vl_col - 1) |
+ ? ? ? ? ? ? ? EXYNOS_VIDOSD_BOTTOM_Y(pvid->vl_row - 1);
+ ? ? ? writel(cfg, (unsigned int)&fimd_ctrl->vidosd0b + EXYNOS_VIDOSD(win_id));
+
+ ? ? ? /* set window size for window0*/
+ ? ? ? cfg = EXYNOS_VIDOSD_SIZE(pvid->vl_col * pvid->vl_row);
+ ? ? ? writel(cfg, (unsigned int)&fimd_ctrl->vidosd0c + EXYNOS_VIDOSD(win_id));
+}
+
+static void exynos_fimd_set_buffer_address(unsigned int win_id)
+{
+ ? ? ? unsigned long start_addr, end_addr;
+ ? ? ? struct exynos4_fb *fimd_ctrl =
+ ? ? ? ? ? ? ? (struct exynos4_fb *)samsung_get_base_fimd();
+
+ ? ? ? start_addr = (unsigned long)lcd_base_addr;
+ ? ? ? end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8))
+ ? ? ? ? ? ? ? * pvid->vl_row);
+
+ ? ? ? writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 +
+ ? ? ? ? ? ? ? ? ? ? ? EXYNOS_BUFFER_OFFSET(win_id));
+ ? ? ? writel(end_addr, (unsigned int)&fimd_ctrl->vidw00add1b0 +
+ ? ? ? ? ? ? ? ? ? ? ? EXYNOS_BUFFER_OFFSET(win_id));
+}
+
+static void exynos_fimd_set_clock(vidinfo_t *pvid)
+{
+ ? ? ? unsigned int cfg = 0, div = 0, remainder, remainder_div;
+ ? ? ? unsigned long pixel_clock, src_clock;

drivers/video/exynos_fimd.c line 138

Quoted 10 lines

drivers/video/exynos_fimd.c new file +10 -0

+ ? ? ? struct exynos4_fb *fimd_ctrl =
+ ? ? ? ? ? ? ? (struct exynos4_fb *)samsung_get_base_fimd();
+ ? ? ? u64 div64;
+
+ ? ? ? if (get_pll_clk == NULL) {
+ ? ? ? ? ? ? ? printf("get_pll_clk is null.\n");
+ ? ? ? ? ? ? ? return;
+ ? ? ? }
+
+ ? ? ? if (pvid->dual_lcd_enabled)

need brace.

drivers/video/exynos_fimd.c line 142

Quoted 4 lines

drivers/video/exynos_fimd.c new file +4 -0

+ ? ? ? ? ? ? ? pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
+ ? ? ? ? ? ? ? ? ? ? ? pvid->vl_hbpd + pvid->vl_col / 2) * (pvid->vl_vspw +
+ ? ? ? ? ? ? ? ? ? ? ? ? ? pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
+ ? ? ? else if (pvid->interface_mode == FIMD_CPU_INTERFACE)

need brace.

drivers/video/exynos_fimd.c line 146

Quoted 4 lines

drivers/video/exynos_fimd.c new file +4 -0

+ ? ? ? ? ? ? ? pixel_clock = pvid->vl_freq * pvid->vl_width * pvid->vl_height *
+ ? ? ? ? ? ? ? ? ? (pvid->cs_setup + pvid->wr_setup + pvid->wr_act +
+ ? ? ? ? ? ? ? ? ? ? ? pvid->wr_hold + 1);
+ ? ? ? else

need brace.

Quoted 29 lines

drivers/video/exynos_fimd.c new file +29 -0

+ ? ? ? ? ? ? ? pixel_clock = pvid->vl_freq * (pvid->vl_hspw + pvid->vl_hfpd +
+ ? ? ? ? ? ? ? ? ? ? ? pvid->vl_hbpd + pvid->vl_col) * (pvid->vl_vspw +
+ ? ? ? ? ? ? ? ? ? ? ? ? ? pvid->vl_vfpd + pvid->vl_vbpd + pvid->vl_row);
+
+ ? ? ? src_clock = get_lcd_clk();
+
+ ? ? ? cfg = readl(&fimd_ctrl->vidcon0);
+ ? ? ? cfg &= ~(EXYNOS_VIDCON0_CLKSEL_MASK | EXYNOS_VIDCON0_CLKVALUP_MASK |
+ ? ? ? ? ? ? ? EXYNOS_VIDCON0_CLKVAL_F(0xFF) |
+ ? ? ? ? ? ? ? EXYNOS_VIDCON0_VCLKEN_MASK | EXYNOS_VIDCON0_CLKDIR_MASK);
+ ? ? ? cfg |= (EXYNOS_VIDCON0_CLKSEL_SCLK | EXYNOS_VIDCON0_CLKVALUP_ALWAYS |
+ ? ? ? ? ? ? ? EXYNOS_VIDCON0_VCLKEN_NORMAL | EXYNOS_VIDCON0_CLKDIR_DIVIDED);
+
+ ? ? ? if (pixel_clock > MAX_CLOCK)
+ ? ? ? ? ? ? ? pixel_clock = MAX_CLOCK;
+
+ ? ? ? div64 = (u64)get_lcd_clk();
+
+ ? ? ? /* get quotient and remainder. */
+ ? ? ? remainder = do_div(div64, pixel_clock);
+ ? ? ? div = (u32) div64;
+
+ ? ? ? remainder *= 10;
+ ? ? ? remainder_div = remainder / pixel_clock;
+
+ ? ? ? /* round about one places of decimals. */
+ ? ? ? if (remainder_div >= 5)
+ ? ? ? ? ? ? ? div++;
+

drivers/video/exynos_fimd.c line 185

Quoted 10 lines

drivers/video/exynos_fimd.c new file +10 -0

+ ? ? ? /* in case of dual lcd mode. */
+ ? ? ? if (pvid->dual_lcd_enabled)
+ ? ? ? ? ? ? ? div--;
+
+ ? ? ? cfg |= EXYNOS_VIDCON0_CLKVAL_F(div - 1);
+ ? ? ? writel(cfg, &fimd_ctrl->vidcon0);
+}
+
+void exynos_set_trigger(void)
+

dead space

drivers/video/exynos_fimd.c line 197

Quoted 12 lines

drivers/video/exynos_fimd.c new file +12 -0

+{
+ ? ? ? unsigned int cfg = 0;
+ ? ? ? struct exynos4_fb *fimd_ctrl =
+ ? ? ? ? ? ? ? (struct exynos4_fb *)samsung_get_base_fimd();
+
+ ? ? ? cfg = readl(&fimd_ctrl->trigcon);
+
+ ? ? ? cfg |= EXYNOS_I80SOFT_TRIG_EN | EXYNOS_I80START_TRIG;
+
+ ? ? ? writel(cfg, &fimd_ctrl->trigcon);
+}
+

Thanks,
Minkyu Kang.

Signature · 2 lines

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