ARM: EXYNOS: add exynos lcd clock interface
Subsystems (2)
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PATCH v3 3/4 ARM: EXYNOS: add exynos lcd clock interface
To get lcd clock in EXYNOS display driver, added get_lcd_clk() interface.
Signed-off-by Donghwa Lee <[email protected]>
Signed-off-by Inki Dae <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
--- arch/arm/cpu/armv7/exynos/clock.c | 79 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 2 + 2 files changed, 81 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/exynos/clock.c +79 -0
@@ -414,6 +414,71 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)writel (val, addr); } +/* get_lcd_clk: return lcd clock frequency */ +static unsigned long exynos4_get_lcd_clk (void ) +{ +struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock (); +unsigned long pclk, sclk; +unsigned int sel; +unsigned int ratio; + +/* +* CLK_SRC_LCD0 +* FIMD0_SEL [3:0] +*/ + sel =readl (&clk->src_lcd0); + sel = sel &0xf ; + +/* +* 0x6: SCLK_MPLL +* 0x7: SCLK_EPLL +* 0x8: SCLK_VPLL +*/ +if (sel ==0x6 ) + sclk =get_pll_clk (MPLL ); +else if (sel ==0x7 ) + sclk =get_pll_clk (EPLL ); +else if (sel ==0x8 ) + sclk =get_pll_clk (VPLL ); +else +return 0 ; + +/* +* CLK_DIV_LCD0 +* FIMD0_RATIO [3:0] +*/ + ratio =readl (&clk->div_lcd0); + ratio = ratio &0xf ; + + pclk = sclk / (ratio +1 ); + +return pclk; +} + +void exynos4_set_lcd_clk (void ) +{ +struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock (); +unsigned int cfg =0 ; + +/* set lcd src clock 0x6: SCLK_VPLL */ + cfg =readl (&clk->src_lcd0); + cfg &= ~(0xf ); + cfg |=0x6 ; +writel (cfg, &clk->src_lcd0); + +/* Gating all clocks for FIMD0 */ + cfg =readl (&clk->gate_ip_lcd0); + cfg |=1 <<0 ; +writel (cfg, &clk->gate_ip_lcd0); + +/* set fimd ratio */ + cfg &= ~(0xf ); + cfg |=0x1 ; +writel (cfg, &clk->div_lcd0); +} +unsigned long get_pll_clk (int pllreg) {if (cpu_is_exynos5 ())
@@ -453,3 +518,17 @@ void set_mmc_clk(int dev_index, unsigned int div)else exynos4_set_mmc_clk (dev_index, div); } + +unsigned long get_lcd_clk (void ) +{ +if (cpu_is_exynos4 ()) +return exynos4_get_lcd_clk (); +else +return 0 ; +} + +void set_lcd_clk (void ) +{ +if (cpu_is_exynos4 ()) +exynos4_set_lcd_clk (); +}
arch/arm/include/asm/arch-exynos/clk.h +2 -0
@@ -33,5 +33,7 @@ unsigned long get_arm_clk(void);unsigned long get_pwm_clk (void );unsigned long get_uart_clk (int dev_index);void set_mmc_clk (int dev_index,unsigned int div); +unsigned long get_lcd_clk (void ); +void set_lcd_clk (void );#endif
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1.7.4.1