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ARM: EXYNOS: add mipi dsi control operation

PATCH New Donghwa Lee 1 participant 1 message Apr 4, 2012

Subsystems (2)
Arm (32-bit) Arm Samsung Exynos
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Donghwa Lee

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PATCH 1/2 ARM: EXYNOS: add mipi dsi control operation

To control mipi dsi interface for EXYNOS SoC, base register address, device clock and any others control register must be set up.
This patch sets up above control operation.

[PATCH v3 1/4] ARM: EXYNOS: definition of system registers [PATCH v3 3/4] ARM: EXYNOS: add exynos lcd clock interface

Signed-off-by Donghwa Lee <[email protected]>
Signed-off-by Inki Dae <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 arch/arm/cpu/armv7/exynos/Makefile       |    2 +-
 arch/arm/cpu/armv7/exynos/clock.c        |   34 +++++++++++++++++++++
 arch/arm/cpu/armv7/exynos/power.c        |   47 ++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-exynos/clk.h   |    1 +
 arch/arm/include/asm/arch-exynos/cpu.h   |    3 ++
 arch/arm/include/asm/arch-exynos/power.h |    6 ++++
 6 files changed, 92 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/exynos/power.c
arch/arm/cpu/armv7/exynos/Makefile +1 -1
index 75c31dc..90ec2bd 100644
@@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).o
 
-COBJS	+= clock.o soc.o system.o
+COBJS	+= clock.o power.o soc.o system.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
arch/arm/cpu/armv7/exynos/clock.c +34 -0
index ecaa11e..e4735a3 100644
@@ -479,6 +479,34 @@ void exynos4_set_lcd_clk(void)
 	writel(cfg, &clk->div_lcd0);
 }
 
+void exynos4_set_mipi_clk(void)
+{
+	struct exynos4_clock *clk =
+	    (struct exynos4_clock *)samsung_get_base_clock();
+	unsigned int cfg = 0;
+
+	/* set mipi0 src clock 0x6: SCLK_MPLL */
+	cfg = readl(&clk->src_lcd0);
+	cfg &= ~(0xf << 12);
+	cfg |= (0x6 << 12);
+	writel(cfg, &clk->src_lcd0);
+
+	/* set src mask mipi0 0x1: Unmask*/
+	cfg = readl(&clk->src_mask_lcd0);
+	cfg |= (0x1 << 12);
+	writel(cfg, &clk->src_mask_lcd0);
+
+	/* Gating all clocks for MIPI0 */
+	cfg = readl(&clk->gate_ip_lcd0);
+	cfg |= 1 << 3;
+	writel(cfg, &clk->gate_ip_lcd0);
+
+	/* set fimd ratio */
+	cfg &= ~(0xf << 16);
+	cfg |= (0x1 << 16);
+	writel(cfg, &clk->div_lcd0);
+}
+
 unsigned long get_pll_clk(int pllreg)
 {
 	if (cpu_is_exynos5())

@@ -532,3 +560,9 @@ void set_lcd_clk(void)
 	if (cpu_is_exynos4())
 		exynos4_set_lcd_clk();
 }
+
+void set_mipi_clk(void)
+{
+	if (cpu_is_exynos4())
+		exynos4_set_mipi_clk();
+}
arch/arm/cpu/armv7/exynos/power.c new file +47 -0

47 lines not on this page · raw message

arch/arm/include/asm/arch-exynos/clk.h +1 -0
index cf00dea..637fb4b 100644
@@ -35,5 +35,6 @@ unsigned long get_uart_clk(int dev_index);
 void set_mmc_clk(int dev_index, unsigned int div);
 unsigned long get_lcd_clk(void);
 void set_lcd_clk(void);
+void set_mipi_clk(void);
 
 #endif
arch/arm/include/asm/arch-exynos/cpu.h +3 -0
index 70048f0..ac4ddc7 100644
@@ -41,6 +41,7 @@
 #define EXYNOS4_GPIO_PART2_BASE		0x11000000
 #define EXYNOS4_GPIO_PART1_BASE		0x11400000
 #define EXYNOS4_FIMD_BASE		0x11C00000
+#define EXYNOS4_MIPI_DSIM_BASE		0x11C80000
 #define EXYNOS4_USBOTG_BASE		0x12480000
 #define EXYNOS4_MMC_BASE		0x12510000
 #define EXYNOS4_SROMC_BASE		0x12570000

@@ -66,6 +67,7 @@
 #define EXYNOS5_GPIO_PART3_BASE		0x10D10000
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
+#define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_SROMC_BASE		0x12250000
 #define EXYNOS5_USBOTG_BASE		0x12480000

@@ -130,6 +132,7 @@ SAMSUNG_BASE(adc, ADC_BASE)
 SAMSUNG_BASE(clock, CLOCK_BASE)
 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 SAMSUNG_BASE(fimd, FIMD_BASE)
+SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
arch/arm/include/asm/arch-exynos/power.h +6 -0
index fb442f7..393d4ac 100644
@@ -227,4 +227,10 @@ struct exynos4_power {
 };
 #endif	/* __ASSEMBLY__ */
 
+void set_mipi_phy0_ctrl(int enable, unsigned int reset);
+
+#define EXYNOS_MIPI_PHY_ENABLE		(1 << 0)
+#define EXYNOS_MIPI_PHY_SRESETN		(1 << 1)
+#define EXYNOS_MIPI_PHY_MRESETN		(1 << 2)
+
 #endif
Signature · 1 line
1.7.4.1