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Query: clk: Defining new struct clk_foo types

DISCUSSION Viresh Kumar 2 participants 6 messages Apr 5, 2012

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Viresh Kumar

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#0 lore raw

Hi Mike,

I am doing SPEAr SoCs clock port with common clock framework.

Currently there are following type of clk_foo implementations present:
- clk_gate
- clk_divider
- clk_fixed_rate
- clk_mux

I have few more in my SoC:
clk with:
- gate + divider
- gate + fixed_rate
- gate + mux
...

How should i go ahead in my implementation for these?
Should i create SPEAr specific structures or enhance drivers/clk for this?

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viresh
#1 lore raw
Quoted 17 lines · Viresh Kumar

Hi Mike,

I am doing SPEAr SoCs clock port with common clock framework.

Currently there are following type of clk_foo implementations present:
- clk_gate
- clk_divider
- clk_fixed_rate
- clk_mux

I have few more in my SoC:
clk with:
- gate + divider
- gate + fixed_rate
- gate + mux
...

Quoted 2 lines

How should i go ahead in my implementation for these?
Should i create SPEAr specific structures or enhance drivers/clk for this?

If you have a gate and a divider then register a gate and a divider. We don't need clk providers for combination of these, the clock framework will handle it just fine.

Sascha

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
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#2 lore raw
Quoted 3 lines · Sascha Hauer

If you have a gate and a divider then register a gate and a divider. We don't need clk providers for combination of these, the clock framework will handle it just fine.

Thanks Sashca, but i didn't get your reply completely. Lets see if i can understand it with help of an example:

I have uart's clock that can be gated and its rate derived as a divider. So to define static clock structures, i do following:

DEFINE_CLK_GATE(uart_gate_clk, "uart_parent", &uart_parent_clk, 0,

	0xd0000000, 5, 0, NULL);
DEFINE_CLK_DIVIDER(uart_divider_clk, "uart_parent", &uart_parent_clk,
	0, 0xd0000080, 4, 2, 0, NULL);

You are suggesting this?

If yes, I don't know how it will work. How will clk get work with dev_id: "uart0". Which one will it pick?

Confused. :(

Signature · 1 line
viresh
#3 lore raw
Quoted 11 lines · Viresh Kumar
Quoted 3 lines · Sascha Hauer

If you have a gate and a divider then register a gate and a divider. We don't need clk providers for combination of these, the clock framework will handle it just fine.

Thanks Sashca, but i didn't get your reply completely. Lets see if i can understand it with help of an example:

I have uart's clock that can be gated and its rate derived as a divider. So to define static clock structures, i do following:

Quoted 6 lines

DEFINE_CLK_GATE(uart_gate_clk, "uart_parent", &uart_parent_clk, 0,

	0xd0000000, 5, 0, NULL);
DEFINE_CLK_DIVIDER(uart_divider_clk, "uart_parent", &uart_parent_clk,
	0, 0xd0000080, 4, 2, 0, NULL);

You are suggesting this?

No, more like this:

DEFINE_CLK_DIVIDER(uart_divider_clk, "uart_parent", &uart_parent_clk,

       0, 0xd0000080, 4, 2, 0, NULL);
DEFINE_CLK_GATE(uart_gate_clk, "uart_divider_clk", &uart_divider_clk,
	CLK_SET_RATE_PARENT, 0xd0000000, 5, 0, NULL);

So the divider is the parent of the gate and a set_rate call to the gate will propagate up to the divider.
You could make the gate the parent of the divider if that's how your hardware really is built, but for the software it makes no difference in this case.

Besides, I don't recommend using the DEFINE_CLK_* macros. You should really consider using clk_register_* instead.

Grmpf. These DEFINE_CLK_* macros are so omnipresent and huge in clk-private.h that people *must* think they are the way to go.

Sascha

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
author
#4 lore raw
Quoted 2 lines · Sascha Hauer

Besides, I don't recommend using the DEFINE_CLK_* macros. You should really consider using clk_register_* instead.

Can you point me to some users of this clock framework, with such runtime stuff? That would be really helpful.

Signature · 1 line
viresh
#5 lore raw
Quoted 6 lines · Viresh Kumar
Quoted 2 lines · Sascha Hauer

Besides, I don't recommend using the DEFINE_CLK_* macros. You should really consider using clk_register_* instead.

Can you point me to some users of this clock framework, with such runtime stuff? That would be really helpful.

See this branch:

git://git.pengutronix.de/git/imx/linux-2.6.git work/v3.4-rc1-imx-clk

Sascha

Signature · 4 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |