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ARM926EJS: Make asm routines volatile in cache ops

PATCH New Marek Vasut 3 participants 4 messages Apr 6, 2012 – Apr 9, 2012 Arm (32-bit)

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Marek Vasut

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#0 lore raw

PATCH 1/2 ARM926EJS: Make asm routines volatile in cache ops

We certainly don't want the compiler to reorganise the code for dcache flushing.

Signed-off-by Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Albert ARIBAUD <[email protected]>
---
 arch/arm/cpu/arm926ejs/cache.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/cpu/arm926ejs/cache.c +1 -1
index 5b23e3a..0b36294 100644
@@ -82,7 +82,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 
-	asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
 }
 
 void flush_cache(unsigned long start, unsigned long size)
Signature · 1 line
1.7.9.1
author
#1 lore raw

PATCH 2/2 ARM926EJS: Fix cache.c to comply with checkpatch.pl

Signed-off-by Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Albert ARIBAUD <[email protected]>
---
 arch/arm/cpu/arm926ejs/cache.c |   17 ++++++++---------
 1 files changed, 8 insertions(+), 9 deletions(-)
arch/arm/cpu/arm926ejs/cache.c +8 -9
index 0b36294..1d3dc6e 100644
@@ -30,7 +30,7 @@
 
 void invalidate_dcache_all(void)
 {
-	asm volatile("mcr p15, 0, %0, c7, c6, 0\n"::"r"(0));
+	asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
 }
 
 void flush_dcache_all(void)

@@ -40,7 +40,7 @@ void flush_dcache_all(void)
 		"mrc p15, 0, r15, c7, c14, 3\n"
 		"bne 0b\n"
 		"mcr p15, 0, %0, c7, c10, 4\n"
-		::"r"(0):"memory"
+		 : : "r"(0) : "memory"
 	);
 }
 

@@ -67,7 +67,7 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop)
 		return;
 
 	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c6, 1\n"::"r"(start));
+		asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 }

@@ -78,11 +78,11 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 		return;
 
 	while (start < stop) {
-		asm volatile("mcr p15, 0, %0, c7, c14, 1\n"::"r"(start));
+		asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 
-	asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
 }
 
 void flush_cache(unsigned long start, unsigned long size)

@@ -114,8 +114,7 @@ void flush_cache(unsigned long start, unsigned long size)
 /*
  * Stub implementations for l2 cache operations
  */
-void __l2_cache_disable(void)
-{
-}
+void __l2_cache_disable(void) {}
+
 void l2_cache_disable(void)
-        __attribute__((weak, alias("__l2_cache_disable")));
+	__attribute__((weak, alias("__l2_cache_disable")));
Signature · 1 line
1.7.9.1
#3 lore raw

PATCH 1/2 ARM926EJS: Make asm routines volatile in cache ops

In reply to Marek Vasut
Quoted 14 lines · Marek Vasut

We certainly don't want the compiler to reorganise the code for dcache flushing.

Signed-off-by Marek Vasut <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Albert ARIBAUD <[email protected]>
---
 arch/arm/cpu/arm926ejs/cache.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/cpu/arm926ejs/cache.c +0 -0
index 5b23e3a..0b36294 100644

arch/arm/cpu/arm926ejs/cache.c void flush_dcache_range(unsigned long start, unsigned long stop) · line 88

Quoted 8 lines
arch/arm/cpu/arm926ejs/cache.c +1 -1
@@ -82,7 +82,7 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 
-	asm("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
+	asm volatile("mcr p15, 0, %0, c7, c10, 4\n"::"r"(0));
 }
 
 void flush_cache(unsigned long start, unsigned long size)
Acked-by Stefano Babic <[email protected]>

Thanks to point this issue - the same happens on MX3x. I will send a patch (ptch for cache in ARM1136 is already merged).

Stefano

Signature · 5 lines
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