Add support for Atmel's AT91SAM9N12-EK (With DT)
Subsystems (4)
v3 cover Add support for Atmel's AT91SAM9N12-EK (With DT)
This series adds support for Atmel's AT91SAM9N12-EK.
Patches are on top of v3.4-rc2 and target for v3.5
Changes since v2 (details are in patch files respectively)
* Removed blank lines
* Removed Nandflash partitioning info (AT91 will handle this later)
* Removed IRQ priority table (AT91 will handle this in an unified way)
Hong Xu (3):
AT91: Add DT description files for AT91SAM9N12-EK
AT91: Add machine header file for AT91SAM9N12 SoC
AT91: Add machine files for AT91SAM9N12 SoC
arch/arm/boot/dts/at91sam9n12.dtsi | 222 +++++++++++++++++++ arch/arm/boot/dts/at91sam9n12ek.dts | 84 +++++++ arch/arm/mach-at91/Kconfig | 9 + arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/Makefile.boot | 2 + arch/arm/mach-at91/at91sam9n12.c | 233 ++++++++++++++++++++ arch/arm/mach-at91/clock.c | 15 +- arch/arm/mach-at91/include/mach/at91sam9n12.h | 60 +++++ .../mach-at91/include/mach/at91sam9n12_matrix.h | 53 +++++ arch/arm/mach-at91/include/mach/cpu.h | 10 + arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/setup.c | 6 + arch/arm/mach-at91/soc.h | 5 + 13 files changed, 697 insertions(+), 5 deletions(-) create mode 100644 arch/arm/boot/dts/at91sam9n12.dtsi create mode 100644 arch/arm/boot/dts/at91sam9n12ek.dts create mode 100644 arch/arm/mach-at91/at91sam9n12.c create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12.h create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
Signature · 1 line
1.7.10
PATCH v3 1/3 AT91: Add DT description files for AT91SAM9N12-EK
Added AT91SAM9N12 SoC DT file, as well as the board definition file for AT91SAM9N12-EK.
---
Changes since v2,
* Removed redundant blank line
* Removed Nandflash partitioning information
arch/arm/boot/dts/at91sam9n12.dtsi | 222 +++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/at91sam9n12ek.dts | 84 +++++++++++++ 2 files changed, 306 insertions(+) create mode 100644 arch/arm/boot/dts/at91sam9n12.dtsi create mode 100644 arch/arm/boot/dts/at91sam9n12ek.dts
arch/arm/boot/dts/at91sam9n12.dtsi new file +222 -0
@@ -0,0 +1,222 @@ +/* + * at91sam9n12.dtsi - Device Tree include file for AT91SAM9N12 SoC + * + * Copyright (C) 2012 Atmel, + * 2012 Hong Xu <[email protected]> + * + * Licensed under GPLv2 or later. + */ + +/include/ "skeleton.dtsi" + +/ { + model = "Atmel AT91SAM9N12 SoC"; + compatible = "atmel,at91sam9n12"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &dbgu; + serial1 = &usart0; + serial2 = &usart1; + serial3 = &usart2; + serial4 = &usart3; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio3 = &pioD; + tcb0 = &tcb0; + tcb1 = &tcb1; + }; + cpus { + cpu at 0 { + compatible = "arm,arm926ejs"; + }; + }; + + memory { + reg = <0x20000000 0x10000000>; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + aic: interrupt-controller at fffff000 { + #interrupt-cells = <2>; + compatible = "atmel,at91rm9200-aic"; + interrupt-controller; + interrupt-parent; + reg = <0xfffff000 0x200>; + }; + + ramc0: ramc at ffffe800 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe800 0x200>; + }; + + pmc: pmc at fffffc00 { + compatible = "atmel,at91rm9200-pmc"; + reg = <0xfffffc00 0x100>; + }; + + rstc at fffffe00 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfffffe00 0x10>; + }; + + pit: timer at fffffe30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe30 0xf>; + interrupts = <1 4>; + }; + + shdwc at fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + }; + + tcb0: timer at f8008000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf8008000 0x100>; + interrupts = <17 4>; + }; + + tcb1: timer at f800c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf800c000 0x100>; + interrupts = <17 4>; + }; + + dma: dma-controller at ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <20 4>; + }; + + pioA: gpio at fffff400 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioB: gpio at fffff600 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x100>; + interrupts = <2 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioC: gpio at fffff800 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + pioD: gpio at fffffa00 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfffffa00 0x100>; + interrupts = <3 4>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + }; + + dbgu: serial at fffff200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfffff200 0x200>; + interrupts = <1 4>; + status = "disabled"; + }; + + usart0: serial at f801c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf801c000 0x4000>; + interrupts = <5 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart1: serial at f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x4000>; + interrupts = <6 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart2: serial at f8024000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8024000 0x4000>; + interrupts = <7 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + + usart3: serial at f8028000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8028000 0x4000>; + interrupts = <8 4>; + atmel,use-dma-rx; + atmel,use-dma-tx; + status = "disabled"; + }; + }; + + nand0: nand at 40000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = < 0x40000000 0x10000000 + 0xffffe000 0x00000600 + 0xffffe600 0x00000200 + 0x00100000 0x00100000 + >; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + gpios = <&pioD 5 0 + &pioD 4 0 + 0 + >; + status = "disabled"; + }; + + usb0: ohci at 00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x00100000>; + interrupts = <22 4>; + status = "disabled"; + }; + }; + + i2c at 0 { + compatible = "i2c-gpio"; + gpios = <&pioA 30 0 /* sda */ + &pioA 31 0 /* scl */ + >; + i2c-gpio,sda-open-drain; + i2c-gpio,scl-open-drain; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +};
arch/arm/boot/dts/at91sam9n12ek.dts new file +84 -0
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Signature · 1 line
1.7.10
PATCH v3 2/3 AT91: Add machine header file for AT91SAM9N12 SoC
In reply to Hong Xu--- arch/arm/mach-at91/include/mach/at91sam9n12.h | 60 ++++++++++++++++++++ .../mach-at91/include/mach/at91sam9n12_matrix.h | 53 +++++++++++++++++ arch/arm/mach-at91/include/mach/cpu.h | 10 ++++ arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/soc.h | 5 ++ 5 files changed, 130 insertions(+) create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12.h create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
arch/arm/mach-at91/include/mach/at91sam9n12.h new file +60 -0
@@ -0,0 +1,60 @@ +/* +* SoC specific header file for the AT91SAM9N12 +* +* Copyright (C) 2012 Atmel Corporation +* +* Common definitions, based on AT91SAM9N12 SoC datasheet +* +* Licensed under GPLv2 or later +*/ + +#ifndef _AT91SAM9N12_H_ +#define _AT91SAM9N12_H_ + +/* +* Peripheral identifiers/interrupts. +*/ +#define AT91SAM9N12_ID_PIOAB 2/* Parallel I/O Controller A and B */ +#define AT91SAM9N12_ID_PIOCD 3/* Parallel I/O Controller C and D */ +#define AT91SAM9N12_ID_FUSE 4/* FUSE Controller */ +#define AT91SAM9N12_ID_USART0 5/* USART 0 */ +#define AT91SAM9N12_ID_USART1 6/* USART 1 */ +#define AT91SAM9N12_ID_USART2 7/* USART 2 */ +#define AT91SAM9N12_ID_USART3 8/* USART 3 */ +#define AT91SAM9N12_ID_TWI0 9/* Two-Wire Interface 0 */ +#define AT91SAM9N12_ID_TWI1 10/* Two-Wire Interface 1 */ +#define AT91SAM9N12_ID_MCI 12/* High Speed Multimedia Card Interface */ +#define AT91SAM9N12_ID_SPI0 13/* Serial Peripheral Interface 0 */ +#define AT91SAM9N12_ID_SPI1 14/* Serial Peripheral Interface 1 */ +#define AT91SAM9N12_ID_UART0 15/* UART 0 */ +#define AT91SAM9N12_ID_UART1 16/* UART 1 */ +#define AT91SAM9N12_ID_TCB 17/* Timer Counter 0, 1, 2, 3, 4 and 5 */ +#define AT91SAM9N12_ID_PWM 18/* Pulse Width Modulation Controller */ +#define AT91SAM9N12_ID_ADC 19/* ADC Controller */ +#define AT91SAM9N12_ID_DMA 20/* DMA Controller */ +#define AT91SAM9N12_ID_UHP 22/* USB Host High Speed */ +#define AT91SAM9N12_ID_UDP 23/* USB Device High Speed */ +#define AT91SAM9N12_ID_LCDC 25/* LCD Controller */ +#define AT91SAM9N12_ID_ISI 25/* Image Sensor Interface */ +#define AT91SAM9N12_ID_SSC 28/* Synchronous Serial Controller */ +#define AT91SAM9N12_ID_TRNG 30/* TRNG */ +#define AT91SAM9N12_ID_IRQ0 31/* Advanced Interrupt Controller */ + +/* +* User Peripheral physical base addresses. +*/ +#define AT91SAM9N12_BASE_USART0 0xf801c000 +#define AT91SAM9N12_BASE_USART1 0xf8020000 +#define AT91SAM9N12_BASE_USART2 0xf8024000 +#define AT91SAM9N12_BASE_USART3 0xf8028000 + +/* +* Internal Memory. +*/ +#define AT91SAM9N12_SRAM_BASE 0x00300000/* Internal SRAM base address */ +#define AT91SAM9N12_SRAM_SIZE SZ_32K/* Internal SRAM size (32Kb) */ + +#define AT91SAM9N12_ROM_BASE 0x00100000/* Internal ROM base address */ +#define AT91SAM9N12_ROM_SIZE SZ_128K/* Internal ROM size (128Kb) */ + +#endif
arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h new file +53 -0
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arch/arm/mach-at91/include/mach/cpu.h +10 -0
@@ -25,6 +25,7 @@#define ARCH_ID_AT91SAM9G45MRL 0x819b05a2/* aka 9G45-ES2 & non ES lots */ #define ARCH_ID_AT91SAM9G45ES 0x819b05a1/* 9G45-ES (Engineering Sample) */ #define ARCH_ID_AT91SAM9X5 0x819a05a0 +#define ARCH_ID_AT91SAM9N12 0x819a07a0#define ARCH_ID_AT91SAM9XE128 0x329973a0#define ARCH_ID_AT91SAM9XE256 0x329a93a0
@@ -70,6 +71,9 @@ enum at91_soc_type {/* SAM9X5 */ AT91_SOC_SAM9X5 , +/* SAM9N12 */ +AT91_SOC_SAM9N12 , +/* Unknown type */ AT91_SOC_NONE };
@@ -184,6 +188,12 @@ static inline int at91_soc_is_detected(void)#define cpu_is_at91sam9x25 () (0)#endif +#ifdef CONFIG_ARCH_AT91SAM9N12 +#define cpu_is_at91sam9n12 () (at91_soc_initdata.type == AT91_SOC_SAM9N12) +#else +#define cpu_is_at91sam9n12 () (0) +#endif +/* * Since this is ARM, we will never run on any AVR32 CPU. But these * definitions may reduce clutter in common drivers.
arch/arm/mach-at91/include/mach/hardware.h +2 -0
@@ -36,6 +36,8 @@#include <mach/at91sam9g45.h> #elif defined(CONFIG_ARCH_AT91SAM9X5 )#include <mach/at91sam9x5.h> +#elif defined(CONFIG_ARCH_AT91SAM9N12 ) +#include <mach/at91sam9n12.h> #elif defined(CONFIG_ARCH_AT91X40 )#include <mach/at91x40.h> #else
arch/arm/mach-at91/soc.h +5 -0
@@ -20,6 +20,7 @@ extern struct at91_init_soc at91sam9263_soc;extern struct at91_init_soc at91sam9g45_soc;extern struct at91_init_soc at91sam9rl_soc;extern struct at91_init_soc at91sam9x5_soc; +extern struct at91_init_soc at91sam9n12_soc;static inline int at91_soc_is_enabled (void ) {
@@ -53,3 +54,7 @@ static inline int at91_soc_is_enabled(void)#if !defined(CONFIG_ARCH_AT91SAM9X5 )#define at91sam9x5_soc at91_boot_soc#endif + +#if !defined(CONFIG_ARCH_AT91SAM9N12 ) +#define at91sam9n12_soc at91_boot_soc +#endif
Signature · 1 line
1.7.10
PATCH v3 3/3 AT91: Add machine files for AT91SAM9N12 SoC
In reply to Hong Xu---
Changes since v2,
* Removed IRQ priority table and related stuff
arch/arm/mach-at91/Kconfig | 9 ++ arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/Makefile.boot | 2 + arch/arm/mach-at91/at91sam9n12.c | 233 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-at91/clock.c | 15 ++- arch/arm/mach-at91/setup.c | 6 + 6 files changed, 261 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-at91/at91sam9n12.c
arch/arm/mach-at91/Kconfig +9 -0
@@ -105,6 +105,15 @@ config ARCH_AT91SAM9X5 select HAVE_NET_MACB select HAVE_AT91_DBGU0 +config ARCH_AT91SAM9N12 + bool "AT91SAM9N12 SoC" + select CPU_ARM926T + select GENERIC_CLOCKEVENTS + select HAVE_FB_ATMEL + select HAVE_AT91_DBGU0 + help + Select this if you are using Atmel's AT91SAM9N12 SoC. + config ARCH_AT91X40 bool "AT91x40" select ARCH_USES_GETTIMEOFFSET
arch/arm/mach-at91/Makefile +1 -0
@@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devi obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam926x_time.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam926x_time.o sam9_smc.o obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support
arch/arm/mach-at91/Makefile.boot +2 -0
@@ -20,3 +20,5 @@ dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9g20.dtb dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb # sam9x5 dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9g25ek.dtb +# sam9n12 +dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9n12ek.dtb
arch/arm/mach-at91/at91sam9n12.c new file +233 -0
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arch/arm/mach-at91/clock.c +10 -5
@@ -57,13 +57,15 @@ void __iomem *at91_pmc_base;#define cpu_has_800M_plla () ( cpu_is_at91sam9g20() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_at91sam9n12())#define cpu_has_300M_plla () (cpu_is_at91sam9g10())#define cpu_has_pllb () (!(cpu_is_at91sam9rl() \ || cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5())) + || cpu_is_at91sam9x5() \ + || cpu_is_at91sam9n12()))#define cpu_has_upll () (cpu_is_at91sam9g45() \ || cpu_is_at91sam9x5())
@@ -77,12 +79,15 @@ void __iomem *at91_pmc_base; || cpu_is_at91sam9x5()))#define cpu_has_plladiv2 () (cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_at91sam9n12())#define cpu_has_mdiv3 () (cpu_is_at91sam9g45() \ - || cpu_is_at91sam9x5()) + || cpu_is_at91sam9x5() \ + || cpu_is_at91sam9n12()) -#define cpu_has_alt_prescaler () (cpu_is_at91sam9x5()) +#define cpu_has_alt_prescaler () (cpu_is_at91sam9x5() \ + || cpu_is_at91sam9n12())static LIST_HEAD (clocks);static DEFINE_SPINLOCK (clk_lock);
arch/arm/mach-at91/setup.c +6 -0
@@ -142,6 +142,11 @@ static void __init soc_detect(u32 dbgu_base) at91_soc_initdata.type =AT91_SOC_SAM9X5 ; at91_boot_soc = at91sam9x5_soc;break ; + +case ARCH_ID_AT91SAM9N12 : + at91_soc_initdata.type =AT91_SOC_SAM9N12 ; + at91_boot_soc = at91sam9n12_soc; +break ; }/* at91sam9g10 */
@@ -209,6 +214,7 @@ static const char *soc_name[] = { [AT91_SOC_SAM9G45] = "at91sam9g45", [AT91_SOC_SAM9RL] = "at91sam9rl", [AT91_SOC_SAM9X5] = "at91sam9x5", + [AT91_SOC_SAM9N12] = "at91sam9n12", [AT91_SOC_NONE] = "Unknown" };
Signature · 1 line
1.7.10
v3 cover Add support for Atmel's AT91SAM9N12-EK (With DT)
In reply to Hong XuOn 04/17/2012 08:26 AM, Hong Xu :
Quoted 9 lines
This series adds support for Atmel's AT91SAM9N12-EK.
Patches are on top of v3.4-rc2 and target for v3.5
Changes since v2 (details are in patch files respectively)
* Removed blank lines
* Removed Nandflash partitioning info (AT91 will handle this later)
* Removed IRQ priority table (AT91 will handle this in an unified way)
Quoted 4 lines
Hong Xu (3):
AT91: Add DT description files for AT91SAM9N12-EK
AT91: Add machine header file for AT91SAM9N12 SoC
AT91: Add machine files for AT91SAM9N12 SoC
Fine with me. I will queue this SoC support for 3.5 inclusion. Maybe some merge modifications will be needed against our "cleanup" branch but I will manage that easily.
Thanks for adding this support Xu Hong.
Best regards,
Quoted 21 lines
arch/arm/boot/dts/at91sam9n12.dtsi | 222 +++++++++++++++++++ arch/arm/boot/dts/at91sam9n12ek.dts | 84 +++++++ arch/arm/mach-at91/Kconfig | 9 + arch/arm/mach-at91/Makefile | 1 + arch/arm/mach-at91/Makefile.boot | 2 + arch/arm/mach-at91/at91sam9n12.c | 233 ++++++++++++++++++++ arch/arm/mach-at91/clock.c | 15 +- arch/arm/mach-at91/include/mach/at91sam9n12.h | 60 +++++ .../mach-at91/include/mach/at91sam9n12_matrix.h | 53 +++++ arch/arm/mach-at91/include/mach/cpu.h | 10 + arch/arm/mach-at91/include/mach/hardware.h | 2 + arch/arm/mach-at91/setup.c | 6 + arch/arm/mach-at91/soc.h | 5 + 13 files changed, 697 insertions(+), 5 deletions(-) create mode 100644 arch/arm/boot/dts/at91sam9n12.dtsi create mode 100644 arch/arm/boot/dts/at91sam9n12ek.dts create mode 100644 arch/arm/mach-at91/at91sam9n12.c create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12.h create mode 100644 arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
Signature · 1 line
Nicolas Ferre