Updates for Exynos5250 Rev1.0 and device tree support

PATCH New Thomas Abraham 3 participants 31 messages Apr 17, 2012 – Apr 19, 2012

Subsystems (6)

Device tree bindings Arm (32-bit) Arm sub-architectures GPIO +2 more subsystems

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Thomas Abraham

author

2012-04-17 05:38 UTC #0 lore raw

cover Updates for Exynos5250 Rev1.0 and device tree support

This patch series includes modifications to support Rev1.0 of Exynos5250 SoC and overrides the existing support for Rev0. It also includes basic device tree support (tested for UART, WDT, RTC, GPIO, I2C, GIC and DMA PL330).

Changhwan Youn (2):
ARM: Exynos5: Modify the GIC physical address for static io-mapping
ARM: Exynos: Redefine IRQ_MCT_L0,1 definition

Heiko Stuebner (1):
rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support

Kisoo Yu (1):
ARM: Exynos5: Add pre-divider and fout mux clocks for bpll and mpll

Sangsu Park (1):
gpio/samsung: add GPC4 bank instance

Thomas Abraham (7):
ARM: Exynos: Remove a new bus_type instance for Exynos5
ARM: Exynos5: Fix incorrect initialization of GIC
ARM: Exynos5: Add watchdog timer clock instance
ARM: Exynos5: Remove duplicated instantiation of pdma clock
ARM: Exynos5: Add MDMA0 clock instance
ARM: Exynos5: Update device tree source files
ARM: Exynos5: Update device tree enabled machine file

 arch/arm/boot/dts/exynos5250-smdk5250.dts      |   52 +++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi              |   44 +++--------
 arch/arm/mach-exynos/clock-exynos5.c           |   98 +++++++++++++++++++++---
 arch/arm/mach-exynos/common.c                  |   27 ++-----
 arch/arm/mach-exynos/include/mach/gpio.h       |    9 ++-
 arch/arm/mach-exynos/include/mach/irqs.h       |    4 +-
 arch/arm/mach-exynos/include/mach/map.h        |    4 +-
 arch/arm/mach-exynos/include/mach/regs-clock.h |    2 +
 arch/arm/mach-exynos/mach-exynos5-dt.c         |    7 ++-
 arch/arm/mach-exynos/mct.c                     |   17 +++--
 arch/arm/plat-s5p/clock.c                      |   11 ---
 drivers/gpio/gpio-samsung.c                    |    8 ++
 drivers/rtc/rtc-s3c.c                          |   18 ++--
 13 files changed, 204 insertions(+), 97 deletions(-)

Thomas Abraham

author

2012-04-17 05:38 UTC #1 lore raw

PATCH 1/12 ARM: Exynos: Remove a new bus_type instance for Exynos5

A seperate bus_type instance is not required for Exynos5. The existing bus_type instance used with Exynos4 is sufficient for both Exynos4 and Exynos5. This also solves issue of uninitialized usage of exynos4_subsys in Exynos4 power management code that is reused for Exynos5 also.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/common.c |   19 ++-----------------
 1 files changed, 2 insertions(+), 17 deletions(-)

arch/arm/mach-exynos/common.c +2 ~~-17~~

index e9e353b..636d5f8 100644
@@ -557,25 +557,13 @@ struct bus_type exynos4_subsys = {
 	.dev_name	= "exynos4-core",
 };
 
-struct bus_type exynos5_subsys = {
-	.name		= "exynos5-core",
-	.dev_name	= "exynos5-core",
-};
-
 static struct device exynos4_dev = {
 	.bus	= &exynos4_subsys,
 };
 
-static struct device exynos5_dev = {
-	.bus	= &exynos5_subsys,
-};
-
 static int __init exynos_core_init(void)
 {
-	if (soc_is_exynos5250())
-		return subsys_system_register(&exynos5_subsys, NULL);
-	else
-		return subsys_system_register(&exynos4_subsys, NULL);
+	return subsys_system_register(&exynos4_subsys, NULL);
 }
 core_initcall(exynos_core_init);

@@ -662,10 +650,7 @@ static int __init exynos_init(void)
 {
 	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-	if (soc_is_exynos5250())
-		return device_register(&exynos5_dev);
-	else
-		return device_register(&exynos4_dev);
+	return device_register(&exynos4_dev);
 }
 
 /* uart registration process */

Signature · 1 line

1.6.6.rc2

Kukjin Kim

2012-04-19 00:15 UTC #2 lore raw

PATCH 1/12 ARM: Exynos: Remove a new bus_type instance for Exynos5

Quoted 3 lines · Thomas Abraham

A seperate bus_type instance is not required for Exynos5. The existing bus_type instance used with Exynos4 is sufficient for both Exynos4 and Exynos5. This also solves issue of uninitialized usage of exynos4_subsys in Exynos4 power

Yes, could be. BTW could you please check that with Jongpill's PM patch for EXYNOS5? If just single bus_type supports EXYNOS4 and EXYNOS5, I'd like to change its name to exynos_subsys.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Quoted 50 lines

management code that is reused for Exynos5 also.

Signed-off-by Thomas Abraham<[email protected]>

---
  arch/arm/mach-exynos/common.c |   19 ++-----------------
  1 files changed, 2 insertions(+), 17 deletions(-)

arch/arm/mach-exynos/common.c +2 ~~-17~~

index e9e353b..636d5f8 100644
@@ -557,25 +557,13 @@ struct bus_type exynos4_subsys = {
  	.dev_name	= "exynos4-core",
  };
 
-struct bus_type exynos5_subsys = {
-	.name		= "exynos5-core",
-	.dev_name	= "exynos5-core",
-};
-
  static struct device exynos4_dev = {
  	.bus	=&exynos4_subsys,
  };
 
-static struct device exynos5_dev = {
-	.bus	=&exynos5_subsys,
-};
-
  static int __init exynos_core_init(void)
  {
-	if (soc_is_exynos5250())
-		return subsys_system_register(&exynos5_subsys, NULL);
-	else
-		return subsys_system_register(&exynos4_subsys, NULL);
+	return subsys_system_register(&exynos4_subsys, NULL);
  }
  core_initcall(exynos_core_init);

@@ -662,10 +650,7 @@ static int __init exynos_init(void)
  {
  	printk(KERN_INFO "EXYNOS: Initializing architecture\n");
 
-	if (soc_is_exynos5250())
-		return device_register(&exynos5_dev);
-	else
-		return device_register(&exynos4_dev);
+	return device_register(&exynos4_dev);
  }
 
  /* uart registration process */

Thomas Abraham

author

2012-04-17 05:38 UTC #3 lore raw

PATCH 2/12 ARM: Exynos5: Fix incorrect initialization of GIC

In reply to Thomas Abraham

Use the of_irq_init() call to setup the gic which also properly registers the gic device node pointer with gic irq domain, without which all interrupt specifier translations for gic fail.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/common.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

arch/arm/mach-exynos/common.c +3 -1

index 636d5f8..35ac675 100644
@@ -532,11 +532,12 @@ void __init exynos4_init_irq(void)
 	s5p_init_irq(NULL, 0);
 }
 
+#ifdef CONFIG_ARCH_EXYNOS5
 void __init exynos5_init_irq(void)
 {
 	int irq;
 
-	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+	of_irq_init(exynos4_dt_irq_match);
 
 	for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
 		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

@@ -551,6 +552,7 @@ void __init exynos5_init_irq(void)
 	 */
 	s5p_init_irq(NULL, 0);
 }
+#endif /* CONFIG_ARCH_EXYNOS5 */
 
 struct bus_type exynos4_subsys = {
 	.name		= "exynos4-core",

Signature · 1 line

1.6.6.rc2

Kukjin Kim

2012-04-19 00:51 UTC #4 lore raw

PATCH 2/12 ARM: Exynos5: Fix incorrect initialization of GIC

Quoted 14 lines · Thomas Abraham

Use the of_irq_init() call to setup the gic which also properly registers the gic device node pointer with gic irq domain, without which all interrupt specifier translations for gic fail.
Signed-off-by Thomas Abraham<[email protected]>
---
  arch/arm/mach-exynos/common.c |    4 +++-
  1 files changed, 3 insertions(+), 1 deletions(-)
arch/arm/mach-exynos/common.c +0 -0
index 636d5f8..35ac675 100644

arch/arm/mach-exynos/common.c void __init exynos4_init_irq(void) · line 535

Quoted 4 lines

arch/arm/mach-exynos/common.c +1 -0

@@ -532,11 +532,12 @@ void __init exynos4_init_irq(void)
  	s5p_init_irq(NULL, 0);
  }
 
+#ifdef CONFIG_ARCH_EXYNOS5

Why this is needed?

Quoted 10 lines

arch/arm/mach-exynos/common.c +1 -1

  void __init exynos5_init_irq(void)
  {
  	int irq;
 
-	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+	of_irq_init(exynos4_dt_irq_match);
 
  	for (irq = 0; irq<  EXYNOS5_MAX_COMBINER_NR; irq++) {
  		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),

arch/arm/mach-exynos/common.c void __init exynos5_init_irq(void) · line 558

Quoted 7 lines

arch/arm/mach-exynos/common.c +1 -0

@@ -551,6 +552,7 @@ void __init exynos5_init_irq(void)
  	 */
  	s5p_init_irq(NULL, 0);
  }
+#endif /* CONFIG_ARCH_EXYNOS5 */
 
  struct bus_type exynos4_subsys = {
  	.name		= "exynos4-core",

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-04-17 05:38 UTC #5 lore raw

PATCH 3/12 ARM: Exynos5: Add watchdog timer clock instance

In reply to Thomas Abraham

Add watchdog timer clock instance for Exynos5 watchdog controller.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos5.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

arch/arm/mach-exynos/clock-exynos5.c +5 -0

index ad3bec4..662615d 100644
@@ -474,6 +474,11 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_peris_ctrl,
 		.ctrlbit	= (1 << 20),
 	}, {
+		.name		= "watchdog",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 19),
+	}, {
 		.name		= "hsmmc",
 		.devname	= "exynos4-sdhci.0",
 		.parent		= &exynos5_clk_aclk_200.clk,

Signature · 1 line

1.6.6.rc2

Kyungmin Park

2012-04-17 06:14 UTC #6 lore raw

PATCH 3/12 ARM: Exynos5: Add watchdog timer clock instance

Quoted 13 lines · Thomas Abraham

Add watchdog timer clock instance for Exynos5 watchdog controller.
Signed-off-by Thomas Abraham <[email protected]>
---
 arch/arm/mach-exynos/clock-exynos5.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/clock-exynos5.c +0 -0
index ad3bec4..662615d 100644

arch/arm/mach-exynos/clock-exynos5.c static struct clk exynos5_init_clocks_off[] = { · line 480

Quoted 7 lines

arch/arm/mach-exynos/clock-exynos5.c +4 -0

@@ -474,6 +474,11 @@ static struct clk exynos5_init_clocks_off[] = {
 		.enable		= exynos5_clk_ip_peris_ctrl,
 		.ctrlbit	= (1 << 20),
 	}, {
+		.name		= "watchdog",
+		.parent		= &exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1 << 19),

Hi,

Can you place this in order? It has same "exynos5_clk_ip_peris_ctrl", but located under (1 << 20).

Thank you,
Kyungmin Park

Quoted 13 lines

arch/arm/mach-exynos/clock-exynos5.c +1 -1
+	}, {
 		.name		= "hsmmc",
 		.devname	= "exynos4-sdhci.0",
 		.parent		= &exynos5_clk_aclk_200.clk,
--
1.6.6.rc2
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Thomas Abraham

author

2012-04-17 08:12 UTC #7 lore raw

PATCH 3/12 ARM: Exynos5: Add watchdog timer clock instance

Quoted 24 lines · Kyungmin Park

Quoted 13 lines · Thomas Abraham
Add watchdog timer clock instance for Exynos5 watchdog controller.
Signed-off-by Thomas Abraham <[email protected]>
---
?arch/arm/mach-exynos/clock-exynos5.c | ? ?5 +++++ ?1 files changed, 5 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/clock-exynos5.c +0 -0
index ad3bec4..662615d 100644
arch/arm/mach-exynos/clock-exynos5.c static struct clk exynos5_init_clocks_off[] = { · line 480
Quoted 7 lines
arch/arm/mach-exynos/clock-exynos5.c +4 -0
@@ -474,6 +474,11 @@ static struct clk exynos5_init_clocks_off[] = {
 ? ? ? ? ? ? ? .enable ? ? ? ? = exynos5_clk_ip_peris_ctrl,
 ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 20),
 ? ? ? }, {
+ ? ? ? ? ? ? .name ? ? ? ? ? = "watchdog",
+ ? ? ? ? ? ? .parent ? ? ? ? = &exynos5_clk_aclk_66.clk,
+ ? ? ? ? ? ? .enable ? ? ? ? = exynos5_clk_ip_peris_ctrl,
+ ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 19),
Hi,

Quoted 2 lines

Can you place this in order? It has same "exynos5_clk_ip_peris_ctrl", but located under (1 << 20).

Hi Mr. Park,

At present, there is only one clock gate from the peris register for which there is a struct clock instance. This patch adds the watchdog timer clock gate right below it and maintains the descending bit position order.

Thanks,
Thomas.

Quoted 16 lines

Thank you,
Kyungmin Park
Quoted 13 lines
arch/arm/mach-exynos/clock-exynos5.c +1 -1
+ ? ? }, {
 ? ? ? ? ? ? ? .name ? ? ? ? ? = "hsmmc",
 ? ? ? ? ? ? ? .devname ? ? ? ?= "exynos4-sdhci.0",
 ? ? ? ? ? ? ? .parent ? ? ? ? = &exynos5_clk_aclk_200.clk,
--
1.6.6.rc2
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Kukjin Kim

2012-04-19 00:28 UTC #8 lore raw

PATCH 3/12 ARM: Exynos5: Add watchdog timer clock instance

In reply to Thomas Abraham

Quoted 13 lines · Thomas Abraham

Add watchdog timer clock instance for Exynos5 watchdog controller.
Signed-off-by Thomas Abraham<[email protected]>
---
  arch/arm/mach-exynos/clock-exynos5.c |    5 +++++
  1 files changed, 5 insertions(+), 0 deletions(-)
arch/arm/mach-exynos/clock-exynos5.c +0 -0
index ad3bec4..662615d 100644
@@ -474,6 +474,11 @@ static struct clk exynos5_init_clocks_off[] = {
  		.enable		= exynos5_clk_ip_peris_ctrl,

arch/arm/mach-exynos/clock-exynos5.c static struct clk exynos5_init_clocks_off[] = { · line 484

Quoted 10 lines

arch/arm/mach-exynos/clock-exynos5.c +5 -0

  		.ctrlbit	= (1<<  20),
  	}, {
+		.name		= "watchdog",
+		.parent		=&exynos5_clk_aclk_66.clk,
+		.enable		= exynos5_clk_ip_peris_ctrl,
+		.ctrlbit	= (1<<  19),
+	}, {
  		.name		= "hsmmc",
  		.devname	= "exynos4-sdhci.0",
  		.parent		=&exynos5_clk_aclk_200.clk,

Looks ok, will apply.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-04-17 05:38 UTC #9 lore raw

PATCH 4/12 ARM: Exynos5: Remove duplicated instantiation of pdma clock

In reply to Thomas Abraham

The clock of both the peripheral dma controllers is controlled by a single clock gate. Hence remove the duplicate instantiation of the pdma clock.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos5.c |   17 ++++-------------
 1 files changed, 4 insertions(+), 13 deletions(-)

arch/arm/mach-exynos/clock-exynos5.c +4 ~~-13~~

index 662615d..fb95e9b 100644
@@ -762,16 +762,8 @@ static struct clk exynos5_init_clocks_on[] = {
 	}
 };
 
-static struct clk exynos5_clk_pdma0 = {
+static struct clk exynos5_clk_pdma = {
 	.name		= "dma",
-	.devname	= "dma-pl330.0",
-	.enable		= exynos5_clk_ip_fsys_ctrl,
-	.ctrlbit	= (1 << 1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
-	.name		= "dma",
-	.devname	= "dma-pl330.1",
 	.enable		= exynos5_clk_ip_fsys_ctrl,
 	.ctrlbit	= (1 << 1),
 };

@@ -1064,8 +1056,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 };
 
 static struct clk *exynos5_clk_cdev[] = {
-	&exynos5_clk_pdma0,
-	&exynos5_clk_pdma1,
+	&exynos5_clk_pdma,
 	&exynos5_clk_mdma1,
 };

@@ -1089,8 +1080,8 @@ static struct clk_lookup exynos5_clk_lookup[] = {
 	CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
 	CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
 	CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
-	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
-	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma),
+	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma),
 	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
 };

Signature · 1 line

1.6.6.rc2

Kukjin Kim

2012-04-19 00:30 UTC #10 lore raw

PATCH 4/12 ARM: Exynos5: Remove duplicated instantiation of pdma clock

Quoted 19 lines · Thomas Abraham

The clock of both the peripheral dma controllers is controlled by a single clock gate. Hence remove the duplicate instantiation of the pdma clock.
Signed-off-by Thomas Abraham<[email protected]>
---
  arch/arm/mach-exynos/clock-exynos5.c |   17 ++++-------------
  1 files changed, 4 insertions(+), 13 deletions(-)
arch/arm/mach-exynos/clock-exynos5.c +1 -1
index 662615d..fb95e9b 100644
@@ -762,16 +762,8 @@ static struct clk exynos5_init_clocks_on[] = {
  	}
  };
 
-static struct clk exynos5_clk_pdma0 = {
+static struct clk exynos5_clk_pdma = {
  	.name		= "dma",

arch/arm/mach-exynos/clock-exynos5.c static struct clk exynos5_init_clocks_on[] = { · line 768

Quoted 10 lines

arch/arm/mach-exynos/clock-exynos5.c +0 -8

-	.devname	= "dma-pl330.0",
-	.enable		= exynos5_clk_ip_fsys_ctrl,
-	.ctrlbit	= (1<<  1),
-};
-
-static struct clk exynos5_clk_pdma1 = {
-	.name		= "dma",
-	.devname	= "dma-pl330.1",
  	.enable		= exynos5_clk_ip_fsys_ctrl,
  	.ctrlbit	= (1<<  1),

Since this shuld be (1 << 2), this patch can be dropped.

As I know, Boojin's patch fixes this. If not, please fix this :)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-04-17 05:38 UTC #11 lore raw

PATCH 5/12 ARM: Exynos5: Add MDMA0 clock instance

In reply to Thomas Abraham

Add clock instance for MDMA0 controller.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos5.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)

arch/arm/mach-exynos/clock-exynos5.c +9 -2

index fb95e9b..0230ba8 100644
@@ -768,9 +768,14 @@ static struct clk exynos5_clk_pdma = {
 	.ctrlbit	= (1 << 1),
 };
 
+static struct clk exynos5_clk_mdma0 = {
+	.name		= "dma",
+	.enable		= exynos5_clk_ip_acp_ctrl,
+	.ctrlbit	= (1 << 1),
+};
+
 static struct clk exynos5_clk_mdma1 = {
 	.name		= "dma",
-	.devname	= "dma-pl330.2",
 	.enable		= exynos5_clk_ip_gen_ctrl,
 	.ctrlbit	= (1 << 4),
 };

@@ -1057,6 +1062,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 
 static struct clk *exynos5_clk_cdev[] = {
 	&exynos5_clk_pdma,
+	&exynos5_clk_mdma0,
 	&exynos5_clk_mdma1,
 };

@@ -1082,7 +1088,8 @@ static struct clk_lookup exynos5_clk_lookup[] = {
 	CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
 	CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma),
 	CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma),
-	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma0),
+	CLKDEV_INIT("dma-pl330.3", "apb_pclk", &exynos5_clk_mdma1),
 };
 
 static unsigned long exynos5_epll_get_rate(struct clk *clk)

Signature · 1 line

1.6.6.rc2

Kukjin Kim

2012-04-19 01:20 UTC #12 lore raw

PATCH 5/12 ARM: Exynos5: Add MDMA0 clock instance

Quoted 36 lines · Thomas Abraham

Add clock instance for MDMA0 controller.

Signed-off-by Thomas Abraham<[email protected]>

---
  arch/arm/mach-exynos/clock-exynos5.c |   11 +++++++++--
  1 files changed, 9 insertions(+), 2 deletions(-)

arch/arm/mach-exynos/clock-exynos5.c +7 -1

index fb95e9b..0230ba8 100644
@@ -768,9 +768,14 @@ static struct clk exynos5_clk_pdma = {
  	.ctrlbit	= (1<<  1),
  };
 
+static struct clk exynos5_clk_mdma0 = {
+	.name		= "dma",
+	.enable		= exynos5_clk_ip_acp_ctrl,
+	.ctrlbit	= (1<<  1),
+};
+
  static struct clk exynos5_clk_mdma1 = {
  	.name		= "dma",
-	.devname	= "dma-pl330.2",
  	.enable		= exynos5_clk_ip_gen_ctrl,
  	.ctrlbit	= (1<<  4),
  };

@@ -1057,6 +1062,7 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 
  static struct clk *exynos5_clk_cdev[] = {
  	&exynos5_clk_pdma,
+	&exynos5_clk_mdma0,
  	&exynos5_clk_mdma1,
  };

arch/arm/mach-exynos/clock-exynos5.c static struct clk_lookup exynos5_clk_lookup[] = { · line 1095

Quoted 9 lines

arch/arm/mach-exynos/clock-exynos5.c +2 -1

@@ -1082,7 +1088,8 @@ static struct clk_lookup exynos5_clk_lookup[] = {
  	CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2",&exynos5_clk_sclk_mmc3.clk),
  	CLKDEV_INIT("dma-pl330.0", "apb_pclk",&exynos5_clk_pdma),
  	CLKDEV_INIT("dma-pl330.1", "apb_pclk",&exynos5_clk_pdma),
-	CLKDEV_INIT("dma-pl330.2", "apb_pclk",&exynos5_clk_mdma1),
+	CLKDEV_INIT("dma-pl330.2", "apb_pclk",&exynos5_clk_mdma0),
+	CLKDEV_INIT("dma-pl330.3", "apb_pclk",&exynos5_clk_mdma1),
  };
 
  static unsigned long exynos5_epll_get_rate(struct clk *clk)

Well, mdma0 will not be used so we don't need this.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-04-17 05:38 UTC #13 lore raw

PATCH 6/12 rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support

In reply to Thomas Abraham

From: Heiko Stuebner <[email protected]>

Commits 7006ee4f (rtc-s3c: make room for more variants in devicetree block) and 6c0a2365 (rtc-s3c: add variants for S3C2443 and S3C2416) introduced build-failures with enabled CONFIG_USE_OF option.

This patch fixes missing "," in s3c_rtc_dt_match and wrong handling of the of_device_id.data property.

Reported-by Sylwester Nawrocki <[email protected]>

Signed-off-by Heiko Stuebner <[email protected]>

---
 drivers/rtc/rtc-s3c.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

drivers/rtc/rtc-s3c.c +9 -9

index 9ccea13..c792b6d 100644
@@ -449,7 +449,7 @@ static inline int s3c_rtc_get_driver_data(struct platform_device *pdev)
 	if (pdev->dev.of_node) {
 		const struct of_device_id *match;
 		match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
-		return match->data;
+		return (int)match->data;
 	}
 #endif
 	return platform_get_device_id(pdev)->driver_data;

@@ -667,17 +667,17 @@ static int s3c_rtc_resume(struct platform_device *pdev)
 #ifdef CONFIG_OF
 static const struct of_device_id s3c_rtc_dt_match[] = {
 	{
-		.compatible = "samsung,s3c2410-rtc"
-		.data = TYPE_S3C2410,
+		.compatible = "samsung,s3c2410-rtc",
+		.data = (void *)TYPE_S3C2410,
 	}, {
-		.compatible = "samsung,s3c2416-rtc"
-		.data = TYPE_S3C2416,
+		.compatible = "samsung,s3c2416-rtc",
+		.data = (void *)TYPE_S3C2416,
 	}, {
-		.compatible = "samsung,s3c2443-rtc"
-		.data = TYPE_S3C2443,
+		.compatible = "samsung,s3c2443-rtc",
+		.data = (void *)TYPE_S3C2443,
 	}, {
-		.compatible = "samsung,s3c6410-rtc"
-		.data = TYPE_S3C64XX,
+		.compatible = "samsung,s3c6410-rtc",
+		.data = (void *)TYPE_S3C64XX,
 	},
 	{},
 };

Signature · 1 line

1.6.6.rc2

Kyungmin Park

2012-04-17 06:30 UTC #14 lore raw

PATCH 6/12 rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support

Hi,

It's already merged with different patch,

#ifdef CONFIG_OF

static const struct of_device_id s3c_rtc_dt_match[] = {
        {
                .compatible = "samsung,s3c2410-rtc",
                .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
        }, {
                .compatible = "samsung,s3c2416-rtc",
                .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
        }, {
                .compatible = "samsung,s3c2443-rtc",
                .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
        }, {
                .compatible = "samsung,s3c6410-rtc",
                .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
        },
        {},
};

MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
#else
#define s3c_rtc_dt_match NULL
#endif

Thank you,
Kyungmin Park

Quoted 65 lines · Thomas Abraham

From: Heiko Stuebner <[email protected]>
Commits 7006ee4f (rtc-s3c: make room for more variants in devicetree block) and 6c0a2365 (rtc-s3c: add variants for S3C2443 and S3C2416) introduced build-failures with enabled CONFIG_USE_OF option.
This patch fixes missing "," in s3c_rtc_dt_match and wrong handling of the of_device_id.data property.
Reported-by Sylwester Nawrocki <[email protected]>
Signed-off-by Heiko Stuebner <[email protected]>
---
 drivers/rtc/rtc-s3c.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)
drivers/rtc/rtc-s3c.c +1 -1
index 9ccea13..c792b6d 100644
@@ -449,7 +449,7 @@ static inline int s3c_rtc_get_driver_data(struct
 platform_device *pdev)
 	if (pdev->dev.of_node) {
 		const struct of_device_id *match;
 		match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
-		return match->data;
+		return (int)match->data;
 	}
 #endif
drivers/rtc/rtc-s3c.c +8 -8
 	return platform_get_device_id(pdev)->driver_data;
@@ -667,17 +667,17 @@ static int s3c_rtc_resume(struct platform_device
 *pdev)
 #ifdef CONFIG_OF
 static const struct of_device_id s3c_rtc_dt_match[] = {
 	{
-		.compatible = "samsung,s3c2410-rtc"
-		.data = TYPE_S3C2410,
+		.compatible = "samsung,s3c2410-rtc",
+		.data = (void *)TYPE_S3C2410,
 	}, {
-		.compatible = "samsung,s3c2416-rtc"
-		.data = TYPE_S3C2416,
+		.compatible = "samsung,s3c2416-rtc",
+		.data = (void *)TYPE_S3C2416,
 	}, {
-		.compatible = "samsung,s3c2443-rtc"
-		.data = TYPE_S3C2443,
+		.compatible = "samsung,s3c2443-rtc",
+		.data = (void *)TYPE_S3C2443,
 	}, {
-		.compatible = "samsung,s3c6410-rtc"
-		.data = TYPE_S3C64XX,
+		.compatible = "samsung,s3c6410-rtc",
+		.data = (void *)TYPE_S3C64XX,
 	},
 	{},
};
--
1.6.6.rc2
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Thomas Abraham

author

2012-04-17 08:15 UTC #15 lore raw

PATCH 6/12 rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support

Quoted 3 lines · Kyungmin Park

Hi,
It's already merged with different patch,

This is a repost of the patch from Heiko Stuebner which would be required to fix compilation issue for rtc driver. I think you are referring to that patch but it is not merged yet. So I am reposting it with this series.

Thanks,
Thomas.

Quoted 92 lines

#ifdef CONFIG_OF
static const struct of_device_id s3c_rtc_dt_match[] = { ? ? ? ?{
? ? ? ? ? ? ? ?.compatible = "samsung,s3c2410-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C2410], ? ? ? ?}, {
? ? ? ? ? ? ? ?.compatible = "samsung,s3c2416-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C2416], ? ? ? ?}, {
? ? ? ? ? ? ? ?.compatible = "samsung,s3c2443-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C2443], ? ? ? ?}, {
? ? ? ? ? ? ? ?.compatible = "samsung,s3c6410-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C64XX], ? ? ? ?},
? ? ? ?{},
};
MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
#else
#define s3c_rtc_dt_match NULL
#endif
Thank you,
Kyungmin Park
Quoted 65 lines · Thomas Abraham
From: Heiko Stuebner <[email protected]>
Commits 7006ee4f (rtc-s3c: make room for more variants in devicetree block) and 6c0a2365 (rtc-s3c: add variants for S3C2443 and S3C2416) introduced build-failures with enabled CONFIG_USE_OF option.
This patch fixes missing "," in s3c_rtc_dt_match and wrong handling of the of_device_id.data property.
Reported-by Sylwester Nawrocki <[email protected]>
Signed-off-by Heiko Stuebner <[email protected]>
---
?drivers/rtc/rtc-s3c.c | ? 18 +++++++++---------
?1 files changed, 9 insertions(+), 9 deletions(-)
drivers/rtc/rtc-s3c.c +1 -1
index 9ccea13..c792b6d 100644
@@ -449,7 +449,7 @@ static inline int s3c_rtc_get_driver_data(struct
 platform_device *pdev)
 ? ? ? if (pdev->dev.of_node) {
 ? ? ? ? ? ? ? const struct of_device_id *match;
 ? ? ? ? ? ? ? match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
- ? ? ? ? ? ? return match->data;
+ ? ? ? ? ? ? return (int)match->data;
 ? ? ? }
?#endif
? ? ? return platform_get_device_id(pdev)->driver_data;
drivers/rtc/rtc-s3c.c +0 -0
@@ -667,17 +667,17 @@ static int s3c_rtc_resume(struct platform_device
 *pdev)
?#ifdef CONFIG_OF
?static const struct of_device_id s3c_rtc_dt_match[] = { ? ? ? {
- ? ? ? ? ? ? .compatible = "samsung,s3c2410-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C2410,
+ ? ? ? ? ? ? .compatible = "samsung,s3c2410-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C2410,
? ? ? }, {
- ? ? ? ? ? ? .compatible = "samsung,s3c2416-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C2416,
+ ? ? ? ? ? ? .compatible = "samsung,s3c2416-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C2416,
? ? ? }, {
- ? ? ? ? ? ? .compatible = "samsung,s3c2443-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C2443,
+ ? ? ? ? ? ? .compatible = "samsung,s3c2443-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C2443,
? ? ? }, {
- ? ? ? ? ? ? .compatible = "samsung,s3c6410-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C64XX,
+ ? ? ? ? ? ? .compatible = "samsung,s3c6410-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C64XX,
? ? ? },
? ? ? {},
?};
--
1.6.6.rc2
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Kyungmin Park

2012-04-17 08:25 UTC #16 lore raw

PATCH 6/12 rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support

Quoted 9 lines · Thomas Abraham

Quoted 3 lines · Kyungmin Park
Hi,
It's already merged with different patch,
This is a repost of the patch from Heiko Stuebner which would be required to fix compilation issue for rtc driver. I think you are referring to that patch but it is not merged yet. So I am reposting it with this series.

No it's 3.4.0-rc3. it's already included.

Quoted 104 lines

Thanks,
Thomas.
Quoted 87 lines
#ifdef CONFIG_OF
static const struct of_device_id s3c_rtc_dt_match[] = {
       {
               .compatible = "samsung,s3c2410-rtc",
               .data = &s3c_rtc_drv_data_array[TYPE_S3C2410],
       }, {
               .compatible = "samsung,s3c2416-rtc",
               .data = &s3c_rtc_drv_data_array[TYPE_S3C2416],
       }, {
               .compatible = "samsung,s3c2443-rtc",
               .data = &s3c_rtc_drv_data_array[TYPE_S3C2443],
       }, {
               .compatible = "samsung,s3c6410-rtc",
               .data = &s3c_rtc_drv_data_array[TYPE_S3C64XX],
       },
       {},
};
MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
#else
#define s3c_rtc_dt_match NULL
#endif
Thank you,
Kyungmin Park
Quoted 60 lines · Thomas Abraham
From: Heiko Stuebner <[email protected]>
Commits 7006ee4f (rtc-s3c: make room for more variants in devicetree block)
and 6c0a2365 (rtc-s3c: add variants for S3C2443 and S3C2416) introduced build-failures with enabled CONFIG_USE_OF option.
This patch fixes missing "," in s3c_rtc_dt_match and wrong handling of the of_device_id.data property.
Reported-by Sylwester Nawrocki <[email protected]>
Signed-off-by Heiko Stuebner <[email protected]>
---
 drivers/rtc/rtc-s3c.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)
drivers/rtc/rtc-s3c.c +1 -1
index 9ccea13..c792b6d 100644
@@ -449,7 +449,7 @@ static inline int s3c_rtc_get_driver_data(struct
 platform_device *pdev)
      if (pdev->dev.of_node) {
              const struct of_device_id *match;
              match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
-             return match->data;
+             return (int)match->data;
      }
 #endif
      return platform_get_device_id(pdev)->driver_data;
drivers/rtc/rtc-s3c.c +8 -8
@@ -667,17 +667,17 @@ static int s3c_rtc_resume(struct platform_device
 *pdev)
 #ifdef CONFIG_OF
 static const struct of_device_id s3c_rtc_dt_match[] = {
      {
-             .compatible = "samsung,s3c2410-rtc"
-             .data = TYPE_S3C2410,
+             .compatible = "samsung,s3c2410-rtc",
+             .data = (void *)TYPE_S3C2410,
      }, {
-             .compatible = "samsung,s3c2416-rtc"
-             .data = TYPE_S3C2416,
+             .compatible = "samsung,s3c2416-rtc",
+             .data = (void *)TYPE_S3C2416,
      }, {
-             .compatible = "samsung,s3c2443-rtc"
-             .data = TYPE_S3C2443,
+             .compatible = "samsung,s3c2443-rtc",
+             .data = (void *)TYPE_S3C2443,
      }, {
-             .compatible = "samsung,s3c6410-rtc"
-             .data = TYPE_S3C64XX,
+             .compatible = "samsung,s3c6410-rtc",
+             .data = (void *)TYPE_S3C64XX,
      },
      {},
};
--
1.6.6.rc2
Quoted 7 lines
Quoted 7 lines
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Thomas Abraham

author

2012-04-17 08:39 UTC #17 lore raw

PATCH 6/12 rtc-s3c: Fix breakage introduced by S3C2443/S3C2416 support

Quoted 4 lines · Kyungmin Park

Quoted 3 lines · Thomas Abraham
Quoted 2 lines · Kyungmin Park
Hi,

Quoted 8 lines

Quoted 6 lines
Quoted 1 line
It's already merged with different patch,
This is a repost of the patch from Heiko Stuebner which would be required to fix compilation issue for rtc driver. I think you are referring to that patch but it is not merged yet. So I am reposting it with this series.
No it's 3.4.0-rc3. it's already included.

Right, it is merged already. I was still on -rc2 and did not notice this change.

Thanks,
Thomas.

Quoted 104 lines

Quoted 104 lines
Thanks,
Thomas.
Quoted 87 lines
#ifdef CONFIG_OF
static const struct of_device_id s3c_rtc_dt_match[] = { ? ? ? ?{
? ? ? ? ? ? ? ?.compatible = "samsung,s3c2410-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C2410], ? ? ? ?}, {
? ? ? ? ? ? ? ?.compatible = "samsung,s3c2416-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C2416], ? ? ? ?}, {
? ? ? ? ? ? ? ?.compatible = "samsung,s3c2443-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C2443], ? ? ? ?}, {
? ? ? ? ? ? ? ?.compatible = "samsung,s3c6410-rtc", ? ? ? ? ? ? ? ?.data = &s3c_rtc_drv_data_array[TYPE_S3C64XX], ? ? ? ?},
? ? ? ?{},
};
MODULE_DEVICE_TABLE(of, s3c_rtc_dt_match);
#else
#define s3c_rtc_dt_match NULL
#endif
Thank you,
Kyungmin Park
Quoted 60 lines · Thomas Abraham
From: Heiko Stuebner <[email protected]>
Commits 7006ee4f (rtc-s3c: make room for more variants in devicetree block)
and 6c0a2365 (rtc-s3c: add variants for S3C2443 and S3C2416) introduced build-failures with enabled CONFIG_USE_OF option.
This patch fixes missing "," in s3c_rtc_dt_match and wrong handling of the of_device_id.data property.
Reported-by Sylwester Nawrocki <[email protected]>
Signed-off-by Heiko Stuebner <[email protected]>
---
?drivers/rtc/rtc-s3c.c | ? 18 +++++++++--------- ?1 files changed, 9 insertions(+), 9 deletions(-)
drivers/rtc/rtc-s3c.c +1 -1
index 9ccea13..c792b6d 100644
@@ -449,7 +449,7 @@ static inline int s3c_rtc_get_driver_data(struct
 platform_device *pdev)
 ? ? ? if (pdev->dev.of_node) {
 ? ? ? ? ? ? ? const struct of_device_id *match;
 ? ? ? ? ? ? ? match = of_match_node(s3c_rtc_dt_match, pdev->dev.of_node);
- ? ? ? ? ? ? return match->data;
+ ? ? ? ? ? ? return (int)match->data;
 ? ? ? }
?#endif
? ? ? return platform_get_device_id(pdev)->driver_data;
drivers/rtc/rtc-s3c.c +0 -0
@@ -667,17 +667,17 @@ static int s3c_rtc_resume(struct platform_device
 *pdev)
?#ifdef CONFIG_OF
?static const struct of_device_id s3c_rtc_dt_match[] = { ? ? ? {
- ? ? ? ? ? ? .compatible = "samsung,s3c2410-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C2410,
+ ? ? ? ? ? ? .compatible = "samsung,s3c2410-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C2410,
? ? ? }, {
- ? ? ? ? ? ? .compatible = "samsung,s3c2416-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C2416,
+ ? ? ? ? ? ? .compatible = "samsung,s3c2416-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C2416,
? ? ? }, {
- ? ? ? ? ? ? .compatible = "samsung,s3c2443-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C2443,
+ ? ? ? ? ? ? .compatible = "samsung,s3c2443-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C2443,
? ? ? }, {
- ? ? ? ? ? ? .compatible = "samsung,s3c6410-rtc"
- ? ? ? ? ? ? .data = TYPE_S3C64XX,
+ ? ? ? ? ? ? .compatible = "samsung,s3c6410-rtc",
+ ? ? ? ? ? ? .data = (void *)TYPE_S3C64XX,
? ? ? },
? ? ? {},
?};
--
1.6.6.rc2
Quoted 7 lines
Quoted 7 lines
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Thomas Abraham

author

2012-04-17 05:38 UTC #18 lore raw

PATCH 7/12 ARM: Exynos5: Modify the GIC physical address for static io-mapping

In reply to Thomas Abraham

From: Changhwan Youn <[email protected]>

Adapt to changes in GIC physical address in rev1 of Exynos5.

Signed-off-by Changhwan Youn <[email protected]>

---
 arch/arm/mach-exynos/common.c           |    4 ++--
 arch/arm/mach-exynos/include/mach/map.h |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/mach-exynos/common.c +2 -2

index 35ac675..457d031 100644
@@ -265,12 +265,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 	}, {
 		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
-		.length		= SZ_64K,
+		.length		= SZ_8K,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
-		.length		= SZ_64K,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	},
 };

arch/arm/mach-exynos/include/mach/map.h +2 -2

index 0e2292d..648d59b 100644
@@ -78,8 +78,8 @@
 
 #define EXYNOS4_PA_GIC_CPU		0x10480000
 #define EXYNOS4_PA_GIC_DIST		0x10490000
-#define EXYNOS5_PA_GIC_CPU		0x10480000
-#define EXYNOS5_PA_GIC_DIST		0x10490000
+#define EXYNOS5_PA_GIC_CPU		0x10482000
+#define EXYNOS5_PA_GIC_DIST		0x10481000
 
 #define EXYNOS4_PA_COREPERI		0x10500000
 #define EXYNOS4_PA_TWD			0x10500600

Signature · 1 line

1.6.6.rc2

Kyungmin Park

2012-04-17 06:31 UTC #19 lore raw

PATCH 7/12 ARM: Exynos5: Modify the GIC physical address for static io-mapping

Hi,

Quoted 3 lines · Thomas Abraham

From: Changhwan Youn <[email protected]>
Adapt to changes in GIC physical address in rev1 of Exynos5.

Does it different from rev0 and rev1? and does it support the rev1 only?

Thank you,
Kyungmin Park

Quoted 51 lines

Signed-off-by Changhwan Youn <[email protected]>

---
 arch/arm/mach-exynos/common.c           |    4 ++--
 arch/arm/mach-exynos/include/mach/map.h |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/mach-exynos/common.c +2 -2

index 35ac675..457d031 100644
@@ -265,12 +265,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 	}, {
 		.virtual	= (unsigned long)S5P_VA_GIC_CPU,
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
-		.length		= SZ_64K,
+		.length		= SZ_8K,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= (unsigned long)S5P_VA_GIC_DIST,
 		.pfn		= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
-		.length		= SZ_64K,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE,
 	},
 };

arch/arm/mach-exynos/include/mach/map.h +2 -3

index 0e2292d..648d59b 100644
@@ -78,8 +78,8 @@
 
 #define EXYNOS4_PA_GIC_CPU		0x10480000
 #define EXYNOS4_PA_GIC_DIST		0x10490000
-#define EXYNOS5_PA_GIC_CPU		0x10480000
-#define EXYNOS5_PA_GIC_DIST		0x10490000
+#define EXYNOS5_PA_GIC_CPU		0x10482000
+#define EXYNOS5_PA_GIC_DIST		0x10481000
 
 #define EXYNOS4_PA_COREPERI		0x10500000
 #define EXYNOS4_PA_TWD			0x10500600
--

1.6.6.rc2

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Thomas Abraham

author

2012-04-17 08:19 UTC #20 lore raw

PATCH 7/12 ARM: Exynos5: Modify the GIC physical address for static io-mapping

Quoted 8 lines · Kyungmin Park

Hi,
Quoted 3 lines · Thomas Abraham
From: Changhwan Youn <[email protected]>
Adapt to changes in GIC physical address in rev1 of Exynos5.
Does it different from rev0 and rev1? and does it support the rev1 only?

The physical base address of CPU and distributor portions of GIC are different on Rev0 and Rev1.0. This patch series overrides Rev0 and hence the mainline will support only Rev1.0. If the support for Rev0 should also be maintained (if there are users of it), then I can maintain the support for Rev0 also.

Thanks,
Thomas.

Quoted 59 lines

Thank you,
Kyungmin Park
Quoted 45 lines
Signed-off-by Changhwan Youn <[email protected]>
---
?arch/arm/mach-exynos/common.c ? ? ? ? ? | ? ?4 ++-- ?arch/arm/mach-exynos/include/mach/map.h | ? ?4 ++-- ?2 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/mach-exynos/common.c +2 -2
index 35ac675..457d031 100644
@@ -265,12 +265,12 @@ static struct map_desc exynos5_iodesc[] __initdata = {
 ? ? ? }, {
 ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_GIC_CPU,
 ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS5_PA_GIC_CPU),
- ? ? ? ? ? ? .length ? ? ? ? = SZ_64K,
+ ? ? ? ? ? ? .length ? ? ? ? = SZ_8K,
 ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
 ? ? ? }, {
 ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S5P_VA_GIC_DIST,
 ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(EXYNOS5_PA_GIC_DIST),
- ? ? ? ? ? ? .length ? ? ? ? = SZ_64K,
+ ? ? ? ? ? ? .length ? ? ? ? = SZ_4K,
 ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
 ? ? ? },
 ?};
arch/arm/mach-exynos/include/mach/map.h +0 -0
index 0e2292d..648d59b 100644
@@ -78,8 +78,8 @@
 
?#define EXYNOS4_PA_GIC_CPU ? ? ? ? ? 0x10480000
?#define EXYNOS4_PA_GIC_DIST ? ? ? ? ?0x10490000
arch/arm/mach-exynos/include/mach/map.h +2 -2
-#define EXYNOS5_PA_GIC_CPU ? ? ? ? ? 0x10480000
-#define EXYNOS5_PA_GIC_DIST ? ? ? ? ?0x10490000
+#define EXYNOS5_PA_GIC_CPU ? ? ? ? ? 0x10482000
+#define EXYNOS5_PA_GIC_DIST ? ? ? ? ?0x10481000
?#define EXYNOS4_PA_COREPERI ? ? ? ? ?0x10500000 ?#define EXYNOS4_PA_TWD ? ? ? ? ? ? ? ? ? ? ? 0x10500600 --
1.6.6.rc2
Quoted 6 lines
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Thomas Abraham

author

2012-04-17 05:38 UTC #21 lore raw

PATCH 8/12 gpio/samsung: add GPC4 bank instance

In reply to Thomas Abraham

From: Sangsu Park <[email protected]>

Add GPC4 bank instance which is included in rev1 of Exynos5.

Cc Grant Likely <[email protected]>

Signed-off-by Sangsu Park <[email protected]>

---
 arch/arm/mach-exynos/include/mach/gpio.h |    9 ++++++---
 drivers/gpio/gpio-samsung.c              |    8 ++++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

arch/arm/mach-exynos/include/mach/gpio.h +6 -3

index d7498af..df5612b 100644
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 #define EXYNOS5_GPIO_B2_NR	(4)
 #define EXYNOS5_GPIO_B3_NR	(4)
 #define EXYNOS5_GPIO_C0_NR	(7)
-#define EXYNOS5_GPIO_C1_NR	(7)
+#define EXYNOS5_GPIO_C1_NR	(4)
 #define EXYNOS5_GPIO_C2_NR	(7)
 #define EXYNOS5_GPIO_C3_NR	(7)
-#define EXYNOS5_GPIO_D0_NR	(8)
+#define EXYNOS5_GPIO_C4_NR	(8)
+#define EXYNOS5_GPIO_D0_NR	(4)
 #define EXYNOS5_GPIO_D1_NR	(8)
 #define EXYNOS5_GPIO_Y0_NR	(6)
 #define EXYNOS5_GPIO_Y1_NR	(4)

@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
 	EXYNOS5_GPIO_C1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
 	EXYNOS5_GPIO_C2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
 	EXYNOS5_GPIO_C3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_C4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
 	EXYNOS5_GPIO_D1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
 	EXYNOS5_GPIO_Y0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
 	EXYNOS5_GPIO_Y1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),

@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 #define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))
 #define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))
 #define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)	(EXYNOS5_GPIO_C4_START + (_nr))
 #define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))
 #define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))
 #define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))

drivers/gpio/gpio-samsung.c +8 -0

index 4627787..0153bb9 100644
@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
 		},
 	}, {
 		.chip	= {
+			.base	= EXYNOS5_GPC4(0),
+			.ngpio	= EXYNOS5_GPIO_C4_NR,
+			.label	= "GPC4",
+		},
+	}, {
+		.chip	= {
 			.base	= EXYNOS5_GPD0(0),
 			.ngpio	= EXYNOS5_GPIO_D0_NR,
 			.label	= "GPD0",

@@ -2880,6 +2886,8 @@ static __init int samsung_gpiolib_init(void)
 		for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
 			chip->base = gpx_base;
 
+		exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
+
 		chip = exynos5_gpios_1;
 		nr_chips = ARRAY_SIZE(exynos5_gpios_1);

Signature · 1 line

1.6.6.rc2

Kyungmin Park

2012-04-17 06:33 UTC #22 lore raw

PATCH 8/12 gpio/samsung: add GPC4 bank instance

Quoted 66 lines · Thomas Abraham

From: Sangsu Park <[email protected]>

Add GPC4 bank instance which is included in rev1 of Exynos5.

Cc Grant Likely <[email protected]>

Signed-off-by Sangsu Park <[email protected]>

---
 arch/arm/mach-exynos/include/mach/gpio.h |    9 ++++++---
 drivers/gpio/gpio-samsung.c              |    8 ++++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

arch/arm/mach-exynos/include/mach/gpio.h +6 -3

index d7498af..df5612b 100644
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 #define EXYNOS5_GPIO_B2_NR	(4)
 #define EXYNOS5_GPIO_B3_NR	(4)
 #define EXYNOS5_GPIO_C0_NR	(7)
-#define EXYNOS5_GPIO_C1_NR	(7)
+#define EXYNOS5_GPIO_C1_NR	(4)
 #define EXYNOS5_GPIO_C2_NR	(7)
 #define EXYNOS5_GPIO_C3_NR	(7)
-#define EXYNOS5_GPIO_D0_NR	(8)
+#define EXYNOS5_GPIO_C4_NR	(8)
+#define EXYNOS5_GPIO_D0_NR	(4)
 #define EXYNOS5_GPIO_D1_NR	(8)
 #define EXYNOS5_GPIO_Y0_NR	(6)
 #define EXYNOS5_GPIO_Y1_NR	(4)

@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
 	EXYNOS5_GPIO_C1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
 	EXYNOS5_GPIO_C2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
 	EXYNOS5_GPIO_C3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_C4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
 	EXYNOS5_GPIO_D1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
 	EXYNOS5_GPIO_Y0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
 	EXYNOS5_GPIO_Y1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),

@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 #define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))
 #define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))
 #define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)	(EXYNOS5_GPIO_C4_START + (_nr))
 #define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))
 #define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))
 #define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))

drivers/gpio/gpio-samsung.c +6 -0

index 4627787..0153bb9 100644
@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
 		},
 	}, {
 		.chip	= {
+			.base	= EXYNOS5_GPC4(0),
+			.ngpio	= EXYNOS5_GPIO_C4_NR,
+			.label	= "GPC4",
+		},
+	}, {
+		.chip	= {
 			.base	= EXYNOS5_GPD0(0),
 			.ngpio	= EXYNOS5_GPIO_D0_NR,
 			.label	= "GPD0",

drivers/gpio/gpio-samsung.c static __init int samsung_gpiolib_init(void) · line 2889

Quoted 4 lines

drivers/gpio/gpio-samsung.c +1 -0

@@ -2880,6 +2886,8 @@ static __init int samsung_gpiolib_init(void)
 		for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
 			chip->base = gpx_base;
 
+		exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;

'11' seems dangerous. I think you add comments here and above to know '11' meaning.

Quoted 13 lines

drivers/gpio/gpio-samsung.c +1 -1
+
 		chip = exynos5_gpios_1;
 		nr_chips = ARRAY_SIZE(exynos5_gpios_1);
 
--
1.6.6.rc2
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Thomas Abraham

author

2012-04-17 08:24 UTC #23 lore raw

PATCH 8/12 gpio/samsung: add GPC4 bank instance

Quoted 70 lines · Kyungmin Park

Quoted 69 lines · Thomas Abraham

From: Sangsu Park <[email protected]>

Add GPC4 bank instance which is included in rev1 of Exynos5.

Cc Grant Likely <[email protected]>

Signed-off-by Sangsu Park <[email protected]>

---
?arch/arm/mach-exynos/include/mach/gpio.h | ? ?9 ++++++--- ?drivers/gpio/gpio-samsung.c ? ? ? ? ? ? ?| ? ?8 ++++++++ ?2 files changed, 14 insertions(+), 3 deletions(-)

arch/arm/mach-exynos/include/mach/gpio.h +6 -3

index d7498af..df5612b 100644
@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
 ?#define EXYNOS5_GPIO_B2_NR ? (4)
 ?#define EXYNOS5_GPIO_B3_NR ? (4)
 ?#define EXYNOS5_GPIO_C0_NR ? (7)
-#define EXYNOS5_GPIO_C1_NR ? (7)
+#define EXYNOS5_GPIO_C1_NR ? (4)
 ?#define EXYNOS5_GPIO_C2_NR ? (7)
 ?#define EXYNOS5_GPIO_C3_NR ? (7)
-#define EXYNOS5_GPIO_D0_NR ? (8)
+#define EXYNOS5_GPIO_C4_NR ? (8)
+#define EXYNOS5_GPIO_D0_NR ? (4)
 ?#define EXYNOS5_GPIO_D1_NR ? (8)
 ?#define EXYNOS5_GPIO_Y0_NR ? (6)
 ?#define EXYNOS5_GPIO_Y1_NR ? (4)

@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
 ? ? ? EXYNOS5_GPIO_C1_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
 ? ? ? EXYNOS5_GPIO_C2_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
 ? ? ? EXYNOS5_GPIO_C3_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
- ? ? EXYNOS5_GPIO_D0_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+ ? ? EXYNOS5_GPIO_C4_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+ ? ? EXYNOS5_GPIO_D0_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
 ? ? ? EXYNOS5_GPIO_D1_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
 ? ? ? EXYNOS5_GPIO_Y0_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
 ? ? ? EXYNOS5_GPIO_Y1_START ? ? ? ? ? = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),

@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
 ?#define EXYNOS5_GPC1(_nr) ? ?(EXYNOS5_GPIO_C1_START + (_nr))
 ?#define EXYNOS5_GPC2(_nr) ? ?(EXYNOS5_GPIO_C2_START + (_nr))
 ?#define EXYNOS5_GPC3(_nr) ? ?(EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr) ? ?(EXYNOS5_GPIO_C4_START + (_nr))
 ?#define EXYNOS5_GPD0(_nr) ? ?(EXYNOS5_GPIO_D0_START + (_nr))
 ?#define EXYNOS5_GPD1(_nr) ? ?(EXYNOS5_GPIO_D1_START + (_nr))
 ?#define EXYNOS5_GPY0(_nr) ? ?(EXYNOS5_GPIO_Y0_START + (_nr))

drivers/gpio/gpio-samsung.c +6 -0

index 4627787..0153bb9 100644
@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
 ? ? ? ? ? ? ? },
 ? ? ? }, {
 ? ? ? ? ? ? ? .chip ? = {
+ ? ? ? ? ? ? ? ? ? ? .base ? = EXYNOS5_GPC4(0),
+ ? ? ? ? ? ? ? ? ? ? .ngpio ?= EXYNOS5_GPIO_C4_NR,
+ ? ? ? ? ? ? ? ? ? ? .label ?= "GPC4",
+ ? ? ? ? ? ? },
+ ? ? }, {
+ ? ? ? ? ? ? .chip ? = {
 ? ? ? ? ? ? ? ? ? ? ? .base ? = EXYNOS5_GPD0(0),
 ? ? ? ? ? ? ? ? ? ? ? .ngpio ?= EXYNOS5_GPIO_D0_NR,
 ? ? ? ? ? ? ? ? ? ? ? .label ?= "GPD0",

@@ -2880,6 +2886,8 @@ static __init int samsung_gpiolib_init(void)
 ? ? ? ? ? ? ? for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
 ? ? ? ? ? ? ? ? ? ? ? chip->base = gpx_base;

Quoted 3 lines

drivers/gpio/gpio-samsung.c static __init int samsung_gpiolib_init(void) · line 2889
Quoted 1 line
drivers/gpio/gpio-samsung.c +1 -0
+ ? ? ? ? ? ? exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
'11' seems dangerous. I think you add comments here and above to know '11' meaning.

Yes, true. But these will go away when the Samsung pinctrl driver will be merged. For now, I will put a comment to explain the meaning of 11.

Thanks for reviewing the patches.

Thanks,
Thomas.

Quoted 13 lines

Quoted 13 lines
drivers/gpio/gpio-samsung.c +1 -1
+
 ? ? ? ? ? ? ? chip = exynos5_gpios_1;
 ? ? ? ? ? ? ? nr_chips = ARRAY_SIZE(exynos5_gpios_1);
 
--
1.6.6.rc2
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Kukjin Kim

2012-04-19 00:36 UTC #24 lore raw

PATCH 8/12 gpio/samsung: add GPC4 bank instance

In reply to Thomas Abraham

Quoted 6 lines · Thomas Abraham

From: Sangsu Park<[email protected]>
Add GPC4 bank instance which is included in rev1 of Exynos5.
Cc Grant Likely<[email protected]>
Signed-off-by Sangsu Park<[email protected]>

Where is your sign??? Your sign MUST be included here.

Quoted 10 lines

---
  arch/arm/mach-exynos/include/mach/gpio.h |    9 ++++++---
  drivers/gpio/gpio-samsung.c              |    8 ++++++++
  2 files changed, 14 insertions(+), 3 deletions(-)

arch/arm/mach-exynos/include/mach/gpio.h +0 -0

index d7498af..df5612b 100644

arch/arm/mach-exynos/include/mach/gpio.h enum exynos4_gpio_number { · line 159

Quoted 9 lines

arch/arm/mach-exynos/include/mach/gpio.h +2 -2

@@ -153,10 +153,11 @@ enum exynos4_gpio_number {
  #define EXYNOS5_GPIO_B2_NR	(4)
  #define EXYNOS5_GPIO_B3_NR	(4)
  #define EXYNOS5_GPIO_C0_NR	(7)
-#define EXYNOS5_GPIO_C1_NR	(7)
+#define EXYNOS5_GPIO_C1_NR	(4)
  #define EXYNOS5_GPIO_C2_NR	(7)
  #define EXYNOS5_GPIO_C3_NR	(7)
-#define EXYNOS5_GPIO_D0_NR	(8)
+#define EXYNOS5_GPIO_C4_NR	(8)

Should be 7. See the manual again :-(

Quoted 40 lines

arch/arm/mach-exynos/include/mach/gpio.h +4 -1

+#define EXYNOS5_GPIO_D0_NR	(4)
  #define EXYNOS5_GPIO_D1_NR	(8)
  #define EXYNOS5_GPIO_Y0_NR	(6)
  #define EXYNOS5_GPIO_Y1_NR	(4)

@@ -199,7 +200,8 @@ enum exynos5_gpio_number {
  	EXYNOS5_GPIO_C1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
  	EXYNOS5_GPIO_C2_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
  	EXYNOS5_GPIO_C3_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
-	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_C4_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
+	EXYNOS5_GPIO_D0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
  	EXYNOS5_GPIO_D1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
  	EXYNOS5_GPIO_Y0_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
  	EXYNOS5_GPIO_Y1_START		= EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),

@@ -242,6 +244,7 @@ enum exynos5_gpio_number {
  #define EXYNOS5_GPC1(_nr)	(EXYNOS5_GPIO_C1_START + (_nr))
  #define EXYNOS5_GPC2(_nr)	(EXYNOS5_GPIO_C2_START + (_nr))
  #define EXYNOS5_GPC3(_nr)	(EXYNOS5_GPIO_C3_START + (_nr))
+#define EXYNOS5_GPC4(_nr)	(EXYNOS5_GPIO_C4_START + (_nr))
  #define EXYNOS5_GPD0(_nr)	(EXYNOS5_GPIO_D0_START + (_nr))
  #define EXYNOS5_GPD1(_nr)	(EXYNOS5_GPIO_D1_START + (_nr))
  #define EXYNOS5_GPY0(_nr)	(EXYNOS5_GPIO_Y0_START + (_nr))

drivers/gpio/gpio-samsung.c +6 -0

index 4627787..0153bb9 100644
@@ -2452,6 +2452,12 @@ static struct samsung_gpio_chip exynos5_gpios_1[] = {
  		},
  	}, {
  		.chip	= {
+			.base	= EXYNOS5_GPC4(0),
+			.ngpio	= EXYNOS5_GPIO_C4_NR,
+			.label	= "GPC4",
+		},
+	}, {
+		.chip	= {
  			.base	= EXYNOS5_GPD0(0),
  			.ngpio	= EXYNOS5_GPIO_D0_NR,
  			.label	= "GPD0",

drivers/gpio/gpio-samsung.c static __init int samsung_gpiolib_init(void) · line 2893

Quoted 8 lines

drivers/gpio/gpio-samsung.c +2 -0

@@ -2880,6 +2886,8 @@ static __init int samsung_gpiolib_init(void)
  		for (i = 0; i<  4; i++, chip++, gpx_base += 0x20)
  			chip->base = gpx_base;
 
+		exynos5_gpios_1[11].base = gpio_base1 + 0x2E0;
+
  		chip = exynos5_gpios_1;
  		nr_chips = ARRAY_SIZE(exynos5_gpios_1);

This is wrong. If you add GPC4 between GPC3 and GPD0, you need to increase the gpx's counter like following and need to update IRQ_GPIO1_NR_GROUPS as well.

drivers/gpio/gpio-samsung.c +1 -1

index 19d6fc0..1af0fa5 100644
@@ -2875,7 +2875,7 @@ static __init int samsung_gpiolib_init(void)
                }
 
                /* need to set base address for gpx */
-               chip = &exynos5_gpios_1[20];
+               chip = &exynos5_gpios_1[21];
                gpx_base = gpio_base1 + 0xC00;
                for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
                        chip->base = gpx_base;

(quoted diff) +0 -0

b/arch/arm/mach-exynos/inc
index 591e785..887788d 100644

arch/arm/mach-exynos/include/mach/irqs.h +1 -1

@@ -446,7 +446,7 @@
 
 #define EXYNOS5_MAX_COMBINER_NR                32
 
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS    13
+#define EXYNOS5_IRQ_GPIO1_NR_GROUPS    14
 #define EXYNOS5_IRQ_GPIO2_NR_GROUPS    9
 #define EXYNOS5_IRQ_GPIO3_NR_GROUPS    5
 #define EXYNOS5_IRQ_GPIO4_NR_GROUPS    1

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-04-17 05:38 UTC #25 lore raw

PATCH 9/12 ARM: Exynos5: Add pre-divider and fout mux clocks for bpll and mpll

In reply to Thomas Abraham

From: Kisoo Yu <[email protected]>

The fout clock of BPLL and MPLL have a selectable source in rev1 of Exynos5. The clock options are a fixed divided by 2 clock and the output of the PLL itself. Add support for these new clock instances.

Signed-off-by Kisoo Yu <[email protected]>

---
 arch/arm/mach-exynos/clock-exynos5.c           |   73 +++++++++++++++++++++++-
 arch/arm/mach-exynos/include/mach/regs-clock.h |    2 +
 arch/arm/plat-s5p/clock.c                      |   11 ----
 3 files changed, 74 insertions(+), 12 deletions(-)

arch/arm/mach-exynos/clock-exynos5.c +72 -1

index 0230ba8..3aa3fed 100644
@@ -165,6 +165,39 @@ static struct clksrc_clk exynos5_clk_sclk_apll = {
 	.reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
 };
 
+static struct clk clk_fout_bpll_div2 = {
+	.name	= "fout_bpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_bpll_fout_list[] = {
+	[0] = &clk_fout_bpll_div2,
+	[1] = &clk_fout_bpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_bpll_fout = {
+	.sources	= exynos5_clkset_mout_bpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_bpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+	.clk	= {
+		.name		= "mout_bpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_bpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+/* Possible clock sources for BPLL Mux */
+static struct clk *clk_src_bpll_list[] = {
+	[0] = &clk_fin_bpll,
+	[1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+struct clksrc_sources clk_src_bpll = {
+	.sources	= clk_src_bpll_list,
+	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
+};
+
 static struct clksrc_clk exynos5_clk_mout_bpll = {
 	.clk	= {
 		.name		= "mout_bpll",

@@ -207,11 +240,43 @@ static struct clksrc_clk exynos5_clk_mout_epll = {
 	.reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
 };
 
+static struct clk clk_fout_mpll_div2 = {
+	.name	= "fout_mpll_div2",
+};
+
+static struct clk *exynos5_clkset_mout_mpll_fout_list[] = {
+	[0] = &clk_fout_mpll_div2,
+	[1] = &clk_fout_mpll,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_mpll_fout = {
+	.sources	= exynos5_clkset_mout_mpll_fout_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clkset_mout_mpll_fout_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+	.clk	= {
+		.name		= "mout_mpll_fout",
+	},
+	.sources = &exynos5_clkset_mout_mpll_fout,
+	.reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+	[0] = &clk_fin_mpll,
+	[1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+struct clksrc_sources exynos5_clk_src_mpll = {
+	.sources	= exynos5_clk_src_mpll_list,
+	.nr_sources	= ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
 struct clksrc_clk exynos5_clk_mout_mpll = {
 	.clk = {
 		.name		= "mout_mpll",
 	},
-	.sources = &clk_src_mpll,
+	.sources = &exynos5_clk_src_mpll,
 	.reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
 };

@@ -1033,10 +1098,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
 	&exynos5_clk_mout_apll,
 	&exynos5_clk_sclk_apll,
 	&exynos5_clk_mout_bpll,
+	&exynos5_clk_mout_bpll_fout,
 	&exynos5_clk_mout_bpll_user,
 	&exynos5_clk_mout_cpll,
 	&exynos5_clk_mout_epll,
 	&exynos5_clk_mout_mpll,
+	&exynos5_clk_mout_mpll_fout,
 	&exynos5_clk_mout_mpll_user,
 	&exynos5_clk_vpllsrc,
 	&exynos5_clk_sclk_vpll,

@@ -1101,6 +1168,8 @@ static struct clk *exynos5_clks[] __initdata = {
 	&exynos5_clk_sclk_hdmi27m,
 	&exynos5_clk_sclk_hdmiphy,
 	&clk_fout_bpll,
+	&clk_fout_bpll_div2,
+	&clk_fout_mpll_div2,
 	&clk_fout_cpll,
 	&exynos5_clk_armclk,
 };

@@ -1266,8 +1335,10 @@ void __init_or_cpufreq exynos5_setup_clocks(void)
 
 	clk_fout_apll.ops = &exynos5_fout_apll_ops;
 	clk_fout_bpll.rate = bpll;
+	clk_fout_bpll_div2.rate = bpll >> 1;
 	clk_fout_cpll.rate = cpll;
 	clk_fout_mpll.rate = mpll;
+	clk_fout_mpll_div2.rate = mpll >> 1;
 	clk_fout_epll.rate = epll;
 	clk_fout_vpll.rate = vpll;

arch/arm/mach-exynos/include/mach/regs-clock.h +2 -0

index dba83e9..834ab17 100644
@@ -318,6 +318,8 @@
 #define EXYNOS5_CLKGATE_IP_PERIS		EXYNOS_CLKREG(0x10960)
 #define EXYNOS5_CLKGATE_BLOCK			EXYNOS_CLKREG(0x10980)
 
+#define EXYNOS5_PLL_DIV2_SEL			EXYNOS_CLKREG(0x20A24)
+
 #define EXYNOS5_BPLL_CON0			EXYNOS_CLKREG(0x20110)
 #define EXYNOS5_CLKSRC_CDREX			EXYNOS_CLKREG(0x20200)
 #define EXYNOS5_CLKDIV_CDREX			EXYNOS_CLKREG(0x20500)

arch/arm/plat-s5p/clock.c +0 ~~-11~~

index f68a9bb..bea0907 100644
@@ -115,17 +115,6 @@ struct clksrc_sources clk_src_apll = {
 	.nr_sources	= ARRAY_SIZE(clk_src_apll_list),
 };
 
-/* Possible clock sources for BPLL Mux */
-static struct clk *clk_src_bpll_list[] = {
-	[0] = &clk_fin_bpll,
-	[1] = &clk_fout_bpll,
-};
-
-struct clksrc_sources clk_src_bpll = {
-	.sources	= clk_src_bpll_list,
-	.nr_sources	= ARRAY_SIZE(clk_src_bpll_list),
-};
-
 /* Possible clock sources for CPLL Mux */
 static struct clk *clk_src_cpll_list[] = {
 	[0] = &clk_fin_cpll,

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2012-04-17 05:38 UTC #26 lore raw

PATCH 10/12 ARM: Exynos: Redefine IRQ_MCT_L0,1 definition

In reply to Thomas Abraham

From: Changhwan Youn <[email protected]>

Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of Exynos5.

Signed-off-by Changhwan Youn <[email protected]>

---
 arch/arm/mach-exynos/include/mach/irqs.h |    4 ++--
 arch/arm/mach-exynos/mct.c               |   17 +++++++++++------
 2 files changed, 13 insertions(+), 8 deletions(-)

arch/arm/mach-exynos/include/mach/irqs.h +2 -2

index 1161675..86e75f5 100644
@@ -320,6 +320,8 @@
 #define EXYNOS5_IRQ_SATA		IRQ_SPI(115)
 #define EXYNOS5_IRQ_NFCON		IRQ_SPI(116)
 
+#define EXYNOS5_IRQ_MCT_L0		IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1		IRQ_SPI(121)
 #define EXYNOS5_IRQ_MMC44		IRQ_SPI(123)
 #define EXYNOS5_IRQ_MDMA1		IRQ_SPI(124)
 #define EXYNOS5_IRQ_FIMC_LITE0		IRQ_SPI(125)

@@ -399,8 +401,6 @@
 #define EXYNOS5_IRQ_FIMD1_SYSTEM	COMBINER_IRQ(18, 6)
 
 #define EXYNOS5_IRQ_EINT0		COMBINER_IRQ(23, 0)
-#define EXYNOS5_IRQ_MCT_L0		COMBINER_IRQ(23, 1)
-#define EXYNOS5_IRQ_MCT_L1		COMBINER_IRQ(23, 2)
 #define EXYNOS5_IRQ_MCT_G0		COMBINER_IRQ(23, 3)
 #define EXYNOS5_IRQ_MCT_G1		COMBINER_IRQ(23, 4)
 #define EXYNOS5_IRQ_MCT_G2		COMBINER_IRQ(23, 5)

arch/arm/mach-exynos/mct.c +11 -6

index 897d9a9..b601fb8 100644
@@ -388,6 +388,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 {
 	struct mct_clock_event_device *mevt;
 	unsigned int cpu = smp_processor_id();
+	int mct_lx_irq;
 
 	mevt = this_cpu_ptr(&percpu_mct_tick);
 	mevt->evt = evt;

@@ -414,14 +415,18 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
 
 	if (mct_int_type == MCT_INT_SPI) {
 		if (cpu == 0) {
+			mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+						EXYNOS5_IRQ_MCT_L0;
 			mct_tick0_event_irq.dev_id = mevt;
-			evt->irq = EXYNOS4_IRQ_MCT_L0;
-			setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
+			evt->irq = mct_lx_irq;
+			setup_irq(mct_lx_irq, &mct_tick0_event_irq);
 		} else {
+			mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+						EXYNOS5_IRQ_MCT_L1;
 			mct_tick1_event_irq.dev_id = mevt;
-			evt->irq = EXYNOS4_IRQ_MCT_L1;
-			setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
-			irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
+			evt->irq = mct_lx_irq;
+			setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+			irq_set_affinity(mct_lx_irq, cpumask_of(1));
 		}
 	} else {
 		enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);

@@ -473,7 +478,7 @@ static void __init exynos4_timer_resources(void)
 
 static void __init exynos4_timer_init(void)
 {
-	if (soc_is_exynos4210())
+	if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
 		mct_int_type = MCT_INT_SPI;
 	else
 		mct_int_type = MCT_INT_PPI;

Signature · 1 line

1.6.6.rc2

Kukjin Kim

2012-04-19 01:00 UTC #27 lore raw

PATCH 10/12 ARM: Exynos: Redefine IRQ_MCT_L0,1 definition

Quoted 5 lines · Thomas Abraham

From: Changhwan Youn<[email protected]>
Redefine IRQ_MCT_L0,1 irq definition as it is changed in rev1 of Exynos5.
Signed-off-by Changhwan Youn<[email protected]>

Basically, looks ok after initial reviewing but you need to add your sign here. As you know, it is a legal issue and _very_ important.

Please resend with your sign after Changhwan's sign.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2012-04-17 05:39 UTC #28 lore raw

PATCH 11/12 ARM: Exynos5: Update device tree source files

In reply to Thomas Abraham

Updated Exynos5 device tree source files to reflect changes in rev1 of Exynos5 SoC. This includes new additions to the Exynos5 dtsi and SMDK5250 dts files and few minor fixes.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/boot/dts/exynos5250-smdk5250.dts |   52 +++++++++++++++++++++++++++++
 arch/arm/boot/dts/exynos5250.dtsi         |   44 +++++++-----------------
 2 files changed, 65 insertions(+), 31 deletions(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +52 -0

index 399d17b..bcc4b89 100644
@@ -23,4 +23,56 @@
 	chosen {
 		bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
 	};
+
+	i2c@12C60000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <20000>;
+		gpios = <&gpb3 0 2 3 0>,
+			<&gpb3 1 2 3 0>;
+
+		eeprom@50 {
+			compatible = "samsung,s524ad0xd1";
+			reg = <0x50>;
+		};
+	};
+
+	i2c@12C70000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		samsung,i2c-sda-delay = <100>;
+		samsung,i2c-max-bus-freq = <20000>;
+		gpios = <&gpb3 2 2 3 0>,
+			<&gpb3 3 2 3 0>;
+
+		eeprom@51 {
+			compatible = "samsung,s524ad0xd1";
+			reg = <0x51>;
+		};
+	};
+
+	i2c@12C80000 {
+		status = "disabled";
+	};
+
+	i2c@12C90000 {
+		status = "disabled";
+	};
+
+	i2c@12CA0000 {
+		status = "disabled";
+	};
+
+	i2c@12CB0000 {
+		status = "disabled";
+	};
+
+	i2c@12CC0000 {
+		status = "disabled";
+	};
+
+	i2c@12CD0000 {
+		status = "disabled";
+	};
 };

arch/arm/boot/dts/exynos5250.dtsi +13 ~~-31~~

92 lines not on this page · raw message

Signature · 1 line

1.6.6.rc2

Thomas Abraham

author

2012-04-17 05:39 UTC #29 lore raw

PATCH 12/12 ARM: Exynos5: Update device tree enabled machine file

In reply to Thomas Abraham

Add AUXDATA for i2c and MDMA controllers of Exynos5.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos/mach-exynos5-dt.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

arch/arm/mach-exynos/mach-exynos5-dt.c +6 -1

index 4711c89..8adc061 100644
@@ -43,9 +43,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"exynos4210-uart.2", NULL),
 	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
 				"exynos4210-uart.3", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+				"s3c2440-i2c.0", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+				"s3c2440-i2c.1", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
 	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA0, "dma-pl330.2", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.3", NULL),
 	{},
 };

Signature · 1 line

1.6.6.rc2

Kukjin Kim

2012-04-19 00:23 UTC #30 lore raw

PATCH 12/12 ARM: Exynos5: Update device tree enabled machine file

Quoted 14 lines · Thomas Abraham

Add AUXDATA for i2c and MDMA controllers of Exynos5.

Signed-off-by Thomas Abraham<[email protected]>

---
  arch/arm/mach-exynos/mach-exynos5-dt.c |    7 ++++++-
  1 files changed, 6 insertions(+), 1 deletions(-)

arch/arm/mach-exynos/mach-exynos5-dt.c +0 -0

index 4711c89..8adc061 100644
@@ -43,9 +43,14 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
  				"exynos4210-uart.2", NULL),
  	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,

arch/arm/mach-exynos/mach-exynos5-dt.c static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = { · line 53

Quoted 10 lines

arch/arm/mach-exynos/mach-exynos5-dt.c +6 -1

  				"exynos4210-uart.3", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+				"s3c2440-i2c.0", NULL),
+	OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+				"s3c2440-i2c.1", NULL),
  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
  	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
-	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA0, "dma-pl330.2", NULL),
+	OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.3", NULL),

Probably, you missed my comments on your previous patches. Fixed on rc3.

So just need to update i2c stuff now.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.