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i.MX6: mx6q_sabrelite: add SATA bindings

PATCH Superseded Eric Nelson 4 participants 6 messages Apr 25, 2012 – Apr 30, 2012 1 message not in the archive

v3 of 5 Superseded Latest is v5 →

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A message that is not in the archive (sent off-list or not yet received): http://lists.denx.de/pipermail/u-boot/2012-March/120150.html

Eric Nelson

author
#1 lore raw

PATCH v3 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Signed-off-by Eric Nelson <[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   32 +++++++++++++++++++++++++
 include/configs/mx6qsabrelite.h               |   13 ++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)
board/freescale/mx6qsabrelite/mx6qsabrelite.c +32 -0
index 1d09a72..c9a108f 100644
@@ -25,6 +25,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>

@@ -267,6 +269,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int rval = enable_sata_clock();
+	if (rval)
+		return rval ;
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0 ;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();

@@ -283,6 +311,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }
include/configs/mx6qsabrelite.h +13 -0
index f52c3c7..1d92dd0 100644
@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
Signature · 1 line
1.7.9
#2 lore raw

PATCH v3 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Hi Eric,

Quoted 18 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   32 +++++++++++++++++++++++++
  include/configs/mx6qsabrelite.h               |   13 ++++++++++
  2 files changed, 45 insertions(+), 0 deletions(-)
board/freescale/mx6qsabrelite/mx6qsabrelite.c +0 -0
index 1d09a72..c9a108f 100644

board/freescale/mx6qsabrelite/mx6qsabrelite.c line 28

Quoted 4 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +1 -0
@@ -25,6 +25,8 @@
  #include<asm/arch/imx-regs.h>
  #include<asm/arch/mx6x_pins.h>
  #include<asm/arch/iomux-v3.h>
+#include<asm/arch/ccm_regs.h>

Do we need ccm_regs.h here?

Best regards

Dirk

author
#3 lore raw

PATCH v3 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Hi Dirk,

Quoted 16 lines · Dirk Behme

Hi Eric,

Quoted 13 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

board/freescale/mx6qsabrelite/mx6qsabrelite.c | 32 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 ++++++++++

2 files changed, 45 insertions(+), 0 deletions(-)
Quoted 13 lines

board/freescale/mx6qsabrelite/mx6qsabrelite.c line 28

Quoted 10 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +1 -0
index 1d09a72..c9a108f 100644
@@ -25,6 +25,8 @@
 #include<asm/arch/imx-regs.h>
 #include<asm/arch/mx6x_pins.h>
 #include<asm/arch/iomux-v3.h>
+#include<asm/arch/ccm_regs.h>

Do we need ccm_regs.h here?

Nope. Good catch.

I'll generate a V4 in a day or two to allow some other review.

Stefano, what's the status of the dwc_ahsata driver?

Without that, the bindings are clearly useless.

Regards,

Eric

#4 lore raw

PATCH v3 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Quoted 34 lines · Eric Nelson

Hi Dirk,

Quoted 17 lines · Dirk Behme

Hi Eric,

Quoted 14 lines · Eric Nelson
Signed-off-by Eric Nelson<[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

board/freescale/mx6qsabrelite/mx6qsabrelite.c | 32
+++++++++++++++++++++++++
include/configs/mx6qsabrelite.h | 13 ++++++++++

2 files changed, 45 insertions(+), 0 deletions(-)
Quoted 13 lines

board/freescale/mx6qsabrelite/mx6qsabrelite.c line 28

Quoted 10 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +1 -0
index 1d09a72..c9a108f 100644
@@ -25,6 +25,8 @@
 #include<asm/arch/imx-regs.h>
 #include<asm/arch/mx6x_pins.h>
 #include<asm/arch/iomux-v3.h>
+#include<asm/arch/ccm_regs.h>

Do we need ccm_regs.h here?

Quoted 5 lines

Nope. Good catch.

I'll generate a V4 in a day or two to allow some other review.

Stefano, what's the status of the dwc_ahsata driver?

Hi Eric, hi Dirk,

I have merged the dwc_ahsata into the master branch, and the drive ris available.

Best regards,
Stefano Babic

Signature · 5 lines
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
#5 lore raw

PATCH v3 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

In reply to Eric Nelson

Dear Eric Nelson,

Quoted 31 lines
Signed-off-by Eric Nelson <[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

V3 returns immediately from setup_sata() if enable_sata_clock() returns an error.

 board/freescale/mx6qsabrelite/mx6qsabrelite.c |   32
+++++++++++++++++++++++++ include/configs/mx6qsabrelite.h               | 
 13 ++++++++++
 2 files changed, 45 insertions(+), 0 deletions(-)
(quoted diff) +0 -0

b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 1d09a72..c9a108f 100644

board/freescale/mx6qsabrelite/mx6qsabrelite.c +2 -0
@@ -25,6 +25,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/mx6x_pins.h>
 #include <asm/arch/iomux-v3.h>
+#include <asm/arch/ccm_regs.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <mmc.h>

@@ -267,6 +269,32 @@ int board_eth_init(bd_t *bis)
 	return 0;
 }

board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 280

Quoted 10 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +9 -0
 
+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int rval = enable_sata_clock();
+	if (rval)
+		return rval ;

Can you keep the return <val>; consistent with the rest of the file? (so avoid return <val>[space];) ... I dunno if this violates some coding style document though. Just a nitpick.

Quoted 55 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +21 -0
+
+	clrsetbits_le32(&iomuxc_regs->gpr[13],
+			IOMUXC_GPR13_SATA_MASK,
+			IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+			|IOMUXC_GPR13_SATA_PHY_7_SATA2M
+			|IOMUXC_GPR13_SATA_SPEED_3G
+			|(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+			|IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+			|IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+			|IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+			|IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+			|IOMUXC_GPR13_SATA_PHY_1_SLOW);
+
+	return 0 ;
+}
+#endif
+
 int board_early_init_f(void)
 {
        setup_iomux_uart();

@@ -283,6 +311,10 @@ int board_init(void)
 	setup_spi();
 #endif
 
+#ifdef CONFIG_CMD_SATA
+	setup_sata();
+#endif
+
        return 0;
 }
(quoted diff) +0 -0

b/include/configs/mx6qsabrelite.h index f52c3c7..1d92dd0 100644

include/configs/mx6qsabrelite.h +13 -0
@@ -71,6 +71,19 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
+#define CONFIG_CMD_SATA
+/*
+ * SATA Configs
+ */
+#ifdef CONFIG_CMD_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
+
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_MII
author
#6 lore raw

PATCH v3 1/1 i.MX6: mx6q_sabrelite: add SATA bindings

Hi Marek,

Quoted 10 lines · Marek Vasut

Dear Eric Nelson,

Quoted 8 lines
Signed-off-by Eric Nelson<[email protected]>

---
V2 has been stripped of the board-independent changes and uses clrsetbits_le32() instead of twiddling bits by hand.

<snip>

Quoted 12 lines

board/freescale/mx6qsabrelite/mx6qsabrelite.c int board_eth_init(bd_t *bis) · line 280

Quoted 7 lines
board/freescale/mx6qsabrelite/mx6qsabrelite.c +7 -0
+int setup_sata(void)
+{
+	struct iomuxc_base_regs *const iomuxc_regs
+		= (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
+	int rval = enable_sata_clock();
+	if (rval)
+		return rval ;

Can you keep the return<val>; consistent with the rest of the file? (so avoid return<val>[space];) ... I dunno if this violates some coding style document though. Just a nitpick.

Can do. I'll update this in V4.