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pinctrl: SPEAr Updates

PATCH Superseded Viresh Kumar 2 participants 8 messages May 3, 2012 – May 7, 2012

Subsystems (3)
Device tree bindings Pin control Spear platform/clock/pinctrl support

v2 of 3 Superseded Latest is v3 →

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Viresh Kumar

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#0 lore raw

v2 cover pinctrl: SPEAr Updates

Hi Linus,

This patchset mainly focuses on providing support to configure SPEAr pads as gpios. For this i have added a gpiolib based driver and few changes in other SPEAr pinctrl drivers.

It also contains minor fixes.

V1->V2:
- Passing gpio node via DT. Patch for this support in gpiolib is
gpiolib: Add of_get_gpio_chip_by_phandle() helper
- Other minor fixes

Viresh Kumar (5):
pinctrl: SPEAr: Don't set all non muxreg bits on pinctrl_disable
pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
pinctrl: SPEAr: Add plgpio driver
pinctrl: SPEAr: Add gpio ranges support
SPEAr: Add plgpio node in device tree dtsi files

 arch/arm/boot/dts/spear1310-evb.dts       |    4 +
 arch/arm/boot/dts/spear1310.dtsi          |   22 +
 arch/arm/boot/dts/spear1340-evb.dts       |    4 +
 arch/arm/boot/dts/spear1340.dtsi          |   21 +
 arch/arm/boot/dts/spear310-evb.dts        |    4 +
 arch/arm/boot/dts/spear310.dtsi           |   15 +
 arch/arm/boot/dts/spear320-evb.dts        |    4 +
 arch/arm/boot/dts/spear320.dtsi           |   16 +
 drivers/pinctrl/spear/Kconfig             |   11 +
 drivers/pinctrl/spear/Makefile            |    1 +
 drivers/pinctrl/spear/pinctrl-plgpio.c    |  738 ++++++++++++++++++++++++++
 drivers/pinctrl/spear/pinctrl-spear.c     |  110 ++++-
 drivers/pinctrl/spear/pinctrl-spear.h     |   15 +
 drivers/pinctrl/spear/pinctrl-spear1310.c |  812 ++++++++++++++++++++++++++++-
 drivers/pinctrl/spear/pinctrl-spear1340.c |    8 +
 drivers/pinctrl/spear/pinctrl-spear300.c  |    2 +
 drivers/pinctrl/spear/pinctrl-spear310.c  |    2 +
 drivers/pinctrl/spear/pinctrl-spear320.c  |    2 +
 drivers/pinctrl/spear/pinctrl-spear3xx.c  |  120 +++++
 19 files changed, 1898 insertions(+), 13 deletions(-)
 create mode 100644 drivers/pinctrl/spear/pinctrl-plgpio.c
Signature · 1 line
1.7.9
author
#1 lore raw

PATCH v2 1/5 pinctrl: SPEAr: Don't set all non muxreg bits on pinctrl_disable

Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/pinctrl/spear/pinctrl-spear.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/pinctrl/spear/pinctrl-spear.c +1 -1
index 5ae50aa..8653569 100644
@@ -244,7 +244,7 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
 			else
 				temp = ~muxreg->val;
 
-			val |= temp;
+			val |= muxreg->mask & temp;
 			pmx_writel(pmx, val, muxreg->reg);
 		}
 	}
Signature · 1 line
1.7.9
author
#2 lore raw

PATCH v2 2/5 pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res

In reply to Viresh Kumar
Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/pinctrl/spear/pinctrl-spear1310.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/pinctrl/spear/pinctrl-spear1310.c +1 -1
index 12b094d..fff168b 100644
@@ -437,7 +437,7 @@ static struct spear_pingroup clcd_pingroup = {
 };
 
 static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
-	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52 };
+	38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
 static struct spear_muxreg clcd_high_res_muxreg[] = {
 	{
 		.reg = PAD_FUNCTION_EN_1,
Signature · 1 line
1.7.9
author
#3 lore raw

PATCH v2 3/5 pinctrl: SPEAr: Add plgpio driver

In reply to Viresh Kumar

Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio. This patch adds plgpio driver for configuring these pads as gpio.

Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/pinctrl/spear/Kconfig          |    7 +
 drivers/pinctrl/spear/Makefile         |    1 +
 drivers/pinctrl/spear/pinctrl-plgpio.c |  738 ++++++++++++++++++++++++++++++++
 3 files changed, 746 insertions(+), 0 deletions(-)
 create mode 100644 drivers/pinctrl/spear/pinctrl-plgpio.c
drivers/pinctrl/spear/Kconfig +7 -0
index 91558791..6f9a1e8 100644
@@ -41,4 +41,11 @@ config PINCTRL_SPEAR1340
 	depends on MACH_SPEAR1340
 	select PINCTRL_SPEAR
 
+config PINCTRL_SPEAR_PLGPIO
+	bool "SPEAr SoC PLGPIO Controller"
+	depends on GPIOLIB && PINCTRL_SPEAR
+	help
+	  Say yes here to support PLGPIO controller on ST Microelectronics SPEAr
+	  SoCs.
+
 endif
drivers/pinctrl/spear/Makefile +1 -0
index b28a7ba..0e400eb 100644
@@ -1,5 +1,6 @@
 # SPEAr pinmux support
 
+obj-$(CONFIG_PINCTRL_SPEAR_PLGPIO)	+= pinctrl-plgpio.o
 obj-$(CONFIG_PINCTRL_SPEAR)	+= pinctrl-spear.o
 obj-$(CONFIG_PINCTRL_SPEAR3XX)	+= pinctrl-spear3xx.o
 obj-$(CONFIG_PINCTRL_SPEAR300)	+= pinctrl-spear300.o
drivers/pinctrl/spear/pinctrl-plgpio.c new file +738 -0

738 lines not on this page · raw message

Signature · 1 line
1.7.9
author
#4 lore raw

PATCH v2 4/5 pinctrl: SPEAr: Add gpio ranges support

In reply to Viresh Kumar

Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio. This patch gpio enable support for SPEAr pinctrl drivers.

Signed-off-by Viresh Kumar <[email protected]>
---
 drivers/pinctrl/spear/Kconfig             |    4 +
 drivers/pinctrl/spear/pinctrl-spear.c     |  110 ++++-
 drivers/pinctrl/spear/pinctrl-spear.h     |   15 +
 drivers/pinctrl/spear/pinctrl-spear1310.c |  810 +++++++++++++++++++++++++++++
 drivers/pinctrl/spear/pinctrl-spear1340.c |    8 +
 drivers/pinctrl/spear/pinctrl-spear300.c  |    2 +
 drivers/pinctrl/spear/pinctrl-spear310.c  |    2 +
 drivers/pinctrl/spear/pinctrl-spear320.c  |    2 +
 drivers/pinctrl/spear/pinctrl-spear3xx.c  |  120 +++++
 9 files changed, 1061 insertions(+), 12 deletions(-)
drivers/pinctrl/spear/Kconfig +4 -0
index 6f9a1e8..04d93e6 100644
@@ -25,21 +25,25 @@ config PINCTRL_SPEAR310
 	bool "ST Microelectronics SPEAr310 SoC pin controller driver"
 	depends on MACH_SPEAR310
 	select PINCTRL_SPEAR3XX
+	select PINCTRL_SPEAR_PLGPIO
 
 config PINCTRL_SPEAR320
 	bool "ST Microelectronics SPEAr320 SoC pin controller driver"
 	depends on MACH_SPEAR320
 	select PINCTRL_SPEAR3XX
+	select PINCTRL_SPEAR_PLGPIO
 
 config PINCTRL_SPEAR1310
 	bool "ST Microelectronics SPEAr1310 SoC pin controller driver"
 	depends on MACH_SPEAR1310
 	select PINCTRL_SPEAR
+	select PINCTRL_SPEAR_PLGPIO
 
 config PINCTRL_SPEAR1340
 	bool "ST Microelectronics SPEAr1340 SoC pin controller driver"
 	depends on MACH_SPEAR1340
 	select PINCTRL_SPEAR
+	select PINCTRL_SPEAR_PLGPIO
 
 config PINCTRL_SPEAR_PLGPIO
 	bool "SPEAr SoC PLGPIO Controller"
drivers/pinctrl/spear/pinctrl-spear.c +98 -12

164 lines not on this page · raw message

drivers/pinctrl/spear/pinctrl-spear.h +15 -0
index 9155783..dd0d88e 100644
@@ -46,6 +46,12 @@ struct spear_muxreg {
 	u32 val;
 };
 
+struct spear_gpio_pingroup {
+	const unsigned *pins;
+	unsigned npins;
+	struct spear_muxreg muxreg;
+};
+
 /**
  * struct spear_modemux - SPEAr mode mux configuration
  * @modes: mode ids supported by this group of muxregs

@@ -100,6 +106,9 @@ struct spear_function {
  * @nfunctions: The numbmer of entries in @functions.
  * @groups: An array describing all pin groups the pin SoC supports.
  * @ngroups: The numbmer of entries in @groups.
+ * @ranges: PLGPIO ranges for the machine
+ * @gpio_pingroups: gpio pingroups
+ * @ngpio_pingroups: gpio pingroups count
  *
  * @modes_supported: Does SoC support modes
  * @mode: mode configured from probe

@@ -113,6 +122,9 @@ struct spear_pinctrl_machdata {
 	unsigned nfunctions;
 	struct spear_pingroup **groups;
 	unsigned ngroups;
+	struct pinctrl_gpio_range *ranges;
+	struct spear_gpio_pingroup *gpio_pingroups;
+	unsigned ngpio_pingroups;
 
 	bool modes_supported;
 	u16 mode;

@@ -136,6 +148,9 @@ struct spear_pmx {
 
 /* exported routines */
 void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
+void __devinit
+pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
+		unsigned count, u16 reg);
 int __devinit spear_pinctrl_probe(struct platform_device *pdev,
 		struct spear_pinctrl_machdata *machdata);
 int __devexit spear_pinctrl_remove(struct platform_device *pdev);
drivers/pinctrl/spear/pinctrl-spear1310.c +810 -0

822 lines not on this page · raw message

drivers/pinctrl/spear/pinctrl-spear1340.c +8 -0
index a8ab2a6..9380507 100644
@@ -1934,6 +1934,13 @@ static struct spear_function *spear1340_functions[] = {
 	&sata_function,
 };
 
+static struct pinctrl_gpio_range spear1340_plgpio_range = {
+	.name		= "SPEAr1340 PLGPIO",
+	.id		= 0,
+	.pin_base	= 0,
+	.npins		= ARRAY_SIZE(spear1340_pins),
+};
+
 static struct spear_pinctrl_machdata spear1340_machdata = {
 	.pins = spear1340_pins,
 	.npins = ARRAY_SIZE(spear1340_pins),

@@ -1941,6 +1948,7 @@ static struct spear_pinctrl_machdata spear1340_machdata = {
 	.ngroups = ARRAY_SIZE(spear1340_pingroups),
 	.functions = spear1340_functions,
 	.nfunctions = ARRAY_SIZE(spear1340_functions),
+	.ranges = &spear1340_plgpio_range,
 	.modes_supported = false,
 };
drivers/pinctrl/spear/pinctrl-spear300.c +2 -0
index 9c82a35..faa9169 100644
@@ -661,6 +661,8 @@ static int __devinit spear300_pinctrl_probe(struct platform_device *pdev)
 	spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);
 	spear3xx_machdata.functions = spear300_functions;
 	spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);
+	spear3xx_machdata.gpio_pingroups = NULL;
+	spear3xx_machdata.ngpio_pingroups = 0;
 
 	spear3xx_machdata.modes_supported = true;
 	spear3xx_machdata.pmx_modes = spear300_pmx_modes;
drivers/pinctrl/spear/pinctrl-spear310.c +2 -0
index 1a97076..f393639 100644
@@ -388,6 +388,8 @@ static int __devinit spear310_pinctrl_probe(struct platform_device *pdev)
 	spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions);
 
 	pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+	pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
+			spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
 
 	spear3xx_machdata.modes_supported = false;
drivers/pinctrl/spear/pinctrl-spear320.c +2 -0
index de726e6..e8c2d65 100644
@@ -3427,6 +3427,8 @@ static int __devinit spear320_pinctrl_probe(struct platform_device *pdev)
 	spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes);
 
 	pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG);
+	pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups,
+			spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG);
 
 	ret = spear_pinctrl_probe(pdev, &spear3xx_machdata);
 	if (ret)
drivers/pinctrl/spear/pinctrl-spear3xx.c +120 -0

127 lines not on this page · raw message

Signature · 1 line
1.7.9
author
#5 lore raw

PATCH v2 4/5 pinctrl: SPEAr: Add gpio ranges support

Review

Quoted 10 lines · Viresh KUMAR
(quoted diff) +10 -0
+static int gpio_request_endisable(struct pinctrl_dev *pctldev,
+               struct pinctrl_gpio_range *range, unsigned offset, bool enable)
+{
+       struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
+       struct spear_gpio_pingroup *gpio_pingroup;
+
+       gpio_pingroup = get_gpio_pingroup(pmx, offset);
+       if (PTR_ERR(gpio_pingroup))
+               return PTR_ERR(gpio_pingroup);
+

Minor fixup:

---
 drivers/pinctrl/spear/pinctrl-spear.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/pinctrl/spear/pinctrl-spear.c +1 -1
index 2596fa6..c0c3b28 100644
@@ -316,7 +316,7 @@ static int gpio_request_endisable(struct pinctrl_dev *pctldev,
        struct spear_gpio_pingroup *gpio_pingroup;
 
        gpio_pingroup = get_gpio_pingroup(pmx, offset);
-       if (PTR_ERR(gpio_pingroup))
+       if (IS_ERR(gpio_pingroup))
                return PTR_ERR(gpio_pingroup);
 
        if (gpio_pingroup) {
Signature · 1 line
viresh
author
#6 lore raw

PATCH v2 5/5 SPEAr: Add plgpio node in device tree dtsi files

In reply to Viresh Kumar
Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/boot/dts/spear1310-evb.dts |    4 ++++
 arch/arm/boot/dts/spear1310.dtsi    |   22 ++++++++++++++++++++++
 arch/arm/boot/dts/spear1340-evb.dts |    4 ++++
 arch/arm/boot/dts/spear1340.dtsi    |   21 +++++++++++++++++++++
 arch/arm/boot/dts/spear310-evb.dts  |    4 ++++
 arch/arm/boot/dts/spear310.dtsi     |   15 +++++++++++++++
 arch/arm/boot/dts/spear320-evb.dts  |    4 ++++
 arch/arm/boot/dts/spear320.dtsi     |   16 ++++++++++++++++
 8 files changed, 90 insertions(+), 0 deletions(-)
arch/arm/boot/dts/spear1310-evb.dts +4 -0
index 8a51303..c090833 100644
@@ -181,6 +181,10 @@
 			       status = "okay";
 			};
 
+			gpio at d8400000 {
+			       status = "okay";
+			};
+
 			i2c0: i2c at e0280000 {
 			       status = "okay";
 			};
arch/arm/boot/dts/spear1310.dtsi +22 -0
index 9e61da4..c63bba2 100644
@@ -70,6 +70,12 @@
 			status = "disabled";
 		};
 
+		pinmux at e0700000 {
+			compatible = "st,spear1310-pinmux";
+			reg = <0xe0700000 0x1000>;
+			gpio-phandle = <&gpiopinctrl>;
+		};
+
 		spi1: spi at 5d400000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x5d400000 0x1000>;

@@ -179,6 +185,22 @@
 			thermal at e07008c4 {
 				st,thermal-flags = <0x7000>;
 			};
+
+			gpiopinctrl: gpio at d8400000 {
+				compatible = "st,spear-plgpio";
+				reg = <0xd8400000 0x1000>;
+				interrupts = <0 132 0x4>;
+				status = "disabled";
+
+				st-plgpio,ngpio = <246>;
+				st-plgpio,enb-reg = <0xd0>;
+				st-plgpio,wdata-reg = <0x90>;
+				st-plgpio,dir-reg = <0xb0>;
+				st-plgpio,ie-reg = <0x30>;
+				st-plgpio,rdata-reg = <0x70>;
+				st-plgpio,mis-reg = <0x10>;
+				st-plgpio,eit-reg = <0x50>;
+			};
 		};
 	};
 };
arch/arm/boot/dts/spear1340-evb.dts +4 -0
index 60e0e12..0bf9d8f 100644
@@ -193,6 +193,10 @@
 			       status = "okay";
 			};
 
+			gpio at e2800000 {
+			       status = "okay";
+			};
+
 			i2c0: i2c at e0280000 {
 			       status = "okay";
 			};
arch/arm/boot/dts/spear1340.dtsi +21 -0
index a26fc47..e5d4e05 100644
@@ -24,6 +24,12 @@
 			status = "disabled";
 		};
 
+		pinmux at e0700000 {
+			compatible = "st,spear1340-pinmux";
+			reg = <0xe0700000 0x1000>;
+			gpio-phandle = <&gpiopinctrl>;
+		};
+
 		spi1: spi at 5d400000 {
 			compatible = "arm,pl022", "arm,primecell";
 			reg = <0x5d400000 0x1000>;

@@ -51,6 +57,21 @@
 			thermal at e07008c4 {
 				st,thermal-flags = <0x2a00>;
 			};
+
+			gpiopinctrl: gpio at e2800000 {
+				compatible = "st,spear-plgpio";
+				reg = <0xe2800000 0x1000>;
+				interrupts = <0 139 0x4>;
+				status = "disabled";
+
+				st-plgpio,ngpio = <250>;
+				st-plgpio,wdata-reg = <0x40>;
+				st-plgpio,dir-reg = <0x00>;
+				st-plgpio,ie-reg = <0x80>;
+				st-plgpio,rdata-reg = <0x20>;
+				st-plgpio,mis-reg = <0xa0>;
+				st-plgpio,eit-reg = <0x60>;
+			};
 		};
 	};
 };
arch/arm/boot/dts/spear310-evb.dts +4 -0
index a551ee0..12ac5ed 100644
@@ -148,6 +148,10 @@
 			       status = "okay";
 			};
 
+			gpio at b4000000 {
+			       status = "okay";
+			};
+
 			i2c0: i2c at d0180000 {
 			       status = "okay";
 			};
arch/arm/boot/dts/spear310.dtsi +15 -0
index e47081c..fddf84c 100644
@@ -25,6 +25,7 @@
 		pinmux at b4000000 {
 			compatible = "st,spear310-pinmux";
 			reg = <0xb4000000 0x1000>;
+			gpio-phandle = <&gpiopinctrl>;
 		};
 
 		fsmc: flash at 44000000 {

@@ -75,6 +76,20 @@
 				reg = <0xb2200000 0x1000>;
 				status = "disabled";
 			};
+
+			gpiopinctrl: gpio at b4000000 {
+				compatible = "st,spear-plgpio";
+				reg = <0xb4000000 0x1000>;
+				status = "disabled";
+
+				st-plgpio,ngpio = <102>;
+				st-plgpio,enb-reg = <0x10>;
+				st-plgpio,wdata-reg = <0x20>;
+				st-plgpio,dir-reg = <0x30>;
+				st-plgpio,ie-reg = <0x50>;
+				st-plgpio,rdata-reg = <0x40>;
+				st-plgpio,mis-reg = <0x60>;
+			};
 		};
 	};
 };
arch/arm/boot/dts/spear320-evb.dts +4 -0
index 26366f4..a2115aa 100644
@@ -166,6 +166,10 @@
 			       status = "okay";
 			};
 
+			gpio at b3000000 {
+			       status = "okay";
+			};
+
 			i2c0: i2c at d0180000 {
 			       status = "okay";
 			};
arch/arm/boot/dts/spear320.dtsi +16 -0
index 5372ca3..9adac5b 100644
@@ -24,6 +24,7 @@
 		pinmux at b3000000 {
 			compatible = "st,spear320-pinmux";
 			reg = <0xb3000000 0x1000>;
+			gpio-phandle = <&gpiopinctrl>;
 		};
 
 		clcd at 90000000 {

@@ -90,6 +91,21 @@
 				reg = <0xa4000000 0x1000>;
 				status = "disabled";
 			};
+
+			gpiopinctrl: gpio at b3000000 {
+				compatible = "st,spear-plgpio";
+				reg = <0xb3000000 0x1000>;
+				status = "disabled";
+
+				st-plgpio,ngpio = <102>;
+				st-plgpio,enb-reg = <0x24>;
+				st-plgpio,wdata-reg = <0x34>;
+				st-plgpio,dir-reg = <0x44>;
+				st-plgpio,ie-reg = <0x64>;
+				st-plgpio,rdata-reg = <0x54>;
+				st-plgpio,mis-reg = <0x84>;
+				st-plgpio,eit-reg = <0x94>;
+			};
 		};
 	};
 };
Signature · 1 line
1.7.9
#7 lore raw

v2 cover pinctrl: SPEAr Updates

In reply to Viresh Kumar
Quoted 3 lines · Viresh Kumar

- Passing gpio node via DT. Patch for this support in gpiolib is ?gpiolib: Add of_get_gpio_chip_by_phandle() helper
- Other minor fixes

Clever, if you fix the macro I commented on for v1, you can add my

Acked-by Linus Walleij <[email protected]>

for this V2 series.

Yours,
Linus Walleij